JPH0714781A - Formation of thin film - Google Patents
Formation of thin filmInfo
- Publication number
- JPH0714781A JPH0714781A JP15327993A JP15327993A JPH0714781A JP H0714781 A JPH0714781 A JP H0714781A JP 15327993 A JP15327993 A JP 15327993A JP 15327993 A JP15327993 A JP 15327993A JP H0714781 A JPH0714781 A JP H0714781A
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- Prior art keywords
- film
- forming
- refractory metal
- thin film
- semiconductor device
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高融点金属もしくは高
融点金属シリサイドを電極配線材料として用いた半導体
装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a refractory metal or refractory metal silicide as an electrode wiring material.
【０００２】[0002]
【従来の技術】半導体装置の配線材料には、従来、アル
ミニウムもしくはアルミニウム合金が用いられてきた。
しかし、半導体装置の微細化にともなって、化学気相成
長法（ＣＶＤ法）によって形成された、信頼性の高い配
線材料であるタングステン（Ｗ）等の高融点金属が一部
の配線に用いられるようになった。高融点金属のＣＶＤ
法としては、高融点金属のハロゲン化物やカルボニル化
合物を、モノシラン（ＳｉＨ4）によって還元する方法
（以下ＳｉＨ4還元法と示す）や、特開平４−２１１１
２３号公報に記載されているように、高融点金属のハロ
ゲン化物やカルボニル化合物を、２フッ化シラン（Ｓｉ
Ｈ2Ｆ2）によって還元する方法（以下従来のＳｉＨ2Ｆ2
還元法と呼ぶ）が用いられてきている。2. Description of the Related Art Conventionally, aluminum or aluminum alloy has been used as a wiring material for semiconductor devices.
However, with the miniaturization of semiconductor devices, refractory metals such as tungsten (W), which is a highly reliable wiring material, formed by chemical vapor deposition (CVD method) are used for some wirings. It became so. CVD of refractory metals
Examples of the method include a method of reducing a halide or a carbonyl compound of a refractory metal with monosilane (SiH 4 ) (hereinafter referred to as SiH 4 reduction method), and JP-A-4-2111.
As described in Japanese Patent No. 23, the halogenated or carbonyl compound of a refractory metal is treated with difluorosilane (Si).
H 2 F 2 ) reduction method (hereinafter referred to as conventional SiH 2 F 2
The reduction method) has been used.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、ＳｉＨ
4還元法では段差被覆性が悪く、直径１μｍ以下の微細
な接続孔に高融点金属を埋め込むことはできないという
欠点があった。また、従来のＳｉＨ2Ｆ2還元法によって
形成した高融点金属膜の表面には膜厚の２０％程度の凹
凸が存在した。そのため、０．３μｍ以下の微細な接続
孔内に高融点金属膜を形成すると、膜形成の途中で接続
孔側壁に凸部が発生し、成長することが見出された。そ
の結果、凸部により接続孔が塞がれてしまい、その下部
では膜の成長が停止してしまうので、接続孔内の膜の段
差被覆性は悪くなり、特に０．３μｍ以下の微細孔で顕
著になる。However, SiH
The 4 reduction method has a drawback that the step coverage is poor and the refractory metal cannot be embedded in fine connection holes with a diameter of 1 μm or less. Further, the refractory metal film formed by the conventional SiH 2 F 2 reduction method had irregularities of about 20% of the film thickness. Therefore, it has been found that when a refractory metal film is formed in a fine connection hole of 0.3 μm or less, a convex portion is generated on the side wall of the connection hole during the film formation and grows. As a result, the connection hole is blocked by the convex portion, and the film growth stops at the lower part of the connection hole. Therefore, the step coverage of the film in the connection hole is deteriorated, and especially in the case of a fine hole of 0.3 μm or less. It will be noticeable.
【０００４】本発明は、高融点金属膜の表面が平坦で、
０．３μｍ以下の微細な接続孔にさえも段差被覆性の良
い高融点金属膜を形成することができる方法を提供する
ことを目的とする。According to the present invention, the refractory metal film has a flat surface,
It is an object of the present invention to provide a method capable of forming a refractory metal film having good step coverage even in a fine connection hole of 0.3 μm or less.
【０００５】[0005]
【課題を解決するための手段】上記目的は、化学気相成
長法により高融点金属もしくは高融点金属シリサイドを
形成する還元ガスとして、純度が９５ｍｏｌ％以上のＳ
ｉＨ2Ｆ2ガスを用いることによって達成される。SUMMARY OF THE INVENTION The above-mentioned object is to use S having a purity of 95 mol% or more as a reducing gas for forming refractory metal or refractory metal silicide by chemical vapor deposition.
This is achieved by using iH 2 F 2 gas.
【０００６】[0006]
【作用】直径０．３μｍ、深さ０．５μｍの微細接続孔
に高融点金属としてＷを埋め込んだ例を用いて説明す
る。まず、従来のＳｉＨ2Ｆ2還元法で用いられたＳｉＨ
2Ｆ2について、赤外分光法により組成分析を行なった。
初めに、圧力計を備えた容器にＳｉＨ4を導入し、吸光
度とＳｉＨ4の圧力との関係を求めた。同様の方法で、
ＳｉＨＦ3およびＳｉＦ4について、吸光度と圧力との関
係を求めた。その後、容器内にＳｉＨ2Ｆ2を導入し、赤
外分析を行なった。得られた赤外スペクトルの一例を図
１に示す。不純物ガスに対応するピークの吸光度の大き
さから各ガスの分圧が得られる。全圧力から不純物ガス
の分圧の和を引いた値がＳｉＨ2Ｆ2の分圧となる。Ｓｉ
Ｈ2Ｆ2および不純物ガスの分圧と全圧力の比が各ガスの
濃度となる。こうして得た分析の結果を表１に示す。こ
こで各ガスの濃度は、「ｍｏｌ％」、すなわち、分子数
の割合の百分率で表した。The operation will be described using an example in which W as a refractory metal is embedded in a fine connection hole having a diameter of 0.3 μm and a depth of 0.5 μm. First, SiH used in the conventional SiH 2 F 2 reduction method
The composition of 2 F 2 was analyzed by infrared spectroscopy.
First, SiH 4 was introduced into a container equipped with a pressure gauge, and the relationship between the absorbance and the pressure of SiH 4 was determined. In a similar way,
The relationship between absorbance and pressure was determined for SiHF 3 and SiF 4 . After that, SiH 2 F 2 was introduced into the container and infrared analysis was performed. An example of the obtained infrared spectrum is shown in FIG. The partial pressure of each gas can be obtained from the magnitude of the peak absorbance corresponding to the impurity gas. The value obtained by subtracting the sum of the partial pressures of the impurity gas from the total pressure is the partial pressure of SiH 2 F 2 . Si
The ratio of the partial pressure of H 2 F 2 and the impurity gas to the total pressure is the concentration of each gas. The results of the analysis thus obtained are shown in Table 1. Here, the concentration of each gas is represented by “mol%”, that is, the percentage of the number of molecules.
【０００７】[0007]
【表１】 [Table 1]
【０００８】以上の結果から、従来の還元ガスであるＳ
ｉＨ2Ｆ2の純度は約７０ｍｏｌ％であり、不純物として
ＳｉＨ4およびＳｉＨ4のフッ素置換体ＳｉＨＦ3、Ｓｉ
Ｆ4が混入しており、なかでもＳｉＨＦ3が特に多いこと
が分かる。混入している不純物としては、ＳｉＨ4およ
び３フッ化シラン（ＳｉＨＦ3）や４フッ化珪素（Ｓｉ
Ｆ4）等、ＳｉＨ4のフッ素置換体が多く、特にＳｉＨＦ
3が大部分をしめている。さらに、純度を向上させた４
種のＳｉＨ2Ｆ2を用意し、これらのガスについても同様
に赤外分光法により組成分析を行なった。その結果も表
１に示した。From the above results, the conventional reducing gas S
The purity of iH 2 F 2 is about 70 mol%, and SiH 4 and SiH 4 are fluorine-substituted compounds SiHF 3 and Si as impurities.
It can be seen that F 4 is mixed, and especially SiHF 3 is particularly large. Impurities mixed in include SiH 4 and trifluorosilane (SiHF 3 ) or silicon tetrafluoride (Si
F 4) and the like, many fluorine substitution products SiH 4, particularly SiHF
3 is the majority. Further improved purity 4
Seed SiH 2 F 2 was prepared, and the composition analysis was similarly performed on these gases by infrared spectroscopy. The results are also shown in Table 1.
【０００９】次に、これらの純度の異なるＳｉＨ2Ｆ2を
用いて接続孔の埋め込みを行ない、ＳｉＨ2Ｆ2の純度と
Ｗ膜の平坦性、段差被覆性との関係を調べた。図２に示
すように、ｐ型１０Ωｃｍ（１００）Ｓｉ基板１上に公
知のＬＯＣＯＳ工程により、フィールド酸化膜２を形成
した後、Ａｓイオンを公知のイオン打込み法によってド
ーズ量１×1015ｃｍ-2の条件で打込んだ後、所定の熱処
理（以下アニールと呼ぶ）によってｎ＋型拡散層３を形
成した。その後、厚さ５００ｎｍのＰＳＧ（Ｐｈｏｓｐ
ｈｏｓｉｌｉｃａｔｅ Ｇｌａｓｓ）膜４をＣＶＤ法で
形成し、次いでＮ2雰囲気中でアニールを行ない、ＰＳ
Ｇ膜４の緻密化を行なった。その後、通常のホトリソグ
ラフィー技術を用いて、直径０．３μｍの垂直形状の接
続孔を開口した。ついで、接着層としてスパッタ法によ
り接続孔の外の平坦部での厚さが３０ｎｍのＷ膜５を形
成した。Next, these SiH 2 F 2 having different purities were used to fill the contact holes, and the relationship between the purity of SiH 2 F 2 and the flatness and step coverage of the W film was investigated. As shown in FIG. 2, after the field oxide film 2 is formed on the p-type 10 Ωcm (100) Si substrate 1 by the known LOCOS process, the dose of As ions is 1 × 10 15 cm − by the known ion implantation method. After implanting under the condition of 2, the n + type diffusion layer 3 was formed by a predetermined heat treatment (hereinafter referred to as annealing). After that, a PSG (Phosp
a silicate glass) film 4 is formed by a CVD method and then annealed in an N 2 atmosphere to form a PS film.
The G film 4 was densified. After that, a normal photolithography technique was used to open a vertical connection hole having a diameter of 0.3 μm. Then, a W film 5 having a thickness of 30 nm in the flat portion outside the connection hole was formed as an adhesive layer by a sputtering method.
【００１０】つぎに、図３に示すように、４種類のＳｉ
Ｈ2Ｆ2を用いてＷ膜６を形成し、段差被覆率及び平坦性
の指標となる「表面凹凸／平均膜厚」を調べた。ＣＶＤ
条件は、基板温度＝４００℃、ＷＦ6流量＝１００ｓｃ
ｃｍ、ＳｉＨ2Ｆ2流量＝４００ｓｃｃｍ、Ａｒ流量＝３
００ｓｃｃｍ、全圧＝０．５Ｔｏｒｒであった。Next, as shown in FIG. 3, four types of Si
The W film 6 was formed using H 2 F 2 and the “surface unevenness / average film thickness” which is an index of step coverage and flatness was examined. CVD
The conditions are: substrate temperature = 400 ° C., WF 6 flow rate = 100 sc
cm, SiH 2 F 2 flow rate = 400 sccm, Ar flow rate = 3
The pressure was 00 sccm and the total pressure was 0.5 Torr.
【００１１】ここで、図４に示すように、段差被覆率
は、孔の中でＷ膜６の最も薄い部分の膜厚ａと孔の外の
平坦部に形成されたＷ膜６の平均膜厚ｔの比 ａ／ｔ
と定義した。また、表面凹凸は、走査電子顕微鏡によっ
て幅１０μｍの領域にわたって調べた場合の最大膜厚ｔ
ｍａｘと最小膜厚ｔｍｉｎの差とした。As shown in FIG. 4, the step coverage is the average film thickness a of the thinnest part of the W film 6 in the hole and the average film of the W film 6 formed in the flat part outside the hole. Ratio of thickness t a / t
Was defined. In addition, the surface unevenness has the maximum film thickness t when it is examined with a scanning electron microscope over a region having a width of 10 μm.
The difference between the max and the minimum film thickness tmin was set.
【００１２】平坦性、段差被覆性を調べた結果は純度と
ともに表１に示してある。また、純度と平坦性との関係
を図５に示した。ＳｉＨ2Ｆ2の純度は９５ｍｏｌ％以上
の場合、表面の平坦性は著しく改善されたことがわか
る。なお、純度が９８ｍｏｌ％以上であれば、表面凹凸
／平均膜厚は１０％となり、望ましい平坦性が得られ
る。また表１より、Ｗ膜表面が平坦になるのに対応し
て、段差被覆性が高くなっていることがわかる。The results of examining the flatness and the step coverage are shown in Table 1 together with the purity. Further, the relationship between the purity and the flatness is shown in FIG. It can be seen that the surface flatness was remarkably improved when the purity of SiH 2 F 2 was 95 mol% or more. If the purity is 98 mol% or more, the surface roughness / average film thickness is 10%, and the desired flatness is obtained. Further, it can be seen from Table 1 that the step coverage is increased corresponding to the flatness of the W film surface.
【００１３】さらに、＃４のＳｉＨ2Ｆ2を用いた場合、
直径０．３μｍ、深さ１μｍの接続孔に対して、８０％
以上の段差被覆率を得ることができた。Further, when # 4 SiH 2 F 2 is used,
80% for a connection hole with a diameter of 0.3 μm and a depth of 1 μm
The above step coverage can be obtained.
【００１４】次に、最も純度が高い＃４のＳｉＨ2Ｆ2中
にＳｉＨＦ3を添加し種々の濃度に調整した混合ガスを
用いて、図２のスパッタ−Ｗ膜５上にＣＶＤ−Ｗ膜６を
形成する実験を行ない（図３）、不純物のなかで特に濃
度の高いＳｉＨＦ3の影響を調べた。ＣＶＤ条件は、基
板温度＝４００℃、ＷＦ6流量＝２０ｓｃｃｍ、混合ガ
ス流量＝８０ｓｃｃｍ、Ａｒ流量＝４００ｓｃｃｍ、全
圧＝０．３Ｔｏｒｒであった。Ｗ膜の堆積速度を調べた
ところ、図６に示すように、ＳｉＨＦ3濃度が高くなる
と堆積速度が低下することが分かった。堆積速度の低下
に伴う生産性の低下を防止するため、堆積速度はＳｉＨ
Ｆ3濃度が０ｍｏｌ％の場合の値（外挿値）の８５％以
上、望ましくは９５％以上であると良い。そのために
は、ＳｉＨ2Ｆ2中のＳｉＨＦ3濃度を４ｍｏｌ％以下、
望ましくは１．４ｍｏｌ％以下にすることが必要であ
る。Next, a CVD-W film is formed on the sputter-W film 5 in FIG. 2 by using a mixed gas in which SiHF 3 of the highest purity # 4 SiH 2 F 2 is added and adjusted to various concentrations. 6 was conducted (FIG. 3) to examine the effect of SiHF 3 having a particularly high concentration among impurities. The CVD conditions were: substrate temperature = 400 ° C., WF 6 flow rate = 20 sccm, mixed gas flow rate = 80 sccm, Ar flow rate = 400 sccm, total pressure = 0.3 Torr. When the deposition rate of the W film was examined, it was found that the deposition rate decreased as the SiHF 3 concentration increased, as shown in FIG. The deposition rate is set to SiH to prevent a decrease in productivity due to a decrease in deposition rate.
The F 3 concentration is 85% or more, preferably 95% or more of the value (extrapolated value) when it is 0 mol%. For that purpose, the SiHF 3 concentration in SiH 2 F 2 is 4 mol% or less,
Desirably, it should be 1.4 mol% or less.
【００１５】従来用いられていたＳｉＨ2Ｆ2ガスのよう
に、ＳｉＨ2Ｆ2中にＳｉＨＦ3やＳｉＦ4が混入している
と、成長している高融点金属膜表面にこれらの分子が吸
着する。それにより、原料ガス分子や反応中間体の表面
移動が阻害されるため、膜表面に凹凸が生じていた。そ
の結果、微細な接続孔における段差被覆性が悪くなって
いた。従って、本発明のようにＳｉＨＦ3やＳｉＦ4等の
不純物ガス混入が非常に少ないＳｉＨ2Ｆ2ガスを用いれ
ば、平坦性、段差被覆性に優れた高融点金属膜が成長す
る。When SiHF 3 or SiF 4 is mixed in SiH 2 F 2 like the conventionally used SiH 2 F 2 gas, these molecules are adsorbed on the surface of the growing refractory metal film. To do. As a result, the surface migration of the raw material gas molecules and the reaction intermediate is hindered, so that the film surface is uneven. As a result, the step coverage in the fine connection holes is poor. Therefore, when the SiH 2 F 2 gas containing very little impurity gas such as SiHF 3 or SiF 4 is used as in the present invention, a refractory metal film excellent in flatness and step coverage is grown.
【００１６】[0016]
【実施例】（実施例１）高融点金属としてＷを電極配線
材料に用いてＭＯＳ−ＦＥＴ集積回路を作成し、Ｗ形成
に用いたＳｉＨ2Ｆ2の純度の素子特性に与える影響につ
いて調べた。用いたＳｉＨ2Ｆ2は、最も純度が高い＃４
のＳｉＨ2Ｆ2と純度の低い従来のＳｉＨ2Ｆ2である。図
７乃至図１２は、本実施例で作成したＭＯＳ−ＦＥＴ集
積回路の製造工程を示す。まず、図７に示すように、ｐ
型（１００）Ｓｉ基板１上に、フィールド酸化膜２、厚
さ８ｎｍのゲート酸化膜８を形成した後、多結晶シリコ
ン膜９（厚さ３００ｎｍ）を低圧ＣＶＤ法で堆積させ、
不純物を添加し低抵抗化した後、ゲート電極形状に通常
のホトリソグラフィー技術を用いてパターニングした。
次いで、多結晶シリコンゲート電極９をマスクとして、
Ａｓイオンをドーズ量１×1015ｃｍ￣2の条件で打込ん
だ後、アニールを行ない、ソース・ドレイン領域１０を
形成した。その後、ＨＬＤ（Ｈｉｇｈ ｔｅｍｐｅｒａ
ｔｕｒｅ Ｌｏｗ ｐｒｅｓｓｕｒｅ Ｄｅｃｏｍｐｏ
ｓｉｔｉｏｎ）のＳｉ酸化膜１１をＣＶＤ法で堆積させ
た後、全面ドライエッチングにより、ゲート周辺部にの
みＨＬＤ膜１１を残し、いわゆるＬＤＤ（Ｌｉｇｈｔｌ
ｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造を形成した。Example 1 A MOS-FET integrated circuit was prepared by using W as a refractory metal as an electrode wiring material, and the effect of the purity of SiH 2 F 2 used for forming W on the device characteristics was examined. . The SiH 2 F 2 used is the highest purity # 4.
SiH 2 F 2 and conventional SiH 2 F 2 with low purity. 7 to 12 show the manufacturing process of the MOS-FET integrated circuit created in this embodiment. First, as shown in FIG.
After forming a field oxide film 2 and a gate oxide film 8 having a thickness of 8 nm on a mold (100) Si substrate 1, a polycrystalline silicon film 9 (thickness 300 nm) is deposited by a low pressure CVD method,
After adding impurities to reduce the resistance, the gate electrode shape was patterned by using a normal photolithography technique.
Then, using the polycrystalline silicon gate electrode 9 as a mask,
After implanting As ions at a dose of 1 × 10 15 cm¯ 2, annealing is performed to form the source and drain regions 10. After that, HLD (High tempera
true Low pressure Decompo
(state) Si oxide film 11 is deposited by the CVD method, and then the entire surface is dry-etched to leave the HLD film 11 only in the peripheral portion of the gate, so-called LDD (Lightl).
y Doped Drain) structure was formed.
【００１７】その後、図８に示すように、厚さ７００ｎ
ｍのＢＰＳＧ（Ｂｏｒｏｎ ｄｏｐｅｄ ＰＳＧ）膜１
２をＣＶＤ法で堆積させた後、Ｎ2雰囲気中でアニール
を行ない、ＢＰＳＧ膜１２の緻密化を行なった後、通常
のホトリソグラフィー技術を用いて直径０.３μｍの接
続孔１３を形成した。After that, as shown in FIG.
m BPSG (Boron doped PSG) film 1
2 was deposited by the CVD method and then annealed in an N 2 atmosphere to densify the BPSG film 12, and then a connection hole 13 having a diameter of 0.3 μm was formed by using a normal photolithography technique.
【００１８】次に、図９に示すように、ＳｉＨ2Ｆ2還元
ＣＶＤ法により厚さ５００ｎｍのＷ／タングステンシリ
サイド（以下ＷＳｉｘと記す）積層膜１４を堆積した。
ＣＶＤ条件は、最初の１分間は、ＷＦ6、ＳｉＨ2Ｆ2お
よびＡｒの流量をそれぞれ５，１０００，３００ｓｃｃ
ｍ、全圧は０．５Ｔｏｒｒとし、温度は３５０℃として
ＷＳｉｘを形成した。その後、ＷＦ6、ＳｉＨ2Ｆ2およ
びＡｒの流量をそれぞれ１００，４００，３００ｓｃｃ
ｍとしＷを形成した。続いて、通常のホトリソグラフィ
ー技術を用いてＷ／ＷＳｉｘ積層膜１４を配線形状に加
工した。Ｗ／ＷＳｉｘ積層膜１４は下地のＢＰＳＧ膜１
２との接着性が良好であった。本実施例によれば、Ｗ膜
の形成前にＷＳｉｘ膜を基板全面に形成することによ
り、スパッタ法による接着層の形成を行なわなくてもＷ
膜を剥離なく形成できるため、製造工程を簡略化でき、
コストを抑制する効果がある。Next, as shown in FIG. 9, a W / tungsten silicide (hereinafter referred to as WSix) laminated film 14 having a thickness of 500 nm was deposited by SiH 2 F 2 reduction CVD method.
The CVD conditions are such that the flow rates of WF 6 , SiH 2 F 2 and Ar are 5,1000 and 300 scc for the first minute.
m, total pressure was 0.5 Torr, and temperature was 350 ° C. to form WSix. Then, the flow rates of WF 6 , SiH 2 F 2 and Ar are set to 100, 400 and 300 scc, respectively.
m and W was formed. Subsequently, the W / WSix laminated film 14 was processed into a wiring shape by using a normal photolithography technique. The W / WSix laminated film 14 is the underlying BPSG film 1.
The adhesiveness with 2 was good. According to the present embodiment, by forming the WSix film on the entire surface of the substrate before forming the W film, the WSix film is not required to be formed by the sputtering method.
Since the film can be formed without peeling, the manufacturing process can be simplified,
It has the effect of reducing costs.
【００１９】その後、プラズマＣＶＤ法によって形成し
たＳｉＯ膜（以下プラズマＳｉＯと記す）を用い、プラ
ズマＳｉＯ／ＳＯＧ／プラズマＳｉＯ積層絶縁膜７（厚
さ、それぞれ３００ｎｍ／４００ｎｍ／３００ｎｍ、合
計１μｍ）を堆積した後、通常のホトリソグラフィー技
術を用いて、プラズマＳｉＯ／ＳＯＧ／プラズマＳｉＯ
積層絶縁膜７にＷ／ＷＳｉｘ積層膜１４に達する直径
０.４μｍの接続孔１５を形成した。Thereafter, a plasma SiO / SOG / plasma SiO laminated insulating film 7 (thickness: 300 nm / 400 nm / 300 nm, total 1 μm) is deposited using a SiO film formed by plasma CVD method (hereinafter referred to as plasma SiO). Then, plasma SiO / SOG / plasma SiO is formed by using a normal photolithography technique.
A contact hole 15 having a diameter of 0.4 μm reaching the W / WSix laminated film 14 was formed in the laminated insulating film 7.
【００２０】ここで、接続孔１３でのＷ／ＷＳｉｘ積層
膜１４の段差被覆率を調べたところ、＃４のＳｉＨ2Ｆ2
を用いた試料では０．９と良好であるのに対して、従来
のＳｉＨ2Ｆ2を用いた試料では０．６と低いことが分か
った。また、Ｗ／ＷＳｉｘ積層配線とソース・ドレイン
とのコンタクト部の抵抗を測定した。その結果、＃４の
ＳｉＨ2Ｆ2を用いた試料の抵抗値は２００Ωだったのに
対し、従来のＳｉＨ2Ｆ2を用いた場合は４ｋΩだった。Here, when the step coverage of the W / WSix laminated film 14 in the connection hole 13 was examined, SiH 2 F 2 of # 4 was found.
It was found that the sample using Si was as good as 0.9, while the sample using conventional SiH 2 F 2 was as low as 0.6. Further, the resistance of the contact portion between the W / WSix laminated wiring and the source / drain was measured. As a result, the resistance value of the sample using # 4 SiH 2 F 2 was 200Ω, whereas it was 4 kΩ when using the conventional SiH 2 F 2 .
【００２１】その後、図１０に示すように、スパッタ法
およびＳｉＨ2Ｆ2還元Ｗ−ＣＶＤ法により、それぞれ厚
さ３０ｎｍ、５００ｎｍのＷ膜１６、１７を基板全面に
堆積した。ＣＶＤ条件は、ＷＦ6、ＳｉＨ2Ｆ2およびＡ
ｒの流量をそれぞれ１００，４００，３００ｓｃｃｍ、
全圧は０．５Ｔｏｒｒとし、温度は４００℃であった。After that, as shown in FIG. 10, W films 16 and 17 having a thickness of 30 nm and 500 nm, respectively, were deposited on the entire surface of the substrate by a sputtering method and a SiH 2 F 2 reduction W-CVD method. The CVD conditions are WF 6 , SiH 2 F 2 and A
r flow rates of 100, 400 and 300 sccm,
The total pressure was 0.5 Torr and the temperature was 400 ° C.
【００２２】その後、Ｗ膜１６、１７を全面エッチング
し、図１１に示すように接続孔１５内のみにＷ膜１６、
１７を残した。After that, the W films 16 and 17 are entirely etched so that the W films 16 and 17 are formed only in the connection holes 15 as shown in FIG.
I left 17.
【００２３】その後、図１２に示すように、ＴｉＷ膜１
８（厚さ１５０ｎｍ）、Ａｌ膜１９（厚さ８００ｎｍ）
をスパッタ法により順次堆積し、通常のホトリソグラフ
ィー技術を用いて、第２層の配線を形成して、ＭＯＳ−
ＦＥＴ集積回路を完成した。Then, as shown in FIG. 12, a TiW film 1 is formed.
8 (thickness 150 nm), Al film 19 (thickness 800 nm)
Are sequentially deposited by a sputtering method, a second layer wiring is formed by using a normal photolithography technique, and a MOS-
Completed the FET integrated circuit.
【００２４】ここで、第２層のＡｌ／ＴｉＷ積層配線と
第１層のＷ／ＷＳｉｘ積層配線とのコンタクト部の抵抗
を測定した。その結果、上記第１層配線とソース・ドレ
インの場合と同様に、＃４のＳｉＨ2Ｆ2を用いた試料の
コンタクト部の抵抗は、１Ωだったのに対し、従来のＳ
ｉＨ2Ｆ2を用いた場合は３Ωであった。このように、純
度の高いＳｉＨ2Ｆ2を用いてＷ膜の形成を行なった場合
のほうが、第１層配線／ソース・ドレイン間および配線
層間のコンタクト部の抵抗が低く、そのため消費電力が
低く、動作速度が速いＭＯＳ−ＦＥＴ集積回路を作成す
ることができる。Here, the resistance of the contact portion between the Al / TiW laminated wiring of the second layer and the W / WSix laminated wiring of the first layer was measured. As a result, as in the case of the first layer wiring and the source / drain, the resistance of the contact portion of the sample using SiH 2 F 2 of # 4 was 1Ω, whereas the conventional S
It was 3Ω when iH 2 F 2 was used. In this way, when the W film is formed using high-purity SiH 2 F 2 , the resistance of the contact portion between the first-layer wiring / source / drain and between the wiring layers is lower, and therefore the power consumption is lower. It is possible to create a MOS-FET integrated circuit having a high operating speed.
【００２５】また、図９に示した装置を上記と同様に作
成し、接続孔１５に選択ＣＶＤ−ＳｉＨ2Ｆ2還元法によ
りＷを形成した。ＣＶＤ条件は、ＷＦ6、ＳｉＨ2Ｆ2お
よびＡｒの流量をそれぞれ１００，２００，３００ｓｃ
ｃｍ、全圧は０．５Ｔｏｒｒとし、温度は４００℃であ
った。この場合、＃４のＳｉＨ2Ｆ2を用いた試料のほう
が従来のＳｉＨ2Ｆ2を用いた試料より選択性が高く、プ
ラズマＳｉＯ／ＳＯＧ／プラズマＳｉＯ積層絶縁膜７上
に発生したＷの異常成長核の密度は約１／１００に低減
された。Further, the device shown in FIG. 9 was prepared in the same manner as described above, and W was formed in the connection hole 15 by the selective CVD-SiH 2 F 2 reduction method. The CVD conditions are such that the flow rates of WF 6 , SiH 2 F 2 and Ar are 100, 200 and 300 sc, respectively.
cm, total pressure was 0.5 Torr, and temperature was 400 ° C. In this case, the sample using SiH 2 F 2 of # 4 has higher selectivity than the sample using the conventional SiH 2 F 2, and the abnormality of W generated on the plasma SiO / SOG / plasma SiO laminated insulating film 7 is abnormal. The density of growing nuclei was reduced to about 1/100.
【００２６】本実施例では、配線材料はＷを用いたが、
Ｍｏ等の高融点金属を用いても良い。更に、Ｗを形成す
る際には原料ガスとして６フッ化タングステンの他、６
塩化タングステン、タングステンカルボニルを、Ｍｏを
形成する際には原料ガスとして、６フッ化モリブデン、
６塩化モリブデン、モリブデンカルボニル等、高融点金
属のハロゲン化物やカルボニル化合物を用いても良い。In this embodiment, W was used as the wiring material,
A refractory metal such as Mo may be used. Further, when forming W, other than tungsten hexafluoride as a source gas,
Tungsten chloride and tungsten carbonyl are used as raw material gases for forming Mo, molybdenum hexafluoride,
Halides or carbonyl compounds of refractory metals such as molybdenum hexachloride and molybdenum carbonyl may be used.
【００２７】本実施例では、Ｗ膜１４、１７を形成する
際のＷＦ6、ＳｉＨ2Ｆ2の流量をそれぞれ１００、４０
０ｓｃｃｍとしたが、ＳｉＨ2Ｆ2／ＷＦ6の流量比が２
０以下の範囲で流量を変化させてもＷ膜を形成すること
ができる。この際、流量比を大きくすると堆積速度が増
大するが、一方、抵抗率が高くなることに注意する必要
がある。また、基板温度は３５０もしくは４００℃であ
ったが、３００から４５０℃の範囲で変えることができ
る。４５０℃以上ではＷ膜表面の凹凸が大きくなり、段
差被覆性が低下し、３００℃以下ではＷ膜の応力が高く
なり、剥離が起こりやすくなるからである。また、圧力
は０．５Ｔｏｒｒであったが、０．１〜１０Ｔｏｒｒの
範囲で変化させることができる。８０Ｔｏｒｒ程度以上
の高い圧力で形成した場合は堆積速度が大きくなるとい
う利点がある。なお、ＳｉＨ2Ｆ2の流量は５０ｓｃｃｍ
以上、ＷＦ6の流量は１０ｓｃｃｍ以上でタングステン
膜もしくはタングステンシリサイド膜を形成できる。さ
らに、キャリアガスにはＡｒを用いたが、これをＮ2あ
るいはＨ2に代えても同様の結果が得られた。In this embodiment, the flow rates of WF 6 and SiH 2 F 2 when forming the W films 14 and 17 are 100 and 40, respectively.
The flow rate ratio of SiH 2 F 2 / WF 6 is 2 although it is set to 0 sccm.
The W film can be formed even if the flow rate is changed within the range of 0 or less. At this time, increasing the flow rate ratio increases the deposition rate, but it should be noted that the resistivity also increases. Although the substrate temperature was 350 or 400 ° C., it can be changed within the range of 300 to 450 ° C. This is because if the temperature is 450 ° C. or higher, the unevenness of the surface of the W film becomes large and the step coverage decreases, and if the temperature is 300 ° C. or lower, the stress of the W film becomes high and peeling easily occurs. The pressure was 0.5 Torr, but it can be changed within the range of 0.1 to 10 Torr. Forming at a high pressure of about 80 Torr or higher has the advantage of increasing the deposition rate. The flow rate of SiH 2 F 2 is 50 sccm.
As described above, the tungsten film or the tungsten silicide film can be formed with the flow rate of WF 6 of 10 sccm or more. Further, although Ar was used as the carrier gas, similar results were obtained even when Ar was used instead of N 2 or H 2 .
【００２８】本実施例では層間絶縁膜として、第１層目
にＢＰＳＧ膜１２、第２層目にプラズマＳｉＯ／ＳＯＧ
／プラズマＳｉＯの積層膜７を用いたが、代わりにＰＳ
Ｇ、ポリイミド系の耐熱性有機高分子絶縁膜等を用いて
も同様の構造が得られる。In this embodiment, as the interlayer insulating film, the BPSG film 12 is used as the first layer and the plasma SiO / SOG is used as the second layer.
/ Plasma SiO laminated film 7 was used, but PS
The same structure can be obtained by using a heat-resistant organic polymer insulating film of G or polyimide.
【００２９】また、本実施例では第１層配線をＷ／ＷＳ
ｉｘ積層膜で形成したが、Ｗ／ＷＳｉｘ積層膜１４の厚
さを２００ｎｍとし、さらにスパッタ法によりＡｌ膜も
しくはＡｌ合金膜を３００ｎｍ堆積して、Ａｌ／Ｗ／Ｗ
Ｓｉｘの積層配線とすることもできる。この場合、第１
層配線の抵抗が低くなるため、ＭＯＳ−ＦＥＴ集積回路
の動作速度を速くすることができた。また、上記のアル
ミニウムの中に珪素、ゲルマニウム等の半導体、銅、パ
ラジウム等の貴金属、チタン、タンタル等高融点金属を
１種類以上添加したアルミニウム合金を用いても良い。
さらに、Ａｌ膜の代わりに銅膜を用いて積層配線を形成
することもできた。この際、銅の中にニッケル等の耐食
性金属、パラジウム等の貴金属、チタン、タンタル等高
融点金属あるいは燐を一種類以上添加した銅合金を用い
ても良い。In the present embodiment, the first layer wiring is W / WS.
Although the ix laminated film is formed, the W / WSix laminated film 14 has a thickness of 200 nm, and an Al film or an Al alloy film is deposited to a thickness of 300 nm by a sputtering method to form an Al / W / W film.
It can also be a laminated wiring of Six. In this case, the first
Since the resistance of the layer wiring is lowered, the operating speed of the MOS-FET integrated circuit can be increased. An aluminum alloy in which one or more kinds of semiconductors such as silicon and germanium, noble metals such as copper and palladium, and refractory metals such as titanium and tantalum are added to the above aluminum may be used.
Further, a laminated wiring could be formed by using a copper film instead of the Al film. At this time, a corrosion resistant metal such as nickel, a noble metal such as palladium, a refractory metal such as titanium or tantalum, or a copper alloy containing one or more kinds of phosphorus may be used in copper.
【００３０】さらに、高融点金属は金属上もしくは半導
体上にＣＶＤ−ＳｉＨ2Ｆ2還元法により、選択成長させ
ることもできる。Further, the refractory metal can be selectively grown on the metal or the semiconductor by the CVD-SiH 2 F 2 reduction method.
【００３１】（実施例２）作用の欄で行った方法と同一
の方法で図２に示した装置を製造した後、従来のＳｉＨ
2Ｆ2と＃１、＃２、＃３、＃４の純度の異なるＳｉＨ2
Ｆ2を用いてＷ膜６を形成し、通常のホトリソグラフィ
ー技術を用いて、Ｗ膜５、６を配線形状に加工した。さ
らに、プラズマＳｉＯ／ＳＯＧ（Ｓｐｉｎ Ｏｎ Ｇｌ
ａｓｓ）／プラズマＳｉＯ積層膜７（厚さ、それぞれ１
５０ｎｍ／２００ｎｍ／１５０ｎｍ、合計５００ｎｍ）
を堆積した後、通常のホトリソグラフィー技術を用い
て、電極接続用の開口部を形成し、電気特性評価用の素
子を作成した。これを図１３に示す。このような試料に
おいて、ｎ＋型拡散層とＷ膜との接触抵抗および接続孔
内部のＷの配線抵抗を合計したコンタクト部の抵抗を測
定した。その結果、従来のＳｉＨ2Ｆ2を用いた場合は３
ｋΩ、＃１では２ｋΩ、＃２では２００Ω、＃３＃４で
はともに１５０Ωであった。(Embodiment 2) After manufacturing the device shown in FIG. 2 by the same method as the method carried out in the section of the operation, the conventional SiH
2 F 2 and SiH 2 having different purities of # 1, # 2, # 3 and # 4
The W film 6 was formed using F 2 , and the W films 5 and 6 were processed into a wiring shape by using a normal photolithography technique. Furthermore, plasma SiO / SOG (Spin On Gl)
ass) / plasma SiO layered film 7 (thickness, 1 for each)
(50 nm / 200 nm / 150 nm, total 500 nm)
After depositing, an opening for electrode connection was formed by using a normal photolithography technique, and an element for electrical characteristic evaluation was prepared. This is shown in FIG. In such a sample, the resistance of the contact portion, which is the sum of the contact resistance between the n + type diffusion layer and the W film and the wiring resistance of W inside the connection hole, was measured. As a result, when the conventional SiH 2 F 2 is used, it is 3
kΩ, 2 kΩ for # 1, 200Ω for # 2, and 150Ω for # 3 and # 4.
【００３２】これは、純度が低いＳｉＨ2Ｆ2を用いた試
料では段差被覆性が低いため、孔の内部に空洞が生じ、
プラズマＳｉＯ膜７の形成時に孔の内部のＷ膜が酸化さ
れやすくなるため、孔の内部で導通しているＷ膜が薄く
なり、コンタクト部の抵抗が増大したためと考えられ
る。This is because the sample using SiH 2 F 2 having a low purity has a low step coverage, so that a cavity is formed inside the hole.
It is considered that the W film inside the hole is easily oxidized when the plasma SiO film 7 is formed, so that the W film conducting inside the hole becomes thin and the resistance of the contact portion increases.
【００３３】[0033]
【発明の効果】本発明によれば、表面が平坦で、微細な
接続孔にも段差被覆性の良い高融点金属膜もしくは高融
点金属シリサイド膜を形成することができる。According to the present invention, it is possible to form a refractory metal film or refractory metal silicide film having a flat surface and good step coverage even in fine connection holes.
【図１】従来のＳｉＨ2Ｆ2を赤外分光法で分析したスペ
クトル。FIG. 1 is a spectrum of conventional SiH 2 F 2 analyzed by infrared spectroscopy.
【図２】本発明の平坦性、段差被覆性評価に用いた素子
の製造工程を示す断面図。FIG. 2 is a cross-sectional view showing a manufacturing process of an element used for evaluation of flatness and step coverage of the present invention.
【図３】本発明の平坦性、段差被覆性評価に用いた素子
の製造工程を示す断面図。FIG. 3 is a cross-sectional view showing a manufacturing process of an element used for evaluation of flatness and step coverage of the present invention.
【図４】本発明の段差被覆率及び表面凹凸の定義を示す
図。FIG. 4 is a diagram showing definitions of step coverage and surface irregularities according to the present invention.
【図５】ＳｉＨ2Ｆ2の純度とＷ膜の平坦性との関係を示
す図。FIG. 5 is a diagram showing the relationship between the purity of SiH 2 F 2 and the flatness of a W film.
【図６】ＳｉＨ2Ｆ2中のＳｉＨＦ3濃度とＷ膜の堆積速
度との関係を示す図。FIG. 6 is a diagram showing the relationship between the SiHF 3 concentration in SiH 2 F 2 and the deposition rate of a W film.
【図７】実施例１の製造工程を示す断面図。FIG. 7 is a cross-sectional view showing a manufacturing process of the first embodiment.
【図８】実施例１の製造工程を示す断面図。FIG. 8 is a cross-sectional view showing the manufacturing process of the first embodiment.
【図９】実施例１の製造工程を示す断面図。FIG. 9 is a cross-sectional view showing the manufacturing process of the first embodiment.
【図１０】実施例１の製造工程を示す断面図。FIG. 10 is a cross-sectional view showing a manufacturing process of the first embodiment.
【図１１】実施例１の製造工程を示す断面図。FIG. 11 is a cross-sectional view showing the manufacturing process of the first embodiment.
【図１２】実施例１の製造工程を示す断面図。FIG. 12 is a cross-sectional view showing the manufacturing process of the first embodiment.
【図１３】実施例３の電気特性評価用の素子の断面図。FIG. 13 is a sectional view of an element for evaluating electrical characteristics of Example 3.
１…シリコン基板、２、８…シリコン酸化膜、３…ｎ＋
型領域、４…ＰＳＧ膜、５、６、１６、１７…Ｗ膜、７
…プラズマＳｉＯ／ＳＯＧ／プラズマＳｉＯ積層絶縁
膜、９…多結晶シリコン膜、１０…ソース・ドレイン領
域、１１…ＨＬＤ−ＳｉＯ2膜、１２…ＢＰＳＧ膜、１
３、１５…接続孔、１４…Ｗ／ＷＳｉｘ積層膜、１８…
チタン−タングステン膜、１９…Ａｌ膜。1 ... Silicon substrate, 2, 8 ... Silicon oxide film, 3 ... n +
Mold region, 4 ... PSG film, 5, 6, 16, 17 ... W film, 7
... plasma SiO / SOG / plasma SiO stacked insulating film, 9 ... polycrystalline silicon film, 10 ... drain region, 11 ... HLD-SiO 2 film, 12 ... BPSG film, 1
3, 15 ... Connection hole, 14 ... W / WSix laminated film, 18 ...
Titanium-tungsten film, 19 ... Al film.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 中村 吉孝 東京都国分寺市東恋ケ窪１丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yoshitaka Nakamura 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Inside Hitachi Central Research Laboratory
Claims (18)
スと、２フッ化シランの純度が９５ｍｏｌ％以上である
第２の原料ガスとを用いた化学気相成長法により、基体
上に前記高融点金属膜もしくは前記高融点金属のシリサ
イド膜を形成することを特徴とする薄膜の形成方法。1. A chemical vapor deposition method using a first source gas made of a compound of a refractory metal and a second source gas having a purity of difluorinated silane of 95 mol% or more on a substrate. A method of forming a thin film, comprising forming the refractory metal film or the refractory metal silicide film.
前記高融点金属はタングステンであることを特徴とする
薄膜の形成方法。2. The method for forming a thin film according to claim 1, wherein
The method for forming a thin film, wherein the refractory metal is tungsten.
前記高融点金属はモリブデンであることを特徴とする薄
膜の形成方法。3. The method for forming a thin film according to claim 1, wherein
The method for forming a thin film, wherein the refractory metal is molybdenum.
前記第１の原料ガスは前記高融点金属のハロゲン化物も
しくはカルボニル化合物であることを特徴とする薄膜の
形成方法。4. The method for forming a thin film according to claim 1, wherein
The method for forming a thin film, wherein the first source gas is a halide or carbonyl compound of the refractory metal.
前記ハロゲン化物は６フッ化タングステンあるいは６塩
化タングステンであることを特徴とする薄膜の形成方
法。5. The method of forming a thin film according to claim 4,
The method for forming a thin film, wherein the halide is tungsten hexafluoride or tungsten hexachloride.
前記ハロゲン化物は６フッ化モリブデンあるいは６塩化
モリブデンであることを特徴とする薄膜の形成方法。6. The method for forming a thin film according to claim 4,
The method for forming a thin film, wherein the halide is molybdenum hexafluoride or molybdenum hexachloride.
膜の形成方法において、前記第２の原料ガスに不純物と
して含まれている３フッ化シランの濃度は、４ｍｏｌ％
以下であることを特徴とする薄膜の形成方法。7. The method for forming a thin film according to claim 1, wherein the concentration of trifluorosilane contained as an impurity in the second source gas is 4 mol%.
A method for forming a thin film, comprising:
膜の形成方法において、前記基体は半導体基板であるこ
とを特徴とする薄膜の形成方法。8. The method for forming a thin film according to claim 1, wherein the base is a semiconductor substrate.
の形成方法において、前記基体は金属配線を有すること
を特徴とする薄膜の形成方法。9. The method for forming a thin film according to claim 1, wherein the base has metal wiring.
る工程と、高融点金属の化合物よりなる第１の原料ガス
と、２フッ化シランの純度が９５ｍｏｌ％以上である第
２の原料ガスとを用いた化学気相成長法により、前記開
孔部を有する絶縁膜が形成された基板上に前記高融点金
属膜もしくは前記高融点金属のシリサイド膜を形成する
工程を有することを特徴とする半導体装置の製造方法。10. A step of forming an insulating film having an opening on a substrate, a first source gas made of a compound of a refractory metal, and a second purity of difluorinated silane of 95 mol% or more. And a step of forming the refractory metal film or the refractory metal silicide film on the substrate on which the insulating film having the openings is formed by a chemical vapor deposition method using a source gas. And a method for manufacturing a semiconductor device.
において、前記開孔部の直径は０．３μｍ以下であるこ
とを特徴とする半導体装置の製造方法。11. The method of manufacturing a semiconductor device according to claim 10, wherein the diameter of the opening is 0.3 μm or less.
る工程と、高融点金属の化合物よりなる第１の原料ガス
と、純度が９５ｍｏｌ％以上の２フッ化シランよりなる
第２の原料ガスとを用いた化学気相成長法により、前記
開孔部に前記高融点金属のシリサイド膜と前記高融点金
属膜との積層膜を形成する工程を有することを特徴とす
る半導体装置の製造方法。12. A step of forming an insulating film having an opening on a substrate, a first raw material gas made of a compound of a refractory metal, and a second raw material made of difluorinated silane having a purity of 95 mol% or more. Manufacturing a semiconductor device, characterized by including a step of forming a laminated film of the silicide film of the refractory metal and the refractory metal film in the opening by a chemical vapor deposition method using a source gas. Method.
において、前記積層膜を形成する工程の後、前記積層膜
上にアルミニウム膜もしくは銅膜を形成する工程を有す
ることを特徴とする半導体装置の製造方法。13. The semiconductor device manufacturing method according to claim 12, further comprising a step of forming an aluminum film or a copper film on the laminated film after the step of forming the laminated film. Manufacturing method.
板上に第１の絶縁膜を形成する工程と、前記拡散層上の
前記第１の絶縁膜を除去して第１の開孔部を形成する工
程と、前記第１の開孔部から前記第１の絶縁膜上に伸び
た配線層を形成する工程と、前記配線層上に第２の開孔
部を有する第２の絶縁膜を形成する工程と、前記第２の
開孔部から前記第２の絶縁膜上に伸びた第１の高融点金
属膜を形成する工程と、前記第１の高融点金属の化合物
よりなる原料ガスと、２フッ化シランの純度が９５ｍｏ
ｌ％以上である原料ガスとを用いた化学気相成長法によ
り、前記第１の高融点金属膜上に第２の高融点金属膜を
形成する工程を有することを特徴とする半導体装置の製
造方法。14. A step of forming a diffusion layer on a substrate, a step of forming a first insulating film on the substrate, and a step of removing the first insulating film on the diffusion layer to form a first opening. A step of forming a portion, a step of forming a wiring layer extending from the first opening portion onto the first insulating film, and a second insulation having a second opening portion on the wiring layer. A step of forming a film, a step of forming a first refractory metal film extending from the second opening portion onto the second insulating film, and a raw material made of a compound of the first refractory metal The purity of gas and difluorosilane is 95mo
Manufacture of a semiconductor device characterized by comprising a step of forming a second refractory metal film on the first refractory metal film by a chemical vapor deposition method using a source gas of 1% or more. Method.
において、前記第１の高融点金属膜及び第２の高融点金
属膜はタングステン膜であることを特徴とする半導体装
置の製造方法。15. The method of manufacturing a semiconductor device according to claim 14, wherein the first refractory metal film and the second refractory metal film are tungsten films.
体装置の製造方法において、前記配線層はタングステン
膜とタングステンシリサイド膜の積層膜の配線層である
ことを特徴とする半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 14 or 15, wherein the wiring layer is a wiring layer of a laminated film of a tungsten film and a tungsten silicide film.
載の半導体装置の製造方法において、前記第１の絶縁膜
はＢＰＳＧ膜であることを特徴とする半導体装置の製造
方法。17. The method of manufacturing a semiconductor device according to claim 14, wherein the first insulating film is a BPSG film.
載の半導体装置の製造方法において、前記第２の絶縁膜
は、プラズマＳｉＯ膜とＳＯＧ膜とプラズマＳｉＯ膜と
の積層膜であることを特徴とする半導体装置の製造方
法。18. The method of manufacturing a semiconductor device according to claim 14, wherein the second insulating film is a laminated film of a plasma SiO film, an SOG film and a plasma SiO film. A method for manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15327993A JPH0714781A (en) | 1993-06-24 | 1993-06-24 | Formation of thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15327993A JPH0714781A (en) | 1993-06-24 | 1993-06-24 | Formation of thin film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0714781A true JPH0714781A (en) | 1995-01-17 |
Family
ID=15559001
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15327993A Pending JPH0714781A (en) | 1993-06-24 | 1993-06-24 | Formation of thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714781A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011166160A (en) * | 2011-03-22 | 2011-08-25 | Tokyo Electron Ltd | Method of forming multilayer film |
-
1993
- 1993-06-24 JP JP15327993A patent/JPH0714781A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011166160A (en) * | 2011-03-22 | 2011-08-25 | Tokyo Electron Ltd | Method of forming multilayer film |
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