JPH0714769A - Semiconductor production device - Google Patents
Semiconductor production deviceInfo
- Publication number
- JPH0714769A JPH0714769A JP15072993A JP15072993A JPH0714769A JP H0714769 A JPH0714769 A JP H0714769A JP 15072993 A JP15072993 A JP 15072993A JP 15072993 A JP15072993 A JP 15072993A JP H0714769 A JPH0714769 A JP H0714769A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- difference
- electrodes
- electrode
- specific value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体製造技術さらに
は膜形成技術及びエッチング技術に関し、例えば多電極
を有するスパッタ装置やプラズマＣＶＤ装置やドライエ
ッチング装置における印加電界の周波数干渉防止に利用
して有用な技術に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, a film forming technique, and an etching technique, and is used for preventing frequency interference of an applied electric field in a sputtering apparatus, a plasma CVD apparatus, or a dry etching apparatus having multiple electrodes. Regarding useful technology.
【０００２】[0002]
【従来の技術】一般に、半導体装置の製造において、半
導体ウェハ上に絶縁膜や配線用の導電膜などを積層させ
る技術として、スパッタ法やＣＶＤ法などの膜形成技術
が知られている。また、形成した絶縁膜や導電膜を所望
のパターン（形状）をなすように加工する技術として、
反応性イオンエッチング法などのドライエッチング技術
が知られている。2. Description of the Related Art Generally, in manufacturing a semiconductor device, a film forming technique such as a sputtering method or a CVD method is known as a technique for laminating an insulating film and a conductive film for wiring on a semiconductor wafer. In addition, as a technique for processing the formed insulating film or conductive film to form a desired pattern (shape),
A dry etching technique such as a reactive ion etching method is known.
【０００３】それら各方法において使用される装置に
は、ＲＦ（高周波）バイアススパッタ装置やプラズマＣ
ＶＤ装置などのように複数の電極を有したものがある。
例えば、筒状の基板電極の側面に複数枚の半導体ウェハ
を取り付けて回転させることにより膜形成を行なうドラ
ム型回転タイプのバイアススパッタ装置では、基板電極
の外側に複数個、例えば４個のターゲット電極が設けら
れている。それら基板電極及びターゲット電極には夫々
専用の高周波電源（各電源の発信周波数は同一であ
る。）が接続されている。An apparatus used in each of these methods includes an RF (high frequency) bias sputtering apparatus and a plasma C
Some VD devices and the like have a plurality of electrodes.
For example, in a drum-type rotation type bias sputtering apparatus in which a plurality of semiconductor wafers are attached to the side surface of a tubular substrate electrode and rotated to form a film, a plurality of, for example, four target electrodes are provided outside the substrate electrode. Is provided. A dedicated high-frequency power source (each power source has the same oscillation frequency) is connected to the substrate electrode and the target electrode.
【０００４】そして、膜形成時に半導体ウェハに付着し
て異物となるスプラッタやコンタミネーションの発生を
抑えるために、各電極に印加する高周波電界の位相を制
御することにより、高周波電界のうなり現象、即ち周波
数干渉の発生を抑制して、放電の不安定状態や異常放電
が起こるのを防いでいる。具体的には、上述した５個の
電極に対して各電極とそれの専用電源との間のケーブル
長を同じにし、且つ各電極に印加する高周波電圧の位相
を各電極毎に制御可能な位相シフターなる装置を用い
て、高周波の位相が各電極毎にずれるようにしている。
多電極を有するプラズマＣＶＤ装置やドライエッチング
装置においても同様にして高周波電界の周波数干渉を防
いでいる。Then, in order to suppress the generation of splatter or contamination that adheres to the semiconductor wafer and becomes a foreign substance during film formation, the phase of the high frequency electric field applied to each electrode is controlled, whereby a beating phenomenon of the high frequency electric field, that is, The occurrence of frequency interference is suppressed to prevent unstable discharge and abnormal discharge. Specifically, the above-mentioned five electrodes have the same cable length between each electrode and its dedicated power source, and the phase of the high-frequency voltage applied to each electrode can be controlled for each electrode. A device called a shifter is used so that the phase of the high frequency shifts for each electrode.
Similarly, in a plasma CVD apparatus or a dry etching apparatus having multiple electrodes, frequency interference of a high frequency electric field is prevented.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上述し
た技術には、次のような問題のあることが本発明者らに
よってあきらかとされた。すなわち、スパッタ装置の組
立・製造時に、上記５個の電極とそれの専用電源間を結
ぶ各ケーブルの長さに誤差が生じてしまうのは避けられ
ないことであり、ケーブル長を厳密に同一にすることは
極めて困難である。従って、各電極に対する位相をシフ
ターで制御しても、実際に電極間に生じる高周波電界の
位相は設定値から僅かにずれているのが普通である。電
源の出力（パワー）が小さい場合には周波数干渉は比較
的起こり難いが、スループットを上げるためにパワーを
大きくすると、位相のずれ等の影響が大きくなり、微少
な異常放電を起こし易くなる。チャンバー内で異常放電
が発生すると、位相シフターが誤動作して装置のインピ
ーダンスの整合などが取れなくなり、制御不能になるこ
とがある、というものである。However, the present inventors have clarified that the above-mentioned technique has the following problems. That is, it is inevitable that an error will occur in the length of each cable that connects the above-mentioned five electrodes and their dedicated power source during the assembly / manufacturing of the sputtering apparatus. It is extremely difficult to do. Therefore, even if the phase for each electrode is controlled by the shifter, the phase of the high-frequency electric field actually generated between the electrodes is usually slightly deviated from the set value. When the output (power) of the power source is small, frequency interference is relatively unlikely to occur, but when the power is increased to increase the throughput, the influence of phase shift and the like becomes large, and a slight abnormal discharge is likely to occur. If an abnormal discharge occurs in the chamber, the phase shifter may malfunction, impedance matching of the device may not be achieved, and control may become impossible.
【０００６】従って、上述した位相制御による周波数干
渉防止では、パワーを余り大きくすることができず、ス
ループットを上げることは困難であるという問題点があ
った。多電極を有するプラズマＣＶＤ装置やドライエッ
チング装置においても同様に、パワーを余り大きくする
ことができず、スループットが上がらなかった。Therefore, in the frequency interference prevention by the above-mentioned phase control, there is a problem that it is difficult to increase the power and it is difficult to increase the throughput. Similarly, in a plasma CVD apparatus or a dry etching apparatus having multiple electrodes, the power could not be increased so much and the throughput could not be improved.
【０００７】本発明はかかる事情に鑑みてなされたもの
で、その主たる目的は、位相制御によらず、印加した高
周波電界に周波数干渉が起こるのを防ぎ、放電の安定化
を図ることを可能ならしめるスパッタ装置やプラズマＣ
ＶＤ装置やドライエッチング装置などの半導体製造装置
を提供することにある。また、本発明の他の目的は、放
電の安定化を図ることにより、パワーアップが可能とな
り、それによってスループットの向上をも可能ならしめ
る半導体製造装置を提供することにある。この発明の前
記ならびにそのほかの目的と新規な特徴については、本
明細書の記述及び添附図面から明らかになるであろう。The present invention has been made in view of the above circumstances, and its main purpose is to prevent the occurrence of frequency interference in the applied high-frequency electric field and stabilize the discharge regardless of the phase control. Sputtering equipment and plasma C
It is to provide a semiconductor manufacturing apparatus such as a VD apparatus or a dry etching apparatus. Another object of the present invention is to provide a semiconductor manufacturing apparatus that can stabilize power discharge and thereby power up, thereby improving throughput. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】上記目的を達成するた
め、本発明者等は、異なる周波数の高周波電界により引
き起こされるうなり現象を検討した結果、高周波電界の
周波数が約１３．５６MHzの場合、図２に示すように、
各周波数間の差が２００Hz以上であれば、うなりが殆ど
発生しないか、または全く発生しないことがわかった。
これより、ある特定値以上の周波数差を設ければうなり
現象が起こらないと考え、本発明の完成に至った。In order to achieve the above object, the inventors of the present invention have studied the beat phenomenon caused by high frequency electric fields of different frequencies. As a result, when the frequency of the high frequency electric field is about 13.56 MHz, As shown in 2,
It has been found that if the difference between the frequencies is 200 Hz or more, the beat hardly occurs or does not occur at all.
From this, it was thought that a beating phenomenon would not occur if a frequency difference of a certain value or more was provided, and the present invention was completed.
【０００９】本願において開示される発明のうち代表的
なものの概要を説明すれば、下記のとおりである。すな
わち、本発明の半導体製造装置においては、複数の電極
を有し、それら電極に印加した各交番電圧の周波数同士
の差である第１次周波数差が第１の特定値以上であるこ
とを提案するものである。さらに、第１次周波数差同士
の差である第２次周波数差が第２の特定値以上であるこ
とも提案する。具体的には、例えば図１に示すように、
５個の電極Ｔ1，Ｔ2，Ｔ3，Ｔ4，Ｓを有する装置の場
合、各電極に夫々印加する高周波電圧の周波数ｆ1，
ｆ2，ｆ3，ｆ4，ｆ5を、夫々、１３．５５０MHz，１
３．５５３MHz，１３．５６５MHz，１３．５７４MHz，
１３．５６０MHzとする。この場合、それら各周波数の
第１次周波数差、即ちｆ1，ｆ2，ｆ3，ｆ4，ｆ5の相互
の差の大きさ（絶対値）は、何れも２００Hz（第１の特
定値）以上である。また、第２次周波数差、即ち各第１
次周波数差の相互の差の大きさ（絶対値）も、何れも２
００Hz（第２の特定値）以上である。The outline of a typical one of the inventions disclosed in the present application will be described below. That is, it is proposed that the semiconductor manufacturing apparatus of the present invention has a plurality of electrodes and that the primary frequency difference, which is the difference between the frequencies of the alternating voltages applied to the electrodes, is equal to or greater than the first specific value. To do. Further, it is also proposed that the second-order frequency difference, which is the difference between the first-order frequency differences, is equal to or larger than the second specific value. Specifically, for example, as shown in FIG.
In the case of a device having five electrodes T 1 , T 2 , T 3 , T 4 , S, the frequency f 1 of the high-frequency voltage applied to each electrode,
f 2 , f 3 , f 4 , and f 5 are respectively set to 13.550 MHz, 1
3.553MHz, 13.565MHz, 13.574MHz,
It is set to 13.560 MHz. In this case, the primary frequency difference of each of these frequencies, that is, the magnitude (absolute value) of the mutual difference of f 1 , f 2 , f 3 , f 4 , and f 5 is 200 Hz (first specific value). ) That is all. In addition, the second-order frequency difference, that is, each first
The magnitude (absolute value) of the mutual difference between the next frequency differences is 2
It is equal to or higher than 00 Hz (second specific value).
【００１０】[0010]
【作用】上記した手段によれば、第１次周波数差が、顕
著にうなり現象の起こる限界値である第１の特定値以上
となるようにしたため、うなり現象の発生を抑えること
ができる。加えて、第２次周波数も同様に顕著なうなり
現象発生の限界値である第２の特定値以上となるように
したため、うなりが殆ど発生しないか、または全く発生
しない。従って、チャンバー内の放電の安定化が図れ
る。According to the above means, the first-order frequency difference is set to be equal to or more than the first specific value which is the limit value at which the beat phenomenon remarkably occurs, so that the occurrence of the beat phenomenon can be suppressed. In addition, since the secondary frequency is also set to be equal to or higher than the second specific value which is the limit value for the occurrence of a noticeable beat phenomenon, the beat hardly occurs or does not occur at all. Therefore, the discharge in the chamber can be stabilized.
【００１１】[0011]
【実施例】本発明に係る半導体製造装置の一例を図１に
示し、以下に説明する。図１には、本発明を適用したド
ラム型回転タイプのＲＦバイアススパッタ装置が示され
ている。同図に示すように、このスパッタ装置１におい
ては、チャンバー１０内に４個のターゲット電極Ｔ1，
Ｔ2，Ｔ3，Ｔ4及びバイアス用の基板電極Ｓが設けられ
ており、それら各電極Ｔ1，Ｔ2，Ｔ3，Ｔ4，Ｓには、夫
々、インピーダンス等の整合をとるマッチング回路
Ｍ1，Ｍ2，Ｍ3，Ｍ4，Ｍ5を介して、専用の高周波電源
Ｐ1，Ｐ2，Ｐ3，Ｐ4，Ｐ5が接続されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of a semiconductor manufacturing apparatus according to the present invention is shown in FIG. 1 and will be described below. FIG. 1 shows a drum type rotary type RF bias sputtering apparatus to which the present invention is applied. As shown in the figure, in this sputtering apparatus 1, four target electrodes T 1 ,
T 2, T 3, T 4 and has substrate electrode S is provided for biasing the their respective electrodes T 1, T 2, T 3, T 4, S, respectively, the matching circuit for matching the impedance, etc. Dedicated high-frequency power supplies P 1 , P 2 , P 3 , P 4 , P 5 are connected via M 1 , M 2 , M 3 , M 4 , M 5 .
【００１２】例えば、各電源Ｐ1，Ｐ2，Ｐ3，Ｐ4，Ｐ5
の各発振周波数ｆ1，ｆ2，ｆ3，ｆ4，ｆ5は、夫々、１
３．５５０MHz，１３．５５３MHz，１３．５６５MHz，
１３．５７４MHz，１３．５６０MHzである。この時、各
周波数ｆ1，ｆ2，ｆ3，ｆ4，ｆ 5同士の差である第１次
周波数差は何れも第１の特定値である２００Hz以上の値
であり、式で表すと以下の通りである。即ち、Δｆ
12（ｆ1とｆ2との差の絶対値｜ｆ1−ｆ2｜を表す。他も
同じ。）＝０．３kHz、Δｆ13＝１５kHz、Δｆ14＝２４
kHz、Δｆ15＝１０kHz、Δｆ23＝１２kHz、Δｆ24＝２
１kHz、Δｆ25＝７kHz、Δｆ34＝０．９kHz、Δｆ35＝
０．５kHz、Δｆ45＝１４kHz、である。また、それら各
第１次周波数差Δｆ12，Δｆ13，Δｆ14，Δｆ15，Δｆ
23，Δｆ24，Δｆ25，Δｆ34，Δｆ35，Δｆ45同士の差
である第２次周波数差は式で表すと以下のようになる。
即ち、Δｆ12-23（Δｆ12とΔｆ23との差の絶対値｜Δ
ｆ12−Δｆ23｜を表す。他も同じ。）＝１１．７kHz、
Δｆ12-34＝０．６kHz、Δｆ12-45＝１３．７kHz、Δｆ
13-23＝３kHz、Δｆ13-34＝１４．１kHz、…、以下省略
するが、同一の値のものはなく、何れも第２の特定値で
ある２００Hz以上の値である。For example, each power source P1, P2, P3, PFour, PFive
Each oscillation frequency f1, F2, F3, FFour, FFiveIs 1
3.550MHz, 13.553MHz, 13.565MHz,
These are 13.574 MHz and 13.560 MHz. At this time, each
Frequency f1, F2, F3, FFour, F FiveThe first, which is the difference between the two
All frequency differences are values above 200Hz, which is the first specific value
And is expressed as follows. That is, Δf
12(F1And f2Absolute value of difference with | f1-F2Represents |. Others
the same. ) = 0.3kHz, Δf13= 15kHz, Δf14= 24
kHz, Δf15= 10kHz, Δftwenty three= 12kHz, Δftwenty four= 2
1kHz, Δftwenty five= 7kHz, Δf34= 0.9kHz, Δf35=
0.5kHz, Δf45= 14 kHz. Also, each of them
Primary frequency difference Δf12, Δf13, Δf14, Δf15, Δf
twenty three, Δftwenty four, Δftwenty five, Δf34, Δf35, Δf45The difference
The second-order frequency difference that is expressed as follows is as follows.
That is, Δf12-23(Δf12And Δftwenty threeAbsolute value of difference with
f12-Δftwenty threeRepresents |. Others are the same. ) = 11.7kHz,
Δf12-34= 0.6kHz, Δf12-45= 13.7kHz, Δf
13-23= 3kHz, Δf13-34= 14.1kHz, ..., omitted below
However, there is no one with the same value, and both are the second specific values.
It is a value over 200Hz.
【００１３】上記ターゲット電極Ｔ1，Ｔ2，Ｔ3，Ｔ
4は、例えば基板電極Ｓに取り付けた半導体ウェハ２０
にＳｉＯ2（酸化シリコン）膜を被着させる場合には、
ＳｉＯ2よりなる。また、図１において、符号３０は排
気口であり、この排気口３０を介して図示しないロータ
リーポンプなどにより例えば２×１０-4Pa以下までチャ
ンバー１０内を真空引きする。そして、真空引きした
後、符号４０で示したガス供給口よりＡｒ（アルゴン）
等の不活性ガスを導入して２．５×１０-1Paに保ち、ス
パッタを行う。The target electrodes T 1 , T 2 , T 3 , T
4 is a semiconductor wafer 20 attached to the substrate electrode S, for example
When depositing a SiO 2 (silicon oxide) film on
It is made of SiO 2 . Further, in FIG. 1, reference numeral 30 denotes an exhaust port, and the interior of the chamber 10 is evacuated to a pressure of, for example, 2 × 10 −4 Pa or less by a rotary pump (not shown) or the like through the exhaust port 30. Then, after evacuation, Ar (argon) is supplied from the gas supply port 40.
Sputtering is carried out by introducing an inert gas such as the above to maintain the pressure at 2.5 × 10 -1 Pa.
【００１４】以上、詳述したように、第１次周波数差が
２００Hz以上で相互に異なる値であり、好ましくはそれ
に加えて第２次周波数差も２００Hz以上で相互に異なる
値であるため、各電極Ｔ1，Ｔ2，Ｔ3，Ｔ4，Ｓに印加し
た各電圧の交番電界による電子の動きと、第１次周波数
差により生じる交番電界による電子の動きと、第２次周
波数差により生じる交番電界による電子の動きとに重な
りが生じない。そのため、発生するプラズマ中の電子密
度に粗密が発生せず、プラズマの安定が図れる。また、
放電が安定し、それによって基板バイアスも安定し、ス
プラッタ等の異物やコンタミネーションが低減される。As described above in detail, the first-order frequency difference has a value different from each other at 200 Hz or more, and preferably the second-order frequency difference also has a value different from each other at 200 Hz or more. Electrons move due to the alternating electric field of each voltage applied to the electrodes T 1 , T 2 , T 3 , T 4 , and S, and move due to the alternating electric field due to the primary frequency difference, and due to the secondary frequency difference There is no overlap with the movement of electrons due to the alternating electric field. Therefore, the density of electrons in the generated plasma does not vary, and the plasma can be stabilized. Also,
The discharge is stabilized, the substrate bias is also stabilized, and foreign matter such as splatter and contamination are reduced.
【００１５】直径１００mmの半導体ウェハに付着した異
物の数をカウントしたところ（但し、約５mm程度の周縁
部を除く。）、従来の位相制御による場合には１μｍ以
上の大きさの異物が数千個であったのに対して、第１次
周波数差のみを２００Hz以上とした場合（第２周波数差
に付いては考慮せず。）にはその数は１００〜２００個
程度であり、さらに第１次周波数差に加えて第２周波数
差も２００Hz以上とした場合にはその数は１０個程度で
あった。即ち、異物付着に対して、極めて優れた効果の
あることが確認された。When the number of foreign matters adhering to a semiconductor wafer having a diameter of 100 mm was counted (excluding the peripheral portion of about 5 mm), the number of foreign matters having a size of 1 μm or more was several thousand when the conventional phase control was used. On the other hand, when only the first frequency difference is set to 200 Hz or more (the second frequency difference is not considered), the number is about 100 to 200, and When the second frequency difference was 200 Hz or more in addition to the primary frequency difference, the number was about 10. That is, it was confirmed that it has an extremely excellent effect on foreign matter adhesion.
【００１６】以上本発明者によってなされた発明を実施
例に基づき具体的に説明したが、本発明は上記実施例に
限定されるものではなく、その要旨を逸脱しない範囲で
種々変更可能であることはいうまでもない。例えば、電
極の数は上記実施例における数に限らず、第２次周波数
差を考慮しない場合には２個以上で有ればよいし、第２
次周波数差も考慮する場合には３個以上で有ればよい。
また、電源の発振周波数も約１３．５６MHzに限らない
のはいうまでもないし、第１次各周波数差及び第２次周
波数差の下限値、即ち第１の特定値及び第２の特定値も
上記実施例における２００Hzに限定されないのはいうま
でもない。即ち、それら第１の特定値及び第２の特定値
は、電源の発振周波数や個々の装置の個体差などにより
決められる。さらに、本発明は、バイアススパッタ以外
の多電極スパッタ装置や多電極ＣＶＤ装置や多電極エッ
チング装置にも適用可能である。Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the number of electrodes is not limited to the number in the above embodiment, and may be two or more if the second-order frequency difference is not considered.
If the next frequency difference is also taken into consideration, the number may be three or more.
Needless to say, the oscillation frequency of the power supply is not limited to about 13.56 MHz, and the lower limit values of the first-order frequency differences and the second-order frequency differences, that is, the first specific value and the second specific value are also It goes without saying that the frequency is not limited to 200 Hz in the above embodiment. That is, the first specific value and the second specific value are determined by the oscillation frequency of the power supply, individual differences of individual devices, and the like. Furthermore, the present invention can be applied to a multi-electrode sputtering apparatus other than bias sputtering, a multi-electrode CVD apparatus, or a multi-electrode etching apparatus.
【００１７】以上の説明では主として本発明者によって
なされた発明をその背景となった利用分野である半導体
装置の製造技術について説明したが、この発明はそれに
限定されるものではなく、膜形成技術一般及びエッチン
グ技術一般に利用することができる。In the above description, the invention made by the present inventor was mainly described as a semiconductor device manufacturing technique which is the field of application of the invention, but the present invention is not limited to this and the film forming technique in general. And the etching technique can be generally used.
【００１８】[0018]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば下記
のとおりである。すなわち、異なる周波数の交番電界に
よるうなりの発生が抑えられるため、チャンバー内の放
電の安定化が図れ、従来の位相制御に較べて周波数干渉
を容易に防ぐことができる。また、位相制御に較べてパ
ワーを上げても放電の安定が保たれるので、従来よりも
パワーを上げて処理することができ、スループットの向
上が図れる。さらに、位相シフターが不要となるので、
装置の構造が簡略化され、装置にかかるコスト等も低く
なる。The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, since the occurrence of beats due to the alternating electric fields of different frequencies is suppressed, the discharge in the chamber can be stabilized, and the frequency interference can be easily prevented as compared with the conventional phase control. Further, since the discharge is kept stable even when the power is increased as compared with the phase control, the power can be increased and the processing can be performed, and the throughput can be improved. Furthermore, since the phase shifter is unnecessary,
The structure of the device is simplified and the cost of the device is reduced.
【図１】本発明に係る半導体製造装置を適用したＲＦバ
イアススパッタ装置の一例の概略構成図である。FIG. 1 is a schematic configuration diagram of an example of an RF bias sputtering apparatus to which a semiconductor manufacturing apparatus according to the present invention is applied.
【図２】うなりに対する周波数差の依存性を示す特性図
である。FIG. 2 is a characteristic diagram showing dependence of frequency difference on beat.
ｆ1，ｆ2，ｆ3，ｆ4，ｆ5 周波数 Ｔ1，Ｔ2，Ｔ3，Ｔ4 ターゲット電極（電極） Ｓ 基板電極（電極）f 1 , f 2 , f 3 , f 4 , f 5 frequency T 1 , T 2 , T 3 , T 4 target electrode (electrode) S substrate electrode (electrode)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 笹部 俊二 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shunji Sasabe 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center
Claims (3)
数の電極を有し、それら電極のうち異なる二電極に夫々
割り当てられた周波数同士の差である第１次周波数差が
第１の特定値以上となっていることを特徴とする半導体
製造装置。1. A plurality of electrodes to which alternating voltages of different frequencies can be applied, and a primary frequency difference, which is a difference between frequencies assigned to two different electrodes of the electrodes, is a first specific value. A semiconductor manufacturing apparatus characterized by the above.
次周波数差同士の差である第２次周波数差が第２の特定
値以上となっていることを特徴とする請求項１記載の半
導体製造装置。2. The first electrode having at least three electrodes,
2. The semiconductor manufacturing apparatus according to claim 1, wherein the secondary frequency difference, which is the difference between the secondary frequency differences, is equal to or greater than a second specific value.
MHzであり、上記第１の特定値及び上記第２の特定値は
何れも２００Hzであることを特徴とする請求項１又は２
記載の半導体製造装置。3. The frequency value of each electrode is about 13.56.
3. The frequency is MHz, and the first specific value and the second specific value are both 200 Hz.
The semiconductor manufacturing apparatus described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15072993A JPH0714769A (en) | 1993-06-22 | 1993-06-22 | Semiconductor production device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15072993A JPH0714769A (en) | 1993-06-22 | 1993-06-22 | Semiconductor production device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0714769A true JPH0714769A (en) | 1995-01-17 |
Family
ID=15503141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15072993A Pending JPH0714769A (en) | 1993-06-22 | 1993-06-22 | Semiconductor production device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714769A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001274099A (en) * | 2000-03-24 | 2001-10-05 | Mitsubishi Heavy Ind Ltd | Power supply method to discharge electrode, high- frequency plasma generation method, and semiconductor- manufacturing method |
| US6456010B2 (en) | 2000-03-13 | 2002-09-24 | Mitsubishi Heavy Industries, Ltd. | Discharge plasma generating method, discharge plasma generating apparatus, semiconductor device fabrication method, and semiconductor device fabrication apparatus |
| WO2012090422A1 (en) * | 2010-12-27 | 2012-07-05 | キヤノンアネルバ株式会社 | Epitaxial film-forming method, sputtering apparatus, method for manufacturing semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| WO2014002465A1 (en) * | 2012-06-26 | 2014-01-03 | キヤノンアネルバ株式会社 | Epitaxial film-forming method, sputtering device, method for manufacturing semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| WO2016203585A1 (en) * | 2015-06-17 | 2016-12-22 | 株式会社シンクロン | Film forming method and film forming device |
-
1993
- 1993-06-22 JP JP15072993A patent/JPH0714769A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6456010B2 (en) | 2000-03-13 | 2002-09-24 | Mitsubishi Heavy Industries, Ltd. | Discharge plasma generating method, discharge plasma generating apparatus, semiconductor device fabrication method, and semiconductor device fabrication apparatus |
| JP2001274099A (en) * | 2000-03-24 | 2001-10-05 | Mitsubishi Heavy Ind Ltd | Power supply method to discharge electrode, high- frequency plasma generation method, and semiconductor- manufacturing method |
| WO2012090422A1 (en) * | 2010-12-27 | 2012-07-05 | キヤノンアネルバ株式会社 | Epitaxial film-forming method, sputtering apparatus, method for manufacturing semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| JP5576507B2 (en) * | 2010-12-27 | 2014-08-20 | キヤノンアネルバ株式会社 | Epitaxial film forming method, sputtering apparatus, semiconductor light emitting element manufacturing method, semiconductor light emitting element, and illumination apparatus |
| US10844470B2 (en) | 2010-12-27 | 2020-11-24 | Canon Anelva Corporation | Epitaxial film forming method, sputtering apparatus, manufacturing method of semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| WO2014002465A1 (en) * | 2012-06-26 | 2014-01-03 | キヤノンアネルバ株式会社 | Epitaxial film-forming method, sputtering device, method for manufacturing semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| JP5886426B2 (en) * | 2012-06-26 | 2016-03-16 | キヤノンアネルバ株式会社 | Epitaxial film forming method, sputtering apparatus, semiconductor light emitting element manufacturing method, semiconductor light emitting element, and illumination apparatus |
| US9379279B2 (en) | 2012-06-26 | 2016-06-28 | Canon Anelva Corporation | Epitaxial film forming method, sputtering apparatus, manufacturing method of semiconductor light-emitting element, semiconductor light-emitting element, and illumination device |
| WO2016203585A1 (en) * | 2015-06-17 | 2016-12-22 | 株式会社シンクロン | Film forming method and film forming device |
| JPWO2016203585A1 (en) * | 2015-06-17 | 2018-04-05 | 株式会社シンクロン | Film forming method and film forming apparatus |
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