JP3949186B2 - Substrate mounting table, plasma processing apparatus, and semiconductor device manufacturing method - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32155—Frequency modulation
- H01J37/32165—Plural frequencies
Description
【０００１】
【発明の属する技術分野】
本発明は、プラズマ処理装置及びプラズマ処理方法に関し、より詳しくは、プラズマにより成膜やエッチングの処理を行うためのプラズマ処理装置及びプラズマ処理方法に関する。
成膜やエッチングの処理では、成膜レートやエッチングレートの均一性を向上させることが要望され、そのため、プラズマ中のイオンが被処理基板に均一に入射するように制御することが重要である。
【０００２】
【従来の技術】
図７に従来例のプラズマ処理装置を示す。図７に示すように、プラズマ生成室１の周囲に高周波電力印加用のコイル２が巻回されており、ＲＦ電力を供給してプラズマを生成する。また、プラズマ生成室１には成膜室３がつながっており、プラズマ生成室１からプラズマを供給する。成膜室３内にはウエハ載置台４が設置され、そのウエハ載置面に処理すべきウエハ９を載置してプラズマ中のイオンにより成膜或いはエッチングを行う。さらに、ウエハ載置台４の材料は樹脂やセラミック等であり、このような材料はプラズマに曝されると、エッチングを受けたりするので、ウエハ載置台４の大きさを載置されるウエハ９の直径よりも小さくし、ウエハ載置台４が損傷を受けないようにしている。
【０００３】
また、ウエハ９へのイオンの入射効率を高めるため、或いはエッチングの異方性を高めるため、ウエハ載置台４の絶縁体５内には円板状の電極６がその板面をウエハ載置面に対向させて埋め込まれている。さらに、１００ｋＨｚ〜２０ＭＨｚの周波数のＲＦ電力を供給するＲＦ電源８がマッチング回路７を介して電極６に接続されている。
【０００４】
上記プラズマ処理装置を用いてエッチングを行う場合、ＲＦ電力を電極６に印加すると、その交番電圧によってプラズマからイオンによる電流と電子による電流との合成電流（ｉＳ）がウエハ９に流れる。このとき、イオンに比べて動きやすい電子による電流の方がイオンによる電流よりも流れやすいため、ＲＦ電力の一周期の間にウエハ９に流れる正負の電荷の総量を等しくするように、即ち電子による電流を減少させ、或いはイオンによる電流を増加させるように、ウエハ９表面には負のセルフバイアス電圧（ＶＳＢ）が発生する。
【０００５】
これにより、プラズマ中のイオンはウエハ９に効率良く入射し、或いはエッチングの異方性が高められる。
【０００６】
【発明が解決しようとする課題】
しかしながら、上記のプラズマ処理装置を用いたエッチングにおいては、ウエハ載置台４の大きさがウエハの直径よりも小さく、また、ＲＦ電力の周波数が高くなると、ウエハ９面内各所に同じ電力を印加することが困難になる。このため、図３（ｂ）に示すように、エッチングレートがウエハ９面内の中央部と周辺部で大きくばらついてしまう場合がある。
【０００７】
本発明は、上記の従来例の問題点に鑑みて創作されたものであり、被処理基板面内の成膜レートやエッチングレートの均一性を向上させることが可能なプラズマ処理装置及びプラズマ処理方法を提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記課題は、第１の発明である、プラズマ処理を行う被処理基板を載置し、前記被処理基板表面に直流バイアス電圧を発生させる交流電力を印加する電極が埋め込まれた絶縁物からなる基板載置台であって、前記電極は、前記被処理基板を固定する中央部の円板状の部分電極と、該中央部の部分電極を中心とするその周辺部であって、該中央部の部分電極に固定された前記被処理基板の周縁の外側周囲に、該中央部の部分電極に対して同心円状にかつ該中央部の部分電極よりも低い位置に配置された部分電極とで構成され、該中央部の部分電極と外側周囲の部分電極は互いに絶縁分離されて、該部分電極にはそれぞれ周波数の異なる前記交流電力を供給する交流電源が接続されていることを特徴とする基板載置台によって達成され、
第２の発明である、前記電極には直流電源が接続され、前記被処理基板を静電吸着する電極を兼ねていることを特徴とする第１の発明に記載の基板載置台によって達成され、
第３の発明である、プラズマ生成室と、前記プラズマ生成室とつながったプラズマ処理室と、前記プラズマ処理室内に設置された第１又は第２の発明のいずれかに記載の基板載置台を有することを特徴とするプラズマ処理装置によって達成され、
第４の発明である、プラズマ処理室と、前記プラズマ処理室内に互いに対向して設けられた第１の電極及び第２の電極とを有する平行平板型のプラズマ処理装置であって、前記第１の電極にはプラズマ生成用交流電力が供給され、前記第２の電極は第１又は第２の発明のいずれかに記載の基板載置台を兼ねていることを特徴とするプラズマ処理装置によって達成され、
第５の発明である、第１又は第２の発明のいずれかに記載の基板載置台に被処理基板として半導体ウエハを載置して処理を行うことを特徴とする半導体装置の製造方法によって達成される。
【０００９】
本発明の基板載置台においては、その基板載置台に互いに絶縁分離された複数の部分電極が埋め込まれ、各部分電極にはそれぞれ周波数の異なる交流電力を供給する交流電源が接続されている。
プラズマ及び基板載置台を含む系全体の電気的等価回路は図６（ａ）に示すようになり、各部分電極毎に独立に電流が流れる。また、基板載置台に埋め込まれた各部分電極に印加する交流電力の周波数の差異により、各部分電極でのセルフバイアス電圧が異なってくる。即ち、図５に示すように、周波数（ｆ）が高くなるにつれて負のセルフバイアス電圧（ＶＳＢ）の絶対値が小さくなる。
【００１０】
従って、上記の基板載置台が備えられている本発明のプラズマ処理装置に適用した場合、例えば、電極の分割前にエッチングレートの小さかったところでは周波数を低くして負のセルフバイアス電圧を負の方にさらに大きくし、エッチングレートの大きかったところでは周波数を高くして負のセルフバイアス電圧の絶対値を小さくする。これにより、表面電位（ＶＳ，ＶＳ１，ＶＳ２）が異なってきて、分割前にエッチングレートの小さかったところでは表面電位が負の方に大きくなってイオンによる電流が増え、エッチングレートの大きかったところでは表面電位が負の方に小さくなってイオンによる電流が減る。
【００１１】
従って、この基板載置台を用いた本発明の半導体装置の製造方法によれば、不均一の程度に応じて周波数を適当に調整することにより、均一なエッチングレートや成膜レートを得ることができる。
また、基板載置台の複数の部分電極のうち周辺部の１以上の部分電極が載置される被処理基板よりも大きい直径の同心円上にある場合、被処理基板の存在領域とその周縁に隣接する外側領域とでセルフバイアス電圧を単独に調整することができる。
【００１２】
これにより、被処理基板の周縁に隣接する外側領域から被処理基板の内側の周辺部のイオンの流れを調整して、被処理基板の周辺部のイオンによる電流を調整することができる。従って、不均一の程度に応じて周波数を適当に調整することにより、均一なエッチングレートや成膜レートを得ることができる。
【００１３】
【発明の実施の形態】
以下に、本発明の実施の形態について図面を参照しながら説明する。
図１（ｂ）は、本発明の実施の形態に係るプラズマ処理装置のプラズマ処理室に設置される基板載置台の詳細を示す平面図と側面図である。
図１（ｂ）に示すように、基板載置台１６は絶縁体１７からなり、セルフバイアス電圧を発生する部分電極１８，１９が絶縁体１７に埋め込まれている。上の平面図に示すように、部分電極１８，１９のうち、中央部の部分電極１８は円板状を有し、その周辺部の部分電極１９は部分電極１８を中心として同心円状に設けられている。各部分電極１８，１９の間には絶縁体１７が介在して部分電極１８，１９同士は互いに絶縁分離されている。
【００１４】
また、部分電極１８，１９にはそれぞれマッチング回路２０，２２を介して交流電源２１，２３が接続され、交流電源２１，２３から部分電極１８，１９にそれぞれ異なる周波数ｆ0 ，ｆ1 を有する交流電力（電圧成分ＶA ・ｓｉｎ（２πｆ0 ・ｔ），ＶA ・ｓｉｎ（２πｆ1 ・ｔ））が供給される。なお、必要な場合には、図４（ａ），（ｂ）に示すように、静電吸着により基板（ウエハ）２４を基板載置台１６に固定させるため、部分電極１８には直流電源２６を接続してもよい。
【００１５】
図１（ａ）は、上記基板載置台１６が設置されたプラズマ処理装置の側面図であり、誘導結合プラズマ処理装置の例を示す。このようなプラズマ処理装置として、代表的なものには、プラズマＣＶＤ装置やプラズマエッチング装置がある。プラズマ処理装置は、図１（ａ）に示すように、プラズマ生成室１１と、これとつながり、プラズマ生成室１１で生成されたプラズマが供給されて、被処理基板に対して成膜やエッチングが行われるプラズマ処理室１５とを有する。上記基板載置台１６はプラズマ処理室１５に設置されている。
【００１６】
また、プラズマ生成室１１の周囲には高周波電力をプラズマ生成室１１に放出するアンテナコイル１２が巻回され、このアンテナコイル１２にマッチング回路１３を介して高周波電力を供給するＲＦ電源１４が接続されている。
なお、プラズマ化される反応ガスをプラズマ生成室１１に導入するガス導入口と、プラズマ生成室１１及びプラズマ処理室１５内を排気し、減圧する排気装置が接続される排気口等は図面には記載されず、省略してある。また、必要な場合、図１（ａ）の基板載置台１６の代わりに図４に示す基板載置台１６が設置されてもよい。
【００１７】
次に、上記プラズマ処理装置を用いてエッチングを行う場合について、図２，図５及び図６を参照しながら説明する。図２はプラズマ処理室１１内の側面図であり、図５は基板載置台に印加されるＲＦ電力の周波数（ｆ）と発生するセルフバイアス電圧（ＶSB）の関係を示す特性図であり、図６（ａ）はプラズマ及び基板載置台を含む系全体の電気的等価回路であり、図６（ｂ）はセルフバイアス電圧（ＶSB）の発生と被処理基板の表面電位（ＶS ）について説明する図である。
【００１８】
まず、被エッチング物としてのシリコン酸化膜が表面に形成されたウエハ２４を基板載置台１６に載置する。排気口からプラズマ生成室１１内及びプラズマ処理室１５内を排気する。所定の圧力に達したら、プラズマ生成室１１に流量１００SCCMのＣＦ4 ガスを導入し、プラズマ生成室１１内の圧力を１０mTorr に保持する。
【００１９】
次いで、ＲＦ電源１４からＲＦパワー２ｋＷの高周波電力を放出し、プラズマ生成室１１内の反応ガスをプラズマ化する。一方、基板載置台１６に埋め込まれた部分電極１８に周波数（ｆ0）５００ｋＨｚ，電力５００Ｗの高周波電力（電圧成分：ＶA・Ｓｉｎ（２πｆ0・ｔ））を供給するとともに、部分電極１９に周波数（ｆ1）１００ｋＨｚ，電力５００Ｗの高周波電力（電圧成分：ＶA・Ｓｉｎ（２πｆ1・ｔ））を供給する。なお、必要な場合、図４（ｂ）に示すように、直流電源２６をフィルタ２５を介して電極１８に接続して直流電圧を印加し、静電吸着によりウエハ２４を基板載置台１６に固定する。
【００２０】
この状態を保持することにより、プラズマが下流のプラズマ処理室１５に流れてきてウエハが負電圧にバイアスされた状態でシリコン酸化膜がエッチングされる。
即ち、部分電極１８と１９とは絶縁分離されているため、図６（ａ）に示すように、２つの経路でそれぞれ独立にプラズマ中の電子による電流とイオンによる電流の合成電流ｉS が流れ、各々の部分電極１８，１９にそれぞれ、図５の傾向にしたがって、周波数（ｆ0 ，ｆ1 ）に対応した負のセルフバイアス電圧ＶSB0 ，ＶSB1 が発生する。即ち、一方では、合成電流ｉS はウエハ２４及び基板載置台１６及び部分電極１８を介して流れ、部分電極１８により基板載置台１６には負のセルフバイアス電圧ＶSB0 が発生する。他方では、合成電流ｉS は基板載置台１６及び部分電極１９を介して流れ、部分電極１９により基板載置台１６には部分電極１８による負のセルフバイアス電圧よりもさらに絶対値の大きな負のセルフバイアス電圧ＶSB1 が発生する。
【００２１】
これに対応して、ウエハ２４の表面電位ＶS0よりもウエハ２４の周縁の外側周囲の基板載置台１６の表面電位ＶS1の方が負側に大きくなる。従って、イオン密度の分布が中央部で大きく、周辺部で小さい場合に、周辺部に引き寄せられるイオンが多くなり、ウエハ２４全面でイオンによる電流が均一化される。このため、シリコン酸化膜のエッチングレートが均一化される。
【００２２】
なお、図５は電極に印加した交流電力５０Ｗで取得したデータなので、上記実施の形態に対してその数値を直接適用できないが、交流電力５０Ｗ以外でも周波数（ｆ）とセルフバイアス電圧（ＶSB）との関係は同じ傾向がある。また、図６（ａ）中、ＺP0，ＺP1はともにプラズマのインピーダンスであり、容量と抵抗の並列接続で表され、ＺE はプラズマから筐体への経路に介在するインピーダンスである。
【００２３】
上記エッチング結果を図３（ａ）に示す。ウエハ２４の表面の中央部１点と周辺部４点の計５点でのシリコン酸化膜のエッチングレート（ｎｍ／ｍｉｎ）が測定された。結果によればエッチングレートのバラツキは最大１６ｎｍ／ｍｉｎだった。これに対して、図８に示す従来の構造の基板載置台４の場合の結果によれば、図３（ｂ）に示すように、エッチングレートのバラツキは最大６０ｎｍ／ｍｉｎだった。
【００２４】
これらの結果より、本発明のプラズマ処理装置によればエッチングレートの均一性を向上させることができる。
なお、上記は本発明をエッチング装置に適用しているが、プラズマＣＶＤ装置を始めとしてプラズマを用いた処理装置に適用することができる。
また、部分電極１８，１９に印加する交流電力の周波数をそれぞれ５００ｋＨｚ，１００ｋＨｚとしているが、イオン密度の分布状態により別の周波数の組み合わせでもよい。さらに、中央部の部分電極１８の方を外側周囲の電極１９の方より高い周波数にしているが、外側周囲の部分電極１９の方を中央部の部分電極１８の方より高い周波数にしてもよい。
【００２５】
更に、本発明の基板載置台は、平行平板型のプラズマ処理装置にも適用することができる。この場合、対向する一方の電極にはプラズマ生成用交流電力が供給され、他方の電極は上記基板載置台を兼ねさせるようにする。
【００２６】
【発明の効果】
以上のように、本発明の基板載置台においては、互いに絶縁分離された複数の部分電極が埋め込まれ、各部分電極にはそれぞれ周波数の異なる交流電力を供給する交流電源が接続されている。
ところで、基板載置台に埋め込まれた各部分電極に印加する交流電力の周波数が高くなるにつれてセルフバイアス電圧が低下するという関係がある。従って、上記の基板載置台を本発明のプラズマ処理装置に適用した場合、プラズマ中のイオン密度の分布にしたがって、基板載置台の場所ごとに周波数を調整し、負のセルフバイアス電圧を場所毎に調整することができる。
【００２７】
また、基板載置台の複数の部分電極のうち周辺部の１以上の部分電極が載置される被処理基板よりも大きい直径の同心円上にある場合、被処理基板の存在領域とその周縁に隣接する外側領域とでセルフバイアス電圧を単独に調整することができる。従って、被処理基板の周縁に隣接する外側領域から被処理基板の内側の周辺部のイオンの流れを調整して、被処理基板の周辺部のイオンによる電流を調整することができる。
【００２８】
以上により、本発明の半導体装置の製造方法に適用した場合、不均一の程度に応じて周波数を適当に調整することにより、均一なエッチングレートや成膜レートを得ることができる。
【図面の簡単な説明】
【図１】図１（ａ）は、本発明の実施の形態に係るプラズマ処理装置について示す側面図であり、図１（ｂ）は、基板載置台について示す平面図である。
【図２】図２は、本発明の実施の形態に係るプラズマ処理装置を用いたエッチング方法について示す側面図である。
【図３】図３（ａ）は、本発明の実施の形態に係るプラズマ処理装置を用いたエッチング方法により得られたウエハ面内のエッチングレートのバラツキについて示す平面図であり、図３（ｂ）は、比較例に係るプラズマ処理装置を用いたエッチング方法により得られたウエハ面内のエッチングレートのバラツキについて示す平面図である。
【図４】図４（ａ）は、本発明の他の実施の形態に係る基板載置台について示す平面図、図４（ｂ）は、この基板載置台の側面図である。
【図５】図５は、本発明の実施の形態に係る基板載置台に埋め込まれた電極に印加された交流電力の周波数に対する基板載置台に発生するセルフバイアス電圧の関係を示す特性図である。
【図６】図６（ａ）は、本発明の実施の形態に係るプラズマ処理における電気的等価回路図であり、図６（ｂ）は、被処理基板を流れる電子による電流とイオンによる電流の合成電流（ｉS0）と、発生するセルフバイアス電圧（ＶSB1 ，ＶSB2 ）との関係について示す図である。
【図７】図７は、従来例に係るプラズマ処理装置について示す側面図である。
【図８】図８は、従来例に係るプラズマ処理装置を用いたエッチング方法について示す側面図である。
【符号の説明】
１１ プラズマ生成室、
１２ アンテナコイル、
１３，２０，２２ マッチング回路、
１４ ＲＦ電源、
１５ プラズマ処理室、
１６ 基板載置台、
１７ 絶縁体、
１８，１９ 部分電極、
２１，２３ 交流電源、
２４ 基板（ウエハ）、
２５ フィルタ、
２６ 直流電源。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma processing apparatus and a plasma processing method, and more particularly to a plasma processing apparatus and a plasma processing method for performing film formation and etching processing using plasma.
In the film formation and etching processes, it is desired to improve the uniformity of the film formation rate and the etching rate. Therefore, it is important to control so that ions in the plasma are uniformly incident on the substrate to be processed.
[0002]
[Prior art]
FIG. 7 shows a conventional plasma processing apparatus. As shown in FIG. 7, a coil 2 for applying high frequency power is wound around a plasma generation chamber 1, and RF power is supplied to generate plasma. Further, a film forming chamber 3 is connected to the plasma generating chamber 1, and plasma is supplied from the plasma generating chamber 1. A wafer mounting table 4 is installed in the film forming chamber 3, and a wafer 9 to be processed is mounted on the wafer mounting surface, and film forming or etching is performed by ions in the plasma. Further, the material of the wafer mounting table 4 is resin, ceramic or the like, and such a material is subjected to etching when exposed to plasma, so that the size of the wafer mounting table 4 is the same as that of the wafer 9 to be mounted. The diameter is smaller than the diameter so that the wafer mounting table 4 is not damaged.
[0003]
Also, in order to increase the efficiency of ion incidence on the wafer 9 or to increase the anisotropy of etching, a disk-like electrode 6 is placed on the wafer mounting surface in the insulator 5 of the wafer mounting table 4. It is embedded to face. Further, an RF power source 8 that supplies RF power having a frequency of 100 kHz to 20 MHz is connected to the electrode 6 via the matching circuit 7.
[0004]
When etching is performed using the plasma processing apparatus, when RF power is applied to the electrode 6, a combined current (iS) of a current caused by ions and a current caused by electrons flows from the plasma to the wafer 9 due to the alternating voltage. At this time, since the current caused by the electrons that move more easily than the current caused by the ions flows more easily than the current caused by the ions, the total amount of positive and negative charges flowing in the wafer 9 during one period of the RF power is made equal, ie, by the electrons. A negative self-bias voltage (VSB) is generated on the surface of the wafer 9 so as to decrease the current or increase the current due to ions.
[0005]
Thereby, ions in the plasma are efficiently incident on the wafer 9 or the etching anisotropy is increased.
[0006]
[Problems to be solved by the invention]
However, in the etching using the plasma processing apparatus described above, when the size of the wafer mounting table 4 is smaller than the diameter of the wafer and the frequency of the RF power is increased, the same power is applied to various parts of the wafer 9 surface. It becomes difficult. For this reason, as shown in FIG. 3B, the etching rate may vary greatly between the central portion and the peripheral portion in the wafer 9 surface.
[0007]
The present invention has been created in view of the problems of the above-described conventional example, and a plasma processing apparatus and a plasma processing method capable of improving the uniformity of the film forming rate and the etching rate within the surface of the substrate to be processed. The purpose is to provide.
[0008]
[Means for Solving the Problems]
The above object is the substrate according to the first invention, which is made of an insulator on which a substrate to be plasma-treated is placed, and an electrode for applying AC power for generating a DC bias voltage is embedded on the surface of the substrate to be processed. A mounting table, wherein the electrode is a central disk-shaped partial electrode for fixing the substrate to be processed, and a peripheral portion centered on the central partial electrode, the central portion The outer periphery of the peripheral edge of the substrate to be processed fixed to the electrode is composed of a partial electrode arranged concentrically with the central partial electrode and at a position lower than the central partial electrode, The center part electrode and the outer peripheral part electrode are insulated and separated from each other, and an AC power supply for supplying the AC power having a different frequency is connected to the partial electrode. Achieved,
A second aspect of the invention is achieved by the substrate mounting table according to the first aspect, wherein a DC power source is connected to the electrode and serves also as an electrode for electrostatically adsorbing the substrate to be processed.
A plasma generation chamber, a plasma processing chamber connected to the plasma generation chamber, and the substrate mounting table according to any one of the first and second inventions installed in the plasma processing chamber. Achieved by a plasma processing apparatus characterized by
According to a fourth aspect of the present invention, there is provided a parallel plate type plasma processing apparatus having a plasma processing chamber, and a first electrode and a second electrode provided in the plasma processing chamber so as to face each other. AC power for plasma generation is supplied to the electrode, and the second electrode is also achieved by a plasma processing apparatus that also serves as the substrate mounting table according to any one of the first and second inventions. ,
A fifth aspect of the invention is achieved by a method for manufacturing a semiconductor device, wherein a semiconductor wafer is mounted as a substrate to be processed on the substrate mounting table according to either the first or second aspect of the invention. Is done.
[0009]
In the substrate mounting table of the present invention, a plurality of partial electrodes insulated and separated from each other are embedded in the substrate mounting table, and an AC power supply for supplying AC power having a different frequency is connected to each partial electrode.
The electrical equivalent circuit of the entire system including the plasma and the substrate mounting table is as shown in FIG. 6A, and a current flows independently for each partial electrode. Further, the self-bias voltage at each partial electrode varies depending on the difference in the frequency of the AC power applied to each partial electrode embedded in the substrate mounting table. That is, as shown in FIG. 5, the absolute value of the negative self-bias voltage (VSB) decreases as the frequency (f) increases.
[0010]
Therefore, when applied to the plasma processing apparatus of the present invention provided with the above-described substrate mounting table, for example, when the etching rate is small before the electrode division, the frequency is lowered and the negative self-bias voltage is set to be negative. When the etching rate is high, the frequency is increased to reduce the absolute value of the negative self-bias voltage. As a result, the surface potentials (VS, VS1, VS2) are different, and when the etching rate was low before the division, the surface potential became negative and the current due to ions increased, and where the etching rate was high. The surface potential becomes smaller in the negative direction and the current due to ions decreases.
[0011]
Therefore, according to the method for manufacturing a semiconductor device of the present invention using this substrate mounting table, a uniform etching rate and film formation rate can be obtained by appropriately adjusting the frequency according to the degree of non-uniformity. .
Further, when one or more of the partial electrodes on the substrate mounting table are on a concentric circle having a diameter larger than that of the substrate to be processed, adjacent to the existence region of the substrate to be processed and its periphery The self-bias voltage can be independently adjusted with the outer region.
[0012]
Thereby, the flow of ions in the peripheral portion inside the substrate to be processed can be adjusted from the outer region adjacent to the periphery of the substrate to be processed, and the current caused by the ions in the peripheral portion of the substrate to be processed can be adjusted. Therefore, a uniform etching rate and film formation rate can be obtained by appropriately adjusting the frequency according to the degree of non-uniformity.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1B is a plan view and a side view showing details of the substrate mounting table installed in the plasma processing chamber of the plasma processing apparatus according to the embodiment of the present invention.
As shown in FIG. 1B, the substrate mounting table 16 is made of an insulator 17, and partial electrodes 18 and 19 that generate a self-bias voltage are embedded in the insulator 17. As shown in the plan view above, of the partial electrodes 18, 19, the central partial electrode 18 has a disc shape, and the peripheral partial electrode 19 is provided concentrically around the partial electrode 18. ing. An insulator 17 is interposed between the partial electrodes 18 and 19 so that the partial electrodes 18 and 19 are insulated from each other.
[0014]
Also, AC power supplies 21 and 23 are connected to the partial electrodes 18 and 19 via matching circuits 20 and 22, respectively, and AC signals having different frequencies f 0 and f 1 from the AC power supplies 21 and 23 to the partial electrodes 18 and 19, respectively. Electric power (voltage component V A · sin (2πf 0 · t), V A · sin (2πf 1 · t)) is supplied. If necessary, as shown in FIGS. 4A and 4B, a DC power supply 26 is provided to the partial electrode 18 in order to fix the substrate (wafer) 24 to the substrate mounting table 16 by electrostatic adsorption. You may connect.
[0015]
FIG. 1A is a side view of a plasma processing apparatus on which the substrate mounting table 16 is installed, and shows an example of an inductively coupled plasma processing apparatus. Typical examples of such a plasma processing apparatus include a plasma CVD apparatus and a plasma etching apparatus. As shown in FIG. 1A, the plasma processing apparatus is connected to the plasma generation chamber 11 and supplied with the plasma generated in the plasma generation chamber 11 to perform film formation and etching on the substrate to be processed. And a plasma processing chamber 15 to be performed. The substrate mounting table 16 is installed in the plasma processing chamber 15.
[0016]
An antenna coil 12 that discharges high-frequency power to the plasma generation chamber 11 is wound around the plasma generation chamber 11, and an RF power source 14 that supplies high-frequency power via a matching circuit 13 is connected to the antenna coil 12. ing.
Note that a gas introduction port for introducing a reaction gas to be converted into plasma into the plasma generation chamber 11, an exhaust port to which an exhaust device for exhausting and depressurizing the plasma generation chamber 11 and the plasma processing chamber 15 is connected are shown in the drawing. It is not described and is omitted. Further, if necessary, the substrate platform 16 shown in FIG. 4 may be installed instead of the substrate platform 16 of FIG.
[0017]
Next, the case where etching is performed using the plasma processing apparatus will be described with reference to FIGS. FIG. 2 is a side view of the inside of the plasma processing chamber 11, and FIG. 5 is a characteristic diagram showing the relationship between the frequency (f) of RF power applied to the substrate mounting table and the generated self-bias voltage (V SB ). FIG. 6A is an electrical equivalent circuit of the entire system including the plasma and the substrate mounting table, and FIG. 6B shows the generation of the self-bias voltage (V SB ) and the surface potential (V S ) of the substrate to be processed. It is a figure explaining.
[0018]
First, the wafer 24 having a silicon oxide film as an object to be etched formed thereon is placed on the substrate platform 16. The plasma generation chamber 11 and the plasma processing chamber 15 are exhausted from the exhaust port. When the predetermined pressure is reached, CF 4 gas having a flow rate of 100 SCCM is introduced into the plasma generation chamber 11 and the pressure in the plasma generation chamber 11 is maintained at 10 mTorr.
[0019]
Next, high frequency power of RF power 2 kW is released from the RF power source 14, and the reaction gas in the plasma generation chamber 11 is turned into plasma. On the other hand, high-frequency power (voltage component: V A · Sin (2πf 0 · t)) having a frequency (f 0 ) of 500 kHz and a power of 500 W is supplied to the partial electrode 18 embedded in the substrate mounting table 16 and also to the partial electrode 19. A high frequency power (voltage component: V A · Sin (2πf 1 · t)) having a frequency (f 1 ) of 100 kHz and a power of 500 W is supplied. If necessary, as shown in FIG. 4B, a DC power supply 26 is connected to the electrode 18 through a filter 25 to apply a DC voltage, and the wafer 24 is fixed to the substrate mounting table 16 by electrostatic adsorption. To do.
[0020]
By maintaining this state, the silicon oxide film is etched while the plasma flows into the downstream plasma processing chamber 15 and the wafer is biased to a negative voltage.
That is, since the partial electrodes 18 and 19 are isolated from each other, as shown in FIG. 6A, the combined current i S of the current caused by the electrons in the plasma and the current caused by the ions flows through the two paths independently. Negative self-bias voltages V SB0 and V SB1 corresponding to the frequencies (f 0 , f 1 ) are generated on the partial electrodes 18 and 19 in accordance with the tendency shown in FIG. That is, on the other hand, the combined current i S flows through the wafer 24, the substrate mounting table 16 and the partial electrode 18, and a negative self-bias voltage V SB0 is generated in the substrate mounting table 16 by the partial electrode 18. On the other hand, the combined current i S flows through the substrate mounting table 16 and the partial electrode 19, and the partial electrode 19 causes the negative electrode self-bias voltage having a larger absolute value than the negative self-bias voltage generated by the partial electrode 18. A bias voltage V SB1 is generated.
[0021]
Correspondingly, the surface potential V S1 of the substrate mounting table 16 around the outer periphery of the periphery of the wafer 24 becomes larger on the negative side than the surface potential V S0 of the wafer 24. Accordingly, when the ion density distribution is large in the central portion and small in the peripheral portion, more ions are attracted to the peripheral portion, and the current due to the ions is made uniform over the entire surface of the wafer 24. For this reason, the etching rate of the silicon oxide film is made uniform.
[0022]
Since FIG. 5 is data acquired with the AC power of 50 W applied to the electrode, the numerical value cannot be directly applied to the above embodiment, but the frequency (f) and the self-bias voltage (V SB ) can be applied to other than the AC power of 50 W. The relationship with is the same. In FIG. 6A , Z P0 and Z P1 are both plasma impedances, which are represented by a parallel connection of capacitance and resistance, and Z E is an impedance interposed in the path from the plasma to the casing.
[0023]
The etching result is shown in FIG. The etching rate (nm / min) of the silicon oxide film was measured at a total of five points including one point on the center of the surface of the wafer 24 and four points on the periphery. According to the results, the variation in the etching rate was 16 nm / min at the maximum. On the other hand, according to the result of the substrate mounting table 4 having the conventional structure shown in FIG. 8, the variation in the etching rate was 60 nm / min at the maximum as shown in FIG.
[0024]
From these results, the plasma processing apparatus of the present invention can improve the uniformity of the etching rate.
Although the present invention is applied to an etching apparatus in the above, it can be applied to a processing apparatus using plasma such as a plasma CVD apparatus.
Further, although the frequencies of the AC power applied to the partial electrodes 18 and 19 are 500 kHz and 100 kHz, respectively, other frequency combinations may be used depending on the ion density distribution state. Further, although the central partial electrode 18 has a higher frequency than the outer peripheral electrode 19, the outer peripheral partial electrode 19 may have a higher frequency than the central partial electrode 18. .
[0025]
Furthermore, the substrate mounting table of the present invention can also be applied to a parallel plate type plasma processing apparatus. In this case, the plasma generating AC power is supplied to one of the opposing electrodes, and the other electrode is also used as the substrate mounting table.
[0026]
【The invention's effect】
As described above, in the substrate mounting table of the present invention, a plurality of partial electrodes insulated from each other are embedded, and each partial electrode is connected to an AC power source that supplies AC power having a different frequency.
By the way, there is a relationship that the self-bias voltage decreases as the frequency of the AC power applied to each partial electrode embedded in the substrate mounting table increases. Therefore, when the above-described substrate mounting table is applied to the plasma processing apparatus of the present invention, the frequency is adjusted for each location of the substrate mounting table according to the distribution of ion density in the plasma, and the negative self-bias voltage is set for each location. Can be adjusted.
[0027]
Further, when one or more of the partial electrodes on the substrate mounting table are on a concentric circle having a diameter larger than that of the substrate to be processed, adjacent to the existence region of the substrate to be processed and its periphery The self-bias voltage can be independently adjusted with the outer region. Therefore, the flow of ions in the peripheral portion inside the substrate to be processed can be adjusted from the outer region adjacent to the periphery of the substrate to be processed, and the current caused by the ions in the peripheral portion of the substrate to be processed can be adjusted.
[0028]
As described above, when applied to the method for manufacturing a semiconductor device of the present invention, a uniform etching rate and film formation rate can be obtained by appropriately adjusting the frequency according to the degree of non-uniformity.
[Brief description of the drawings]
FIG. 1 (a) is a side view showing a plasma processing apparatus according to an embodiment of the present invention, and FIG. 1 (b) is a plan view showing a substrate mounting table.
FIG. 2 is a side view showing an etching method using the plasma processing apparatus according to the embodiment of the present invention.
FIG. 3 (a) is a plan view showing variations in the etching rate within a wafer surface obtained by an etching method using the plasma processing apparatus according to the embodiment of the present invention, and FIG. ) Is a plan view showing variations in the etching rate within a wafer surface obtained by an etching method using a plasma processing apparatus according to a comparative example.
FIG. 4 (a) is a plan view showing a substrate mounting table according to another embodiment of the present invention, and FIG. 4 (b) is a side view of the substrate mounting table.
FIG. 5 is a characteristic diagram showing a relationship of a self-bias voltage generated in the substrate mounting table with respect to the frequency of the AC power applied to the electrodes embedded in the substrate mounting table according to the embodiment of the present invention. .
FIG. 6A is an electrical equivalent circuit diagram in the plasma processing according to the embodiment of the present invention, and FIG. 6B is a diagram of currents due to electrons flowing through a substrate to be processed and currents due to ions. It is a figure which shows about the relationship between the synthetic | combination electric current ( iS0 ) and the self bias voltage ( VSB1 , VSB2 ) to generate | occur | produce.
FIG. 7 is a side view showing a plasma processing apparatus according to a conventional example.
FIG. 8 is a side view showing an etching method using a plasma processing apparatus according to a conventional example.
[Explanation of symbols]
11 Plasma generation chamber,
12 antenna coil,
13, 20, 22 matching circuit,
14 RF power supply,
15 Plasma processing chamber,
16 substrate mounting table,
17 insulator,
18, 19 Partial electrodes,
21, 23 AC power supply,
24 substrate (wafer),
25 filters,
26 DC power supply.
Claims (5)
前記電極は、前記被処理基板を固定する中央部の円板状の部分電極と、該中央部の部分電極を中心とするその周辺部であって、該中央部の部分電極に固定された前記被処理基板の周縁の外側周囲に、該中央部の部分電極に対して同心円状にかつ該中央部の部分電極よりも低い位置に配置された部分電極とで構成され、該中央部の部分電極と外側周囲の部分電極は互いに絶縁分離されて、該部分電極にはそれぞれ周波数の異なる前記交流電力を供給する交流電源が接続されていることを特徴とする基板載置台。A substrate mounting table made of an insulator in which a substrate to be processed for plasma processing is mounted and an electrode for applying AC power for generating a DC bias voltage is embedded in the surface of the processing substrate ;
The electrode includes a central disk-shaped partial electrode that fixes the substrate to be processed, and a peripheral portion centered on the central partial electrode, and is fixed to the central partial electrode. around the outside of the periphery of the substrate, is composed of a the central portion concentrically and is arranged at a position lower than the partial electrodes of the central portion portion electrode to the portion electrode, the partial electrodes of the central portion And the outer peripheral partial electrodes are insulated from each other, and the partial electrodes are connected to an AC power supply for supplying the AC power having different frequencies.
前記プラズマ生成室とつながったプラズマ処理室と、
前記プラズマ処理室内に設置された請求項１又は請求項２のいずれかに記載の基板載置台を有することを特徴とするプラズマ処理装置。A plasma generation chamber;
A plasma processing chamber connected to the plasma generation chamber;
A plasma processing apparatus comprising the substrate mounting table according to claim 1 or 2 installed in the plasma processing chamber.
前記第１の電極にはプラズマ生成用交流電力が供給され、前記第２の電極は請求項１又は請求項２のいずれかに記載の基板載置台を兼ねていることを特徴とするプラズマ処理装置。A parallel plate type plasma processing apparatus having a plasma processing chamber, and a first electrode and a second electrode provided opposite to each other in the plasma processing chamber,
3. The plasma processing apparatus according to claim 1, wherein the first electrode is supplied with AC power for plasma generation, and the second electrode also serves as the substrate mounting table according to claim 1. .
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| JP33711095A JP3949186B2 (en) | 1995-12-25 | 1995-12-25 | Substrate mounting table, plasma processing apparatus, and semiconductor device manufacturing method |
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| JP33711095A JP3949186B2 (en) | 1995-12-25 | 1995-12-25 | Substrate mounting table, plasma processing apparatus, and semiconductor device manufacturing method |
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| JPH09176860A JPH09176860A (en) | 1997-07-08 |
| JP3949186B2 true JP3949186B2 (en) | 2007-07-25 |
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|---|---|---|---|---|
| KR101114131B1 (en) * | 2005-07-29 | 2012-03-13 | 어플라이드 머티어리얼스, 인코포레이티드 | Chemical vapor deposition chamber with dual frequency bias and method for manufacturing a photomask using the same |
| TWI671850B (en) * | 2015-06-17 | 2019-09-11 | 美商應用材料股份有限公司 | Multiple electrode substrate support assembly and phase control system |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09176860A (en) | 1997-07-08 |
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