JPH07142939A - Mosfet power amplifier - Google Patents
Mosfet power amplifierInfo
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- JPH07142939A JPH07142939A JP5309684A JP30968493A JPH07142939A JP H07142939 A JPH07142939 A JP H07142939A JP 5309684 A JP5309684 A JP 5309684A JP 30968493 A JP30968493 A JP 30968493A JP H07142939 A JPH07142939 A JP H07142939A
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、携帯音響製品、携帯パ
ーソナルコンピュータ、携帯マルチメディア機器、移動
電話機等の携帯用電気機器において、音声信号を増幅す
るＭＯＳＦＥＴ電力増幅器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET power amplifier for amplifying an audio signal in portable electric equipment such as portable audio products, portable personal computers, portable multimedia equipment and mobile phones.
【０００２】[0002]
【従来の技術】携帯用電気機器の音声信号の電力増幅
は、従来ではバイポーラトランジスタ回路によって実現
されていたが、使用する電源電圧の低電圧化に伴って、
バイポーラトランジスタが本質的に持っているコレクタ
・エミッタ間飽和電圧（Ｖｃｅ）が出力電圧の利用効率
を落してしまい、結果として出力パワーが不十分となっ
たり、電力効率が低下するという問題が大きくなってき
た。2. Description of the Related Art Power amplification of a voice signal of a portable electric device has conventionally been realized by a bipolar transistor circuit, but with the decrease of the power supply voltage to be used,
The collector-emitter saturation voltage (Vce) inherent in the bipolar transistor lowers the utilization efficiency of the output voltage, resulting in insufficient output power or a problem of reduced power efficiency. Came.
【０００３】そこで、昇圧回路を付加し、電源電圧を昇
圧して電力増幅部を動作させることが行なわれてきた
が、電力効率の面の改善は進まなかった。Therefore, a booster circuit has been added to boost the power supply voltage to operate the power amplifying section, but the improvement in power efficiency has not progressed.
【０００４】一方、ＦＥＴ素子を使用して電力増幅器を
構成する試みが成された。しかし、品質の要求が厳しく
ない分野には応用されているものの、ハイファイでは充
分に高い電圧で動作させることができる場合以外は、実
用化されていない。On the other hand, attempts have been made to construct a power amplifier using FET elements. However, although it is applied to a field where quality requirements are not strict, it has not been put to practical use except when it can be operated at a sufficiently high voltage in hi-fi.
【０００５】これは、ＦＥＴは電流を駆動する能力がバ
イポーラトランジスタに劣っており、パイポーラトラン
ジスタ並に電力を駆動しようとすると、それ以上に無効
電力（貫通電流による）を消費する結果になることが不
可避であるからである。This is because the FET is inferior to the bipolar transistor in the ability to drive the current, and if it is attempted to drive the electric power as much as the bipolar transistor, the reactive power (through current) is consumed more than that. Is inevitable.
【０００６】ところで、近年バイアス電流を出力振幅に
応じて制御する方法を実用化して、大振幅のときだけ電
流駆動能力を増加させて電力効率を改善した、図２に示
すようなＭＯＳＦＥＴ電力増幅器が提案されている（IE
EE J.SOLID STATE CIRCUITS,Vol.SC-17,no.6,pp929-98
2, Dec.1982 ）。この図２の回路は準ソースホロワ電力
増幅器とよばれるもので、図中、１は入力端子、２は出
力端子、３は正側増幅段、４は負側増幅器段である。ま
た、Ｑ１は出力用ＰＭＯＳＦＥＴ、Ｑ２は出力用ＮＭＯ
ＳＦＥＴであり、ＣＭＯＳ構成の電力増幅段を構成す
る。By the way, in recent years, a MOSFET power amplifier as shown in FIG. 2 has been put into practical use in which a method of controlling a bias current according to an output amplitude is put into practical use, and current driving capability is increased only when the amplitude is large to improve power efficiency. Proposed (IE
EE J.SOLID STATE CIRCUITS, Vol.SC-17, no.6, pp929-98
2, Dec.1982). The circuit of FIG. 2 is called a quasi-source follower power amplifier. In the figure, 1 is an input terminal, 2 is an output terminal, 3 is a positive amplification stage, and 4 is a negative amplification stage. Q1 is an output PMOSFET, Q2 is an output NMO.
It is an SFET and constitutes a power amplification stage having a CMOS structure.
【０００７】またこのような準ソースホロワ電力増幅器
においては、入力無信号時の消費電力低減化のために、
図３に示すように、増幅段３、４に対して入力オフセッ
トを持たせる方法も提案されている。Ｖ１、Ｖ２が入力
オフセット電圧である（IEEEJ.SOLID STATE CIRCUITS,V
ol.SC-20,no.6,pp1200-1205, Dec.1982 ）。Further, in such a quasi-source follower power amplifier, in order to reduce power consumption when there is no signal input,
As shown in FIG. 3, a method of providing an input offset to the amplification stages 3 and 4 has also been proposed. V1 and V2 are input offset voltages (IEEE J.SOLID STATE CIRCUITS, V
ol.SC-20, no.6, pp1200-1205, Dec.1982).
【０００８】[0008]
【発明が解決しようとする課題】ところで、電力増幅器
に求められる資質として、出力電圧範囲が広いこと、大
電流を駆動できること及び回路内部の消費電流が少ない
こと等が挙げられる。上記した準ソースホロワ増幅器
は、基本的に入力電圧が出力電圧に等しいボルテージホ
ロワ回路として動作するが、出力レベルを電源電圧範囲
でフルスイングさせようとすると、増幅段３、４の入力
範囲を全電源電圧範囲まで拡大し、いわゆるRAIL TO RA
IL 動作（フルスイング動作）を行なわせなければなら
ない。By the way, the qualities required for the power amplifier include a wide output voltage range, the ability to drive a large current, and the low current consumption in the circuit. The above-mentioned quasi-source follower amplifier basically operates as a voltage follower circuit in which the input voltage is equal to the output voltage. However, when the output level is to be fully swung in the power supply voltage range, the input range of the amplification stages 3 and 4 is completely reduced. Expanded to the power supply voltage range, so-called RAIL TO RA
IL operation (full swing operation) must be performed.
【０００９】しかし、ここに使用するエンハンスメント
形ＭＯＳＦＥＴは、閾値（Ｖｔｈ）以下の入力では動作
しないため、上記フルスイング動作を得るためには、回
路部品数が増加し、複雑化してしまうことが避けられな
い。However, since the enhancement type MOSFET used here does not operate at an input below the threshold value (Vth), in order to obtain the above full swing operation, it is avoided that the number of circuit components increases and the circuit becomes complicated. I can't.
【００１０】かといって、入力範囲に制限のある図２、
図３に示した従来の増幅器を用いると、その入力範囲外
の信号については、上記増幅器の出力電圧が所望の電圧
に安定せず、ＭＯＳＦＥＴＱ１、Ｑ２間に過大な貫通電
流が流れたり、得られる出力電圧が飽和し音声品質が劣
化する等の問題がある。However, the input range is limited as shown in FIG.
When the conventional amplifier shown in FIG. 3 is used, for a signal outside the input range, the output voltage of the amplifier does not stabilize to a desired voltage, and an excessive shoot-through current flows between the MOSFETs Q1 and Q2, or is obtained. There is a problem that the output voltage is saturated and the voice quality is deteriorated.
【００１１】本発明の目的は、出力電圧を電源レベルま
で安定的に駆動できるようにし、上記した問題を解決し
た電力増幅器を提供することである。An object of the present invention is to provide a power amplifier capable of stably driving an output voltage up to a power supply level and solving the above problems.
【００１２】[0012]
【課題を解決するための手段】本発明の目的は、電力出
力段がＣＭＯＳ構成からなるプッシュプル型のＭＯＳＦ
ＥＴ電力増幅器において、入力電圧が正電源電圧に近い
第１の所定値以上、又は負電源電圧に近い第２の所定値
以下になるとこれを検出する検出手段と、該検出手段の
検出動作により、駆動されている側の電力出力ＭＯＳＦ
ＥＴと反対側の電力出力ＭＯＳＦＥＴをカットオフさせ
る補正手段とを設けたことを特徴とするＭＯＳＦＥＴ電
力増幅器によって達成される。SUMMARY OF THE INVENTION An object of the present invention is to provide a push-pull type MOSF whose power output stage has a CMOS structure.
In the ET power amplifier, when the input voltage becomes equal to or higher than a first predetermined value close to the positive power supply voltage or becomes equal to or lower than a second predetermined value close to the negative power supply voltage, a detection unit detects the input voltage and a detection operation of the detection unit. Power output MOSF on the driven side
And a correction means for cutting off the power output MOSFET on the side opposite to ET.
【００１３】また、入力信号の正側信号を増幅する正側
増幅段と、該正側増幅段の出力信号を増幅する電力出力
ＰＭＯＳＦＥＴと、入力信号の負側信号を増幅する負側
増幅段と、該負側増幅段の出力信号を増幅し上記電力出
力ＰＭＯＳＦＥＴと相補形に接続される電力出力ＮＭＯ
ＳＦＥＴとを具備し、入力電圧が正電源電圧に近い第１
の所定値以上になると上記負側増幅段内のＭＯＳＦＥＴ
がフローテンィグ状態になり、負電源電圧に近い第２の
所定値以下になると上記正側増幅段内のＭＯＳＦＥＴが
フローティング状態になるプッシュプル型のＭＯＳＦＥ
Ｔ電力増幅器において、上記入力電圧が上記第１の所定
値以上になるとこれを検出する第１の検出手段と、該第
１の検出手段の検出出力によって上記ＮＭＯＳＦＥＴを
カットオフさせる第１の補正手段と、上記入力電圧が上
記第２の所定値以下になるとこれを検出する第２の検出
手段と、該第２の検出手段の検出出力によって上記ＰＭ
ＯＳＦＥＴをカットオフさせる第２の補正手段とを設け
たことを特徴とするＭＯＳＦＥＴ電力増幅器によっても
達成される。A positive amplification stage for amplifying the positive side signal of the input signal, a power output PMOSFET for amplifying the output signal of the positive side amplification stage, and a negative side amplification stage for amplifying the negative side signal of the input signal. , A power output NMO that amplifies the output signal of the negative amplification stage and is connected in a complementary form to the power output PMOSFET.
A first SFET with an input voltage close to the positive power supply voltage
MOSFET above the negative side amplification stage
Becomes a floating state, and when the voltage becomes a second predetermined value or less close to the negative power source voltage, the MOSFET in the positive side amplification stage becomes a floating state.
In the T power amplifier, first detecting means for detecting when the input voltage becomes equal to or higher than the first predetermined value, and first correcting means for cutting off the NMOSFET by a detection output of the first detecting means. And the second detection means for detecting when the input voltage becomes equal to or lower than the second predetermined value, and the PM output by the detection output of the second detection means.
It is also achieved by a MOSFET power amplifier characterized in that a second correction means for cutting off the OSFET is provided.
【００１４】[0014]
【実施例】以下、本発明の実施例について説明する。図
１はその一実施例の電力増幅器の回路図である。本実施
例では、正側増幅段３を、差動接続のＮＭＯＳＦＥＴＱ
３、Ｑ４、その能動負荷としてのカレントミラー接続の
ＰＭＯＳＦＥＴＱ５、Ｑ６、差動回路の動作電流を決め
る電流源用のＮＭＯＳＦＥＴＱ７、その差動回路から出
力を取り出すＰＭＯＳＦＥＴＱ８、電流源用のＮＭＯＳ
ＦＥＴＱ９から構成している。この内、ＭＯＳＦＥＴＱ
３〜Ｑ７はＭＯＳＦＥＴ差動増幅器を構成し、ＭＯＳＦ
ＥＴＱ８、Ｑ９は増幅出力部を構成する。Ｖｓ１は定電
圧である。EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of a power amplifier of the embodiment. In the present embodiment, the positive side amplification stage 3 is connected to a differentially connected NMOSFET Q.
3, Q4, PMOSFETs Q5 and Q6 in a current mirror connection as an active load thereof, NMOSFET Q7 for a current source that determines the operating current of the differential circuit, PMOSFET Q8 for extracting an output from the differential circuit, and NMOS for a current source
It is composed of FET Q9. Of these, MOSFETQ
3 to Q7 constitute a MOSFET differential amplifier, and MOSF
ETQ8 and ETQ form an amplification output section. Vs1 is a constant voltage.
【００１５】また、負側増幅段４は、差動接続のＰＭＯ
ＳＦＥＴＱ１０、Ｑ１１、その能動負荷としてのカレン
トミラー接続のＮＭＯＳＦＥＴＱ１２、Ｑ１３、差動回
路の動作電流を決める電流源用のＰＭＯＳＦＥＴＱ１
４、その差動回路から出力を取り出すＮＭＯＳＦＥＴＱ
１５、電流源用のＰＭＯＳＦＥＴＱ１６から構成してい
る。この内ＭＯＳＦＥＴＱ１０〜Ｑ１４はＭＯＳＦＥＴ
差動増幅器を構成し、ＭＯＳＦＥＴＱ１５、Ｑ１６は増
幅出力部を構成する。Ｖｓ２は定電圧である。The negative amplification stage 4 is a differentially connected PMO.
SFETs Q10 and Q11, NMOSFETs Q12 and Q13 in current mirror connection as active loads thereof, and PMOSFET Q1 for current source that determines the operating current of the differential circuit.
4. NMOSFET Q that takes output from the differential circuit
15, PMOSFET Q16 for current source. Of these, MOSFETs Q10 to Q14 are MOSFETs
A differential amplifier is formed, and the MOSFETs Q15 and Q16 form an amplification output section. Vs2 is a constant voltage.
【００１６】このような基本的な回路において、本実施
例では、正側増幅段３のレファレンス側ＮＭＯＳＦＥＴ
Ｑ３の出力を受けるＰＭＯＳＦＥＴＱ１７とそこに接続
される電流源としてのＮＭＯＳＦＥＴＱ１８とにより正
側検出回路５を構成し、そこで得られる検出信号を、電
力出力ＰＭＯＳＦＥＴＱ１のゲートと正電源電圧Ｖｄｄ
との間に接続したＰＭＯＳＦＥＴＱ１９からなる正側補
正回路６に印加している。In such a basic circuit, in this embodiment, the reference side NMOSFET of the positive side amplification stage 3 is used.
The PMOSFET Q17 that receives the output of Q3 and the NMOSFET Q18 as a current source that is connected to the PMOSFET Q17 constitute the positive-side detection circuit 5, and the detection signal obtained there is supplied to the gate of the power output PMOSFET Q1 and the positive power supply voltage Vdd.
It is applied to the positive side correction circuit 6 composed of a PMOSFET Q19 connected between and.
【００１７】また、負側増幅段４においても、レファレ
ンス側ＰＭＯＳＦＥＴＱ１０の出力を受けるＮＭＯＳＦ
ＥＴＱ２０とそこに接続される電流源としてのＰＭＯＳ
ＦＥＴＱ２１とにより負側検出回路７を構成し、そこで
得られる出力信号を電力出力ＮＭＯＳＦＥＴＱ２のゲー
トと接地との間に接続したＮＭＯＳＦＥＴＱ２２からな
る負側補正回路８に印加している。Also in the negative side amplification stage 4, the NMOSF which receives the output of the reference side PMOSFET Q10.
ETQ20 and PMOS as a current source connected to it
The FET Q21 constitutes the negative side detection circuit 7, and the output signal obtained there is applied to the negative side correction circuit 8 composed of the NMOSFET Q22 connected between the gate of the power output NMOSFET Q2 and the ground.
【００１８】さて、この回路では、正側増幅段３と電力
出力ＰＭＯＳＦＥＴＱ１がボルテージホロワとして動作
し、また負側増幅段４と電力出力ＮＭＯＳＦＥＴＱ２が
ボルテージホロワとして動作するので、出力端子２に現
れる電圧が入力端子１の電圧に等しくなるように動作す
る。In this circuit, the positive amplification stage 3 and the power output PMOSFET Q1 operate as a voltage follower, and the negative amplification stage 4 and the power output NMOSFET Q2 operate as a voltage follower, so that they appear at the output terminal 2. It operates so that the voltage becomes equal to the voltage of the input terminal 1.
【００１９】ところが、この入力端子１の電圧が電源電
圧Ｖｄｄ近くにまで高くなると、負側増幅段４のＰＭＯ
ＳＦＥＴＱ１０、Ｑ１１がカットオフするので、そこの
ＮＭＯＳＦＥＴＱ１２、Ｑ１３もカットオフし、ＮＭＯ
ＳＦＥＴＱ１５のゲートがフローティング状態（又は接
地状態）になる。However, when the voltage of the input terminal 1 rises to near the power supply voltage Vdd, the PMO of the negative side amplification stage 4 is increased.
Since the SFETs Q10 and Q11 are cut off, the NMOSFETs Q12 and Q13 there are also cut off and the NMO
The gate of the SFET Q15 goes into a floating state (or ground state).
【００２０】よって、このままでは、電力出力ＮＭＯＳ
ＦＥＴＱ２が不安定になって動作（オン）することも有
り得、この場合にはオンしている他方の電力出力ＰＭＯ
ＳＦＥＴＱ１との間に貫通電流が流れて無駄な電流が消
費されるばかりか、出力電圧や電流の低下が起こる事態
が発生する。Therefore, in this state, the power output NMOS
It is possible that the FET Q2 becomes unstable and operates (turns on). In this case, the other power output PMO that is turned on.
Not only the through current flows between the SFETQ1 and the SFETQ1 and unnecessary current is consumed, but also the output voltage and the current decrease.
【００２１】このような場合に、本実施例では負側検出
回路７と負側補正回路８が有効に機能する。上記したよ
うに入力端子１の電圧が電源電圧Ｖｄｄ近くにまで上昇
しＰＭＯＳＦＥＴＱ１０がカットオフしたとき、ＮＭＯ
ＳＦＥＴＱ１２、Ｑ１３と共に負側検出回路７のＮＭＯ
ＳＦＥＴＱ２０もカットオフするので、ＰＭＯＳＦＥＴ
Ｑ２１のドレイン電圧（Ｖｄｄに近い電圧）が負側補正
回路８のＮＭＯＳＦＥＴＱ２１のゲート電圧に印加し、
そのＮＭＯＳＦＥＴＱ２２がオンする。この結果、電力
出力ＮＭＯＳＦＥＴＱ２のゲートが接地されるので、そ
のＮＭＯＳＦＥＴＱ２は完全にカットオフし、そこに貫
通電流が流れることはない。なお、以上の動作は入力端
子１の電圧が正側のある電圧範囲の場合に限られ、負側
の電圧が入力された場合にはＮＭＯＳＦＥＴ２２はソー
ス・ゲートがほぼ同一電位となりオンすることはないの
で、負側の出力用ＭＯＳＦＥＴＱ２の動作を妨げること
はない。In such a case, the negative side detection circuit 7 and the negative side correction circuit 8 function effectively in this embodiment. As described above, when the voltage of the input terminal 1 rises to near the power supply voltage Vdd and the PMOSFET Q10 cuts off, the NMO
NMO of the negative side detection circuit 7 together with SFETs Q12 and Q13
SFET Q20 also cuts off, so PMOSFET
The drain voltage of Q21 (voltage close to Vdd) is applied to the gate voltage of the NMOSFET Q21 of the negative side correction circuit 8,
The NMOSFET Q22 turns on. As a result, since the gate of the power output NMOSFET Q2 is grounded, the NMOSFET Q2 is completely cut off, and a through current does not flow there. Note that the above operation is limited to the case where the voltage of the input terminal 1 is within a certain voltage range on the positive side, and when the voltage on the negative side is input, the NMOSFET 22 does not turn on because the source and gate have substantially the same potential. Therefore, the operation of the output MOSFET Q2 on the negative side is not hindered.
【００２２】一方、入力端子１に入力する電圧が接地電
圧近くにまで低下したときは、今度は正側増幅段３のＮ
ＭＯＳＦＥＴＱ３、Ｑ４がカットオフし、カレントミラ
ーＰＭＯＳＦＥＴＱ５、Ｑ６もカットオフして、ＰＭＯ
ＳＦＥＴＱ８のゲートがフローテンィグ状態（又は電源
電位）となるが、このときは正側検出回路５のＰＭＯＳ
ＦＥＴＱ１７もカットオフになり、正側補正回路６のＰ
ＭＯＳＦＥＴＱ１９がオンして、電力出力ＰＭＯＳＦＥ
ＴＱ１をカットオフさせ、貫通電流の発生を防止する。
なお、以上の動作は入力端子１の電圧が接地電位に近い
電圧範囲の場合に限られ、正側の電圧が入力された場合
にはＰＭＯＳＦＥＴ１９はソース・ゲートがほぼ同一電
位となりオンすることはないので、正側の出力用ＭＯＳ
ＦＥＴＱ１の動作を妨げることはない。On the other hand, when the voltage input to the input terminal 1 drops to near the ground voltage, this time the N of the positive amplification stage 3 is increased.
The MOSFETs Q3 and Q4 are cut off, the current mirror PMOSFETs Q5 and Q6 are also cut off, and the PMO
The gate of the SFET Q8 is in a floating state (or power supply potential). At this time, the PMOS of the positive side detection circuit 5 is
The FET Q17 is also cut off, and P of the positive side correction circuit 6
MOSFET Q19 turns on, power output PMOSFE
Cut off TQ1 to prevent the generation of through current.
Note that the above operation is limited to the case where the voltage of the input terminal 1 is in the voltage range close to the ground potential, and when the positive side voltage is input, the PMOSFET 19 has substantially the same potential as the source and gate and does not turn on. Therefore, the positive output MOS
It does not interfere with the operation of the FET Q1.
【００２３】以上から、入力端子１に入力する電圧が電
源電圧近くにまで高くなり、若しくは接地電圧近くにま
で低下したときでも、電力出力ＭＯＳＦＥＴＱ１、Ｑ２
間を流れる貫通電流が発生することはなく、出力端子２
の電圧をフルスイングさせることが可能となる。From the above, even when the voltage input to the input terminal 1 becomes high near the power supply voltage or drops near the ground voltage, the power output MOSFETs Q1, Q2
No through current flowing between the output terminals 2
It is possible to make the voltage of the full swing.
【００２４】このように、本実施例では正側増幅段３の
差動回路を流れる電流が減少乃至０になると、当該正側
の電力出力ＰＭＯＳＦＥＴＱ１をカットオフさせ、負側
増幅段４の差動回路を流れる電流が減少乃至０になると
当該負極側の電力出力ＮＭＯＳＦＥＴＱ２をカットオフ
させるものであるが、入力電圧の検出は増幅段３、４内
の差動回路内の電圧を検出することに限られるものでは
なく、入力端子１に印加した電圧をそこで直接検出して
も良く、また電力出力ＭＯＳＦＥＴＱ１、Ｑ２のカット
オフ制御は、そこに制御用トランジスタを直列接続して
これを入力電圧の振幅が大きく又は小さくなったときに
オフさせることでも、貫通電流の発生を防止できる。As described above, in this embodiment, when the current flowing through the differential circuit of the positive amplification stage 3 decreases or becomes zero, the positive power output PMOSFET Q1 is cut off, and the differential of the negative amplification stage 4 is changed. When the current flowing through the circuit decreases or becomes zero, the power output NMOSFET Q2 on the negative electrode side is cut off, but the detection of the input voltage is limited to the detection of the voltage in the differential circuit in the amplification stages 3 and 4. Alternatively, the voltage applied to the input terminal 1 may be directly detected there, and the cut-off control of the power output MOSFETs Q1 and Q2 is performed by connecting a control transistor in series to the cutoff control and the amplitude of the input voltage The generation of the shoot-through current can also be prevented by turning it off when it becomes large or small.
【００２５】[0025]
【発明の効果】以上から本発明によれば、駆動能力向上
のために出力電圧をフルスイングさせようとする場合
に、貫通電流が発生することが確実に防止されるので、
安定的に完全なフルスイングを実現できるばかりか、無
効な消費電流を防止でき、更に特別部品点数が増加する
こともないという利点がある。As described above, according to the present invention, when a full swing of the output voltage is attempted in order to improve the driving capability, it is possible to reliably prevent the generation of a through current.
Not only can a stable full swing be realized, but invalid current consumption can be prevented, and the number of special parts does not increase.
【図１】 本発明の一実施例の電力増幅器の回路図であ
る。FIG. 1 is a circuit diagram of a power amplifier according to an embodiment of the present invention.
【図２】 従来の準ソースホロワ電力増幅器のブロック
図である。FIG. 2 is a block diagram of a conventional quasi-source follower power amplifier.
【図３】 従来の別の準ソースホロワ電力増幅器のブロ
ック図である。FIG. 3 is a block diagram of another conventional quasi-source follower power amplifier.
１：入力端子、２：出力端子、３：正側増幅段、４：負
側増幅段、５：正側検出回路、６：正側補正回路、７：
負側検出回路、８：負側補正回路。1: Input terminal, 2: Output terminal, 3: Positive amplification stage, 4: Negative amplification stage, 5: Positive detection circuit, 6: Positive correction circuit, 7:
Negative side detection circuit, 8: Negative side correction circuit.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０３Ｆ 3/345 Ｂ 8124−5Ｊ Ｈ０３Ｋ 17/16 Ｌ 9184−5Ｊ 17/687 Continuation of front page (51) Int.Cl. 6 Identification code Office reference number FI Technical indication location H03F 3/345 B 8124-5J H03K 17/16 L 9184-5J 17/687
Claims (2)
シュプル型のＭＯＳＦＥＴ電力増幅器において、入力電
圧が正電源電圧に近い第１の所定値以上、又は負電源電
圧に近い第２の所定値以下になるとこれを検出する検出
手段と、該検出手段の検出動作により、駆動されている
側の電力出力ＭＯＳＦＥＴと反対側の電力出力ＭＯＳＦ
ＥＴをカットオフさせる補正手段とを設けたことを特徴
とするＭＯＳＦＥＴ電力増幅器。1. A push-pull MOSFET power amplifier having a CMOS power output stage, wherein an input voltage is equal to or higher than a first predetermined value close to a positive power supply voltage or lower than a second predetermined value close to a negative power supply voltage. In this case, the detection means for detecting this and the power output MOSF on the side opposite to the power output MOSFET on the driven side by the detection operation of the detection means.
A MOSFET power amplifier, comprising: a correction means for cutting off ET.
段と、該正側増幅段の出力信号を増幅する電力出力ＰＭ
ＯＳＦＥＴと、入力信号の負側信号を増幅する負側増幅
段と、該負側増幅段の出力信号を増幅し上記電力出力Ｐ
ＭＯＳＦＥＴと相補形に接続される電力出力ＮＭＯＳＦ
ＥＴとを具備し、 入力電圧が正電源電圧に近い第１の所定値以上になると
上記負側増幅段内のＭＯＳＦＥＴがフローテンィグ状態
になり、負電源電圧に近い第２の所定値以下になると上
記正側増幅段内のＭＯＳＦＥＴがフローティング状態に
なるプッシュプル型のＭＯＳＦＥＴ電力増幅器におい
て、 上記入力電圧が上記第１の所定値以上になるとこれを検
出する第１の検出手段と、該第１の検出手段の検出出力
によって上記ＮＭＯＳＦＥＴをカットオフさせる第１の
補正手段と、上記入力電圧が上記第２の所定値以下にな
るとこれを検出する第２の検出手段と、該第２の検出手
段の検出出力によって上記ＰＭＯＳＦＥＴをカットオフ
させる第２の補正手段とを設けたことを特徴とするＭＯ
ＳＦＥＴ電力増幅器。2. A positive amplification stage for amplifying a positive signal of an input signal, and a power output PM for amplifying an output signal of the positive amplification stage.
The OSFET, the negative side amplification stage for amplifying the negative side signal of the input signal, and the power output P for amplifying the output signal of the negative side amplification stage.
Power output NMOSF connected complementary to MOSFET
ET, and when the input voltage is equal to or higher than a first predetermined value close to the positive power supply voltage, the MOSFET in the negative amplification stage is in a floating state, and is equal to or lower than a second predetermined value close to the negative power supply voltage. In a push-pull type MOSFET power amplifier in which a MOSFET in a positive side amplification stage is in a floating state, a first detecting means for detecting the input voltage when the input voltage is equal to or higher than the first predetermined value, and the first detection means. First correction means for cutting off the NMOSFET by the detection output of the means, second detection means for detecting the input voltage when the input voltage becomes equal to or lower than the second predetermined value, and detection by the second detection means. A second correction means for cutting off the PMOSFET according to the output is provided.
SFET power amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30968493A JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30968493A JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07142939A true JPH07142939A (en) | 1995-06-02 |
| JP3178494B2 JP3178494B2 (en) | 2001-06-18 |
Family
ID=17996039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30968493A Expired - Fee Related JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3178494B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000013152A (en) * | 1998-01-13 | 2000-01-14 | Xerox Corp | Analog video buffer |
| JP2003092873A (en) * | 2001-09-19 | 2003-03-28 | Fuji Electric Co Ltd | Switching power supply circuit and its semiconductor integrated circuit |
| JP2006050296A (en) * | 2004-08-05 | 2006-02-16 | Nec Corp | Differential amplifier, and data driver of display device using the same |
| WO2016152079A1 (en) * | 2015-03-20 | 2016-09-29 | Seiko Epson Corporation | Liquid ejecting device, driver circuit, and head unit |
-
1993
- 1993-11-17 JP JP30968493A patent/JP3178494B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000013152A (en) * | 1998-01-13 | 2000-01-14 | Xerox Corp | Analog video buffer |
| JP2003092873A (en) * | 2001-09-19 | 2003-03-28 | Fuji Electric Co Ltd | Switching power supply circuit and its semiconductor integrated circuit |
| JP2006050296A (en) * | 2004-08-05 | 2006-02-16 | Nec Corp | Differential amplifier, and data driver of display device using the same |
| WO2016152079A1 (en) * | 2015-03-20 | 2016-09-29 | Seiko Epson Corporation | Liquid ejecting device, driver circuit, and head unit |
| US10245827B2 (en) | 2015-03-20 | 2019-04-02 | Seiko Epson Corporation | Liquid ejecting device, driver circuit, and head unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3178494B2 (en) | 2001-06-18 |
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