JP3178494B2 - MOSFET power amplifier - Google Patents
MOSFET power amplifierInfo
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- JP3178494B2 JP3178494B2 JP30968493A JP30968493A JP3178494B2 JP 3178494 B2 JP3178494 B2 JP 3178494B2 JP 30968493 A JP30968493 A JP 30968493A JP 30968493 A JP30968493 A JP 30968493A JP 3178494 B2 JP3178494 B2 JP 3178494B2
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- power
- pmosfet
- amplification stage
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Description
【０００１】[0001]
【産業上の利用分野】本発明は、携帯音響製品、携帯パ
ーソナルコンピュータ、携帯マルチメディア機器、移動
電話機等の携帯用電気機器において、音声信号を増幅す
るＭＯＳＦＥＴ電力増幅器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET power amplifier for amplifying an audio signal in a portable audio product, a portable personal computer, a portable multimedia device, a portable electric device such as a mobile telephone.
【０００２】[0002]
【従来の技術】携帯用電気機器の音声信号の電力増幅
は、従来ではバイポーラトランジスタ回路によって実現
されていたが、使用する電源電圧の低電圧化に伴って、
バイポーラトランジスタが本質的に持っているコレクタ
・エミッタ間飽和電圧（Ｖｃｅ）が出力電圧の利用効率
を落してしまい、結果として出力パワーが不十分となっ
たり、電力効率が低下するという問題が大きくなってき
た。2. Description of the Related Art Conventionally, power amplification of audio signals of portable electric equipment has been realized by a bipolar transistor circuit.
The bipolar transistor inherently has a collector-emitter saturation voltage (Vce), which lowers the utilization efficiency of the output voltage, resulting in a problem that the output power becomes insufficient or the power efficiency decreases. Have been.
【０００３】そこで、昇圧回路を付加し、電源電圧を昇
圧して電力増幅部を動作させることが行なわれてきた
が、電力効率の面の改善は進まなかった。Therefore, a booster circuit has been added to boost the power supply voltage to operate the power amplifying unit. However, power efficiency has not been improved.
【０００４】一方、ＦＥＴ素子を使用して電力増幅器を
構成する試みが成された。しかし、品質の要求が厳しく
ない分野には応用されているものの、ハイファイでは充
分に高い電圧で動作させることができる場合以外は、実
用化されていない。On the other hand, attempts have been made to construct a power amplifier using FET elements. However, although it is applied to fields where the demands on quality are not strict, it has not been put to practical use except in the case where it can be operated at a sufficiently high voltage in Hi-Fi.
【０００５】これは、ＦＥＴは電流を駆動する能力がバ
イポーラトランジスタに劣っており、パイポーラトラン
ジスタ並に電力を駆動しようとすると、それ以上に無効
電力（貫通電流による）を消費する結果になることが不
可避であるからである。[0005] This is because FETs are inferior to bipolar transistors in their ability to drive current, and attempting to drive power as much as bipolar transistors results in the consumption of more reactive power (due to through current). Is inevitable.
【０００６】ところで、近年バイアス電流を出力振幅に
応じて制御する方法を実用化して、大振幅のときだけ電
流駆動能力を増加させて電力効率を改善した、図２に示
すようなＭＯＳＦＥＴ電力増幅器が提案されている（IE
EE J.SOLID STATE CIRCUITS,Vol.SC-17,no.6,pp929-98
2, Dec.1982 ）。この図２の回路は準ソースホロワ電力
増幅器とよばれるもので、図中、１は入力端子、２は出
力端子、３は正側増幅段、４は負側増幅器段である。ま
た、Ｑ１は出力用ＰＭＯＳＦＥＴ、Ｑ２は出力用ＮＭＯ
ＳＦＥＴであり、ＣＭＯＳ構成の電力増幅段を構成す
る。In recent years, a method of controlling a bias current according to an output amplitude has been put to practical use, and a MOSFET power amplifier as shown in FIG. Proposed (IE
EE J.SOLID STATE CIRCUITS, Vol.SC-17, no.6, pp929-98
2, Dec. 1982). The circuit shown in FIG. 2 is called a quasi-source follower power amplifier. In the figure, reference numeral 1 denotes an input terminal, 2 denotes an output terminal, 3 denotes a positive-side amplifier stage, and 4 denotes a negative-side amplifier stage. Q1 is an output PMOSFET, and Q2 is an output NMO.
It is an SFET and constitutes a power amplification stage having a CMOS configuration.
【０００７】またこのような準ソースホロワ電力増幅器
においては、入力無信号時の消費電力低減化のために、
図３に示すように、増幅段３、４に対して入力オフセッ
トを持たせる方法も提案されている。Ｖ１、Ｖ２が入力
オフセット電圧である（IEEEJ.SOLID STATE CIRCUITS,V
ol.SC-20,no.6,pp1200-1205, Dec.1982 ）。In such a quasi-source follower power amplifier, in order to reduce power consumption when there is no input signal,
As shown in FIG. 3, a method of giving an input offset to the amplification stages 3 and 4 has also been proposed. V1 and V2 are input offset voltages (IEEEJ. SOLID STATE CIRCUITS, V
ol. SC-20, no. 6, pp1200-1205, Dec. 1982).
【０００８】[0008]
【発明が解決しようとする課題】ところで、電力増幅器
に求められる資質として、出力電圧範囲が広いこと、大
電流を駆動できること及び回路内部の消費電流が少ない
こと等が挙げられる。上記した準ソースホロワ増幅器
は、基本的に入力電圧が出力電圧に等しいボルテージホ
ロワ回路として動作するが、出力レベルを電源電圧範囲
でフルスイングさせようとすると、増幅段３、４の入力
範囲を全電源電圧範囲まで拡大し、いわゆるRAIL TO RA
IL 動作（フルスイング動作）を行なわせなければなら
ない。By the way, the qualities required of the power amplifier include a wide output voltage range, the ability to drive a large current, and the low current consumption inside the circuit. The quasi-source follower amplifier described above basically operates as a voltage follower circuit in which the input voltage is equal to the output voltage. Expanded to the power supply voltage range, so-called RAIL TO RA
IL operation (full swing operation) must be performed.
【０００９】しかし、ここに使用するエンハンスメント
形ＭＯＳＦＥＴは、閾値（Ｖｔｈ）以下の入力では動作
しないため、上記フルスイング動作を得るためには、回
路部品数が増加し、複雑化してしまうことが避けられな
い。However, the enhancement type MOSFET used here does not operate at an input lower than the threshold value (Vth). Therefore, in order to obtain the above-mentioned full swing operation, increase in the number of circuit components and complication are avoided. I can't.
【００１０】かといって、入力範囲に制限のある図２、
図３に示した従来の増幅器を用いると、その入力範囲外
の信号については、上記増幅器の出力電圧が所望の電圧
に安定せず、ＭＯＳＦＥＴＱ１、Ｑ２間に過大な貫通電
流が流れたり、得られる出力電圧が飽和し音声品質が劣
化する等の問題がある。On the other hand, FIG. 2 in which the input range is limited,
When the conventional amplifier shown in FIG. 3 is used, for a signal outside the input range, the output voltage of the amplifier is not stabilized at a desired voltage, and an excessive through current flows or is obtained between MOSFETs Q1 and Q2. There is a problem that the output voltage is saturated and the voice quality is deteriorated.
【００１１】本発明の目的は、出力電圧を電源レベルま
で安定的に駆動できるようにし、上記した問題を解決し
た電力増幅器を提供することである。An object of the present invention is to provide a power amplifier capable of stably driving an output voltage to a power supply level and solving the above problem.
【００１２】[0012]
【課題を解決するための手段】上記課題を解決するため
本発明は、入力信号の正側信号を増幅するＮＭＯＳＦＥ
Ｔの差動対をもつ正側増幅段と、該正側増幅段の出力信
号を増幅する電力出力ＰＭＯＳＦＥＴと、上記入力信号
の負側信号を増幅するＰＭＯＳＦＥＴの差動対をもつ負
側増幅段と、該負側増幅段の出力信号を増幅し上記電力
出力ＰＭＯＳＦＥＴと相補形に接続される電力出力ＮＭ
ＯＳＦＥＴとを具備するプッシュプル型のＭＯＳＦＥＴ
電力増幅器において、上記正側増幅段の出力電圧を常時
監視し上記正側増幅段の上記差動対のＮＭＯＳＦＥＴが
カットオフするとこれを検出する第１の検出手段と、該
第１の検出手段の検出出力によって上記電力出力ＰＭＯ
ＳＦＥＴに逆バイアスを印加し上記電力出力ＰＭＯＳＦ
ＥＴをカットオフさせる第１の補正手段と、上記負側増
幅段の出力電圧を常時監視し上記負側増幅段の上記差動
対のＰＭＯＳＦＥＴがカットオフするとこれを検出する
第２の検出手段と、該第２の検出手段の検出出力によっ
て上記電力出力ＮＭＯＳＦＥＴに逆バイアスを印加し上
記電力出力ＮＭＯＳＦＥＴをカットオフさせる第２の補
正手段と、を設けて構成した。According to the present invention, there is provided an NMOS FE for amplifying a positive signal of an input signal.
A positive amplification stage having a differential pair of T; a power output PMOSFET for amplifying an output signal of the positive amplification stage; and a negative amplification stage having a PMOSFET differential pair for amplifying a negative signal of the input signal When power is connected to amplify the output signal of the negative side amplifier stage complementary with said power output PMOSFET output NM
Push-pull type MOSFET having OSFET
In the power amplifier, first detection means for constantly monitoring the output voltage of the positive-side amplification stage and detecting when the NMOSFET of the differential pair of the positive-side amplification stage is cut off, The power output PMO according to the detection output
A reverse bias is applied to the SFET and the power output PMOSF
First correction means for cutting off ET, and second detection means for constantly monitoring the output voltage of the negative amplification stage and detecting when the PMOSFET of the differential pair in the negative amplification stage is cut off. And a second correction means for applying a reverse bias to the power output NMOSFET based on the detection output of the second detection means to cut off the power output NMOSFET.
【００１３】[0013]
【００１４】[0014]
【実施例】以下、本発明の実施例について説明する。図
１はその一実施例の電力増幅器の回路図である。本実施
例では、正側増幅段３を、差動接続のＮＭＯＳＦＥＴＱ
３、Ｑ４、その能動負荷としてのカレントミラー接続の
ＰＭＯＳＦＥＴＱ５、Ｑ６、差動回路の動作電流を決め
る電流源用のＮＭＯＳＦＥＴＱ７、その差動回路から出
力を取り出すＰＭＯＳＦＥＴＱ８、電流源用のＮＭＯＳ
ＦＥＴＱ９から構成している。この内、ＭＯＳＦＥＴＱ
３〜Ｑ７はＭＯＳＦＥＴ差動増幅器を構成し、ＭＯＳＦ
ＥＴＱ８、Ｑ９は増幅出力部を構成する。Ｖｓ１は定電
圧である。Embodiments of the present invention will be described below. FIG. 1 is a circuit diagram of a power amplifier according to one embodiment. In the present embodiment, the positive side amplification stage 3 is connected to a differentially connected NMOSFET Q
3, Q4, current mirror connected PMOSFETs Q5 and Q6 as active loads thereof, NMOSFET Q7 for a current source for determining the operating current of the differential circuit, PMOSFET Q8 for extracting an output from the differential circuit, NMOS for a current source
It is composed of an FET Q9. MOSFET Q
3-Q7 constitute a MOSFET differential amplifier, and MOSF
ETQ8 and Q9 constitute an amplification output unit. Vs1 is a constant voltage.
【００１５】また、負側増幅段４は、差動接続のＰＭＯ
ＳＦＥＴＱ１０、Ｑ１１、その能動負荷としてのカレン
トミラー接続のＮＭＯＳＦＥＴＱ１２、Ｑ１３、差動回
路の動作電流を決める電流源用のＰＭＯＳＦＥＴＱ１
４、その差動回路から出力を取り出すＮＭＯＳＦＥＴＱ
１５、電流源用のＰＭＯＳＦＥＴＱ１６から構成してい
る。この内ＭＯＳＦＥＴＱ１０〜Ｑ１４はＭＯＳＦＥＴ
差動増幅器を構成し、ＭＯＳＦＥＴＱ１５、Ｑ１６は増
幅出力部を構成する。Ｖｓ２は定電圧である。The negative side amplification stage 4 is a differentially connected PMO
SFETs Q10 and Q11, NMOSFETs Q12 and Q13 of current mirror connection as active loads thereof, and PMOSFET Q1 for a current source which determines the operating current of the differential circuit
4. NMOSFET Q for taking output from the differential circuit
15, a PMOSFET Q16 for a current source. MOSFETs Q10 to Q14 are MOSFETs
A differential amplifier is formed, and MOSFETs Q15 and Q16 form an amplification output section. Vs2 is a constant voltage.
【００１６】このような基本的な回路において、本実施
例では、正側増幅段３のレファレンス側ＮＭＯＳＦＥＴ
Ｑ３の出力を受けるＰＭＯＳＦＥＴＱ１７とそこに接続
される電流源としてのＮＭＯＳＦＥＴＱ１８とにより正
側検出回路５を構成し、そこで得られる検出信号を、電
力出力ＰＭＯＳＦＥＴＱ１のゲートと正電源電圧Ｖｄｄ
との間に接続したＰＭＯＳＦＥＴＱ１９からなる正側補
正回路６に印加している。In such a basic circuit, in this embodiment, the reference-side NMOSFET of the positive side amplification stage 3 is used.
A positive side detection circuit 5 is constituted by a PMOSFET Q17 receiving the output of Q3 and an NMOSFET Q18 as a current source connected thereto, and a detection signal obtained therefrom is transmitted to the gate of the power output PMOSFET Q1 and the positive power supply voltage Vdd.
Is applied to the positive side correction circuit 6 composed of a PMOSFET Q19 connected between the positive and negative side.
【００１７】また、負側増幅段４においても、レファレ
ンス側ＰＭＯＳＦＥＴＱ１０の出力を受けるＮＭＯＳＦ
ＥＴＱ２０とそこに接続される電流源としてのＰＭＯＳ
ＦＥＴＱ２１とにより負側検出回路７を構成し、そこで
得られる出力信号を電力出力ＮＭＯＳＦＥＴＱ２のゲー
トと接地との間に接続したＮＭＯＳＦＥＴＱ２２からな
る負側補正回路８に印加している。Also, in the negative side amplification stage 4, the NMOSF receiving the output of the reference side PMOSFET Q10
ETQ20 and PMOS connected to it as current source
The FET Q21 constitutes a negative side detection circuit 7, and the output signal obtained therefrom is applied to a negative side correction circuit 8 comprising an NMOSFET Q22 connected between the gate of the power output NMOSFET Q2 and the ground.
【００１８】さて、この回路では、正側増幅段３と電力
出力ＰＭＯＳＦＥＴＱ１がボルテージホロワとして動作
し、また負側増幅段４と電力出力ＮＭＯＳＦＥＴＱ２が
ボルテージホロワとして動作するので、出力端子２に現
れる電圧が入力端子１の電圧に等しくなるように動作す
る。In this circuit, the positive side amplification stage 3 and the power output PMOSFET Q1 operate as a voltage follower, and the negative side amplification stage 4 and the power output NMOSFET Q2 operate as a voltage follower. The operation is performed so that the voltage becomes equal to the voltage of the input terminal 1.
【００１９】ところが、この入力端子１の電圧が電源電
圧Ｖｄｄ近くにまで高くなると、負側増幅段４のＰＭＯ
ＳＦＥＴＱ１０、Ｑ１１がカットオフするので、そこの
ＮＭＯＳＦＥＴＱ１２、Ｑ１３もカットオフし、ＮＭＯ
ＳＦＥＴＱ１５のゲートがフローティング状態（又は接
地状態）になる。However, when the voltage at the input terminal 1 rises to near the power supply voltage Vdd, the PMO
Since the SFETs Q10 and Q11 are cut off, the NMOSFETs Q12 and Q13 there are also cut off and the NMO
The gate of SFET Q15 enters a floating state (or ground state).
【００２０】よって、このままでは、電力出力ＮＭＯＳ
ＦＥＴＱ２が不安定になって動作（オン）することも有
り得、この場合にはオンしている他方の電力出力ＰＭＯ
ＳＦＥＴＱ１との間に貫通電流が流れて無駄な電流が消
費されるばかりか、出力電圧や電流の低下が起こる事態
が発生する。Therefore, in this state, the power output NMOS
The FET Q2 may become unstable and operate (turn on), in which case the other power output PMO
Not only does a through current flow between the SFET Q1 and wasteful current is consumed, but also a situation occurs in which the output voltage and the current decrease.
【００２１】このような場合に、本実施例では負側検出
回路７と負側補正回路８が有効に機能する。上記したよ
うに入力端子１の電圧が電源電圧Ｖｄｄ近くにまで上昇
しＰＭＯＳＦＥＴＱ１０がカットオフしたとき、ＮＭＯ
ＳＦＥＴＱ１２、Ｑ１３と共に負側検出回路７のＮＭＯ
ＳＦＥＴＱ２０もカットオフするので、ＰＭＯＳＦＥＴ
Ｑ２１のドレイン電圧（Ｖｄｄに近い電圧）が負側補正
回路８のＮＭＯＳＦＥＴＱ２１のゲート電圧に印加し、
そのＮＭＯＳＦＥＴＱ２２がオンする。この結果、電力
出力ＮＭＯＳＦＥＴＱ２のゲートが接地されるので、そ
のＮＭＯＳＦＥＴＱ２は完全にカットオフし、そこに貫
通電流が流れることはない。なお、以上の動作は入力端
子１の電圧が正側のある電圧範囲の場合に限られ、負側
の電圧が入力された場合にはＮＭＯＳＦＥＴ２２はソー
ス・ゲートがほぼ同一電位となりオンすることはないの
で、負側の出力用ＭＯＳＦＥＴＱ２の動作を妨げること
はない。In such a case, in this embodiment, the negative side detection circuit 7 and the negative side correction circuit 8 function effectively. As described above, when the voltage of the input terminal 1 rises to near the power supply voltage Vdd and the PMOSFET Q10 is cut off, the NMO
NMO of negative side detection circuit 7 together with SFETs Q12 and Q13
Since the SFET Q20 also cuts off, the PMOSFET
The drain voltage of Q21 (a voltage close to Vdd) is applied to the gate voltage of the NMOSFET Q21 of the negative correction circuit 8,
The NMOSFET Q22 turns on. As a result, the gate of the power output NMOSFET Q2 is grounded, so that the NMOSFET Q2 is completely cut off, and no through current flows therethrough. Note that the above operation is limited to the case where the voltage of the input terminal 1 is within a certain positive voltage range. Therefore, the operation of the negative side output MOSFET Q2 is not prevented.
【００２２】一方、入力端子１に入力する電圧が接地電
圧近くにまで低下したときは、今度は正側増幅段３のＮ
ＭＯＳＦＥＴＱ３、Ｑ４がカットオフし、カレントミラ
ーＰＭＯＳＦＥＴＱ５、Ｑ６もカットオフして、ＰＭＯ
ＳＦＥＴＱ８のゲートがフローテンィグ状態（又は電源
電位）となるが、このときは正側検出回路５のＰＭＯＳ
ＦＥＴＱ１７もカットオフになり、正側補正回路６のＰ
ＭＯＳＦＥＴＱ１９がオンして、電力出力ＰＭＯＳＦＥ
ＴＱ１をカットオフさせ、貫通電流の発生を防止する。
なお、以上の動作は入力端子１の電圧が接地電位に近い
電圧範囲の場合に限られ、正側の電圧が入力された場合
にはＰＭＯＳＦＥＴ１９はソース・ゲートがほぼ同一電
位となりオンすることはないので、正側の出力用ＭＯＳ
ＦＥＴＱ１の動作を妨げることはない。On the other hand, when the voltage input to the input terminal 1 drops to near the ground voltage, the N
The MOSFETs Q3 and Q4 are cut off, and the current mirror PMOSFETs Q5 and Q6 are also cut off.
The gate of the SFET Q8 enters a floating state (or power supply potential).
The FET Q17 is also cut off, and the P
MOSFET Q19 turns on, and power output PMOSFE
TQ1 is cut off to prevent generation of a through current.
The above operation is limited to the case where the voltage of the input terminal 1 is within a voltage range close to the ground potential. When a positive voltage is input, the source and the gate of the PMOSFET 19 become substantially the same and the PMOSFET 19 does not turn on. So the positive side output MOS
It does not hinder the operation of the FET Q1.
【００２３】以上から、入力端子１に入力する電圧が電
源電圧近くにまで高くなり、若しくは接地電圧近くにま
で低下したときでも、電力出力ＭＯＳＦＥＴＱ１、Ｑ２
間を流れる貫通電流が発生することはなく、出力端子２
の電圧をフルスイングさせることが可能となる。As described above, even when the voltage input to the input terminal 1 increases to near the power supply voltage or decreases to near the ground voltage, the power output MOSFETs Q1, Q2
No through current flows between the output terminals 2 and
Can be fully swung.
【００２４】このように、本実施例では正側増幅段３の
差動回路を流れる電流が減少乃至０になると、当該正側
の電力出力ＰＭＯＳＦＥＴＱ１をカットオフさせ、負側
増幅段４の差動回路を流れる電流が減少乃至０になると
当該負極側の電力出力ＮＭＯＳＦＥＴＱ２をカットオフ
させるものであるが、入力電圧の検出は増幅段３、４内
の差動回路内の電圧を検出することに限られるものでは
なく、入力端子１に印加した電圧をそこで直接検出して
も良く、また電力出力ＭＯＳＦＥＴＱ１、Ｑ２のカット
オフ制御は、そこに制御用トランジスタを直列接続して
これを入力電圧の振幅が大きく又は小さくなったときに
オフさせることでも、貫通電流の発生を防止できる。As described above, in the present embodiment, when the current flowing through the differential circuit of the positive side amplification stage 3 decreases to 0, the power output PMOSFET Q1 on the positive side is cut off and the differential of the negative side amplification stage 4 is cut off. When the current flowing through the circuit decreases or becomes 0, the power output NMOSFET Q2 on the negative electrode side is cut off. However, the detection of the input voltage is limited to the detection of the voltage in the differential circuits in the amplification stages 3 and 4. Instead, the voltage applied to the input terminal 1 may be directly detected there, and the cut-off control of the power output MOSFETs Q1 and Q2 may be performed by connecting a control transistor in series therewith to reduce the input voltage amplitude. By turning off when it becomes larger or smaller, it is possible to prevent the generation of a through current.
【００２５】[0025]
【発明の効果】以上から本発明によれば、駆動能力向上
のために出力電圧をフルスイングさせようとする場合
に、貫通電流が発生することが確実に防止されるので、
安定的に完全なフルスイングを実現できるばかりか、無
効な消費電流を防止でき、更に特別部品点数が増加する
こともないという利点がある。As described above, according to the present invention, when the output voltage is to be fully swung to improve the driving capability, the generation of the through current is reliably prevented.
In addition to stably achieving a complete full swing, there is an advantage that an ineffective current consumption can be prevented and the number of special components does not increase.
【図１】 本発明の一実施例の電力増幅器の回路図であ
る。FIG. 1 is a circuit diagram of a power amplifier according to an embodiment of the present invention.
【図２】 従来の準ソースホロワ電力増幅器のブロック
図である。FIG. 2 is a block diagram of a conventional quasi-source follower power amplifier.
【図３】 従来の別の準ソースホロワ電力増幅器のブロ
ック図である。FIG. 3 is a block diagram of another conventional quasi-source follower power amplifier.
【符号の説明】 １：入力端子、２：出力端子、３：正側増幅段、４：負
側増幅段、５：正側検出回路、６：正側補正回路、７：
負側検出回路、８：負側補正回路。[Description of Signs] 1: Input terminal, 2: Output terminal, 3: Positive side amplification stage, 4: Negative side amplification stage, 5: Positive side detection circuit, 6: Positive side correction circuit, 7:
Negative side detection circuit, 8: negative side correction circuit.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平６−326525（ＪＰ，Ａ) 特開 昭59−54306（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H03F 1/00 - 3/36 ────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-6-326525 (JP, A) JP-A-59-54306 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H03F 1/00-3/36
Claims (1)
ＥＴの差動対をもつ正側増幅段と、該正側増幅段の出力
信号を増幅する電力出力ＰＭＯＳＦＥＴと、上記入力信
号の負側信号を増幅するＰＭＯＳＦＥＴの差動対をもつ
負側増幅段と、該負側増幅段の出力信号を増幅し上記電
力出力ＰＭＯＳＦＥＴと相補形に接続される電力出力Ｎ
ＭＯＳＦＥＴとを具備するプッシュプル型のＭＯＳＦＥ
Ｔ電力増幅器において、 上記正側増幅段の出力電圧を常時監視し上記正側増幅段
の上記差動対のＮＭＯＳＦＥＴがカットオフするとこれ
を検出する第１の検出手段と、該第１の検出手段の検出
出力によって上記電力出力ＰＭＯＳＦＥＴに逆バイアス
を印加し上記電力出力ＰＭＯＳＦＥＴをカットオフさせ
る第１の補正手段と、上記負側増幅段の出力電圧を常時
監視し上記負側増幅段の上記差動対のＰＭＯＳＦＥＴが
カットオフするとこれを検出する第２の検出手段と、該
第２の検出手段の検出出力によって上記電力出力ＮＭＯ
ＳＦＥＴに逆バイアスを印加し上記電力出力ＮＭＯＳＦ
ＥＴをカットオフさせる第２の補正手段と、を設けたこ
とを特徴とするＭＯＳＦＥＴ電力増幅器。1. An NMOS transistor for amplifying a positive signal of an input signal.
A positive side amplification stage having a differential pair of ET; a power output PMOSFET for amplifying an output signal of the positive side amplification stage; and a negative side amplification stage having a PMOSFET differential pair for amplifying a negative side signal of the input signal When power is connected to amplify the output signal of the negative side amplifier stage complementary with said power output PMOSFET output N
Push-pull MOSFE with MOSFET
In the T power amplifier, first detection means for constantly monitoring the output voltage of the positive amplification stage and detecting when the NMOSFET of the differential pair of the positive amplification stage is cut off, and the first detection means Reverse bias on the power output PMOSFET by the detection output of
And the first correction means for cutting off the power output PMOSFET and constantly monitoring the output voltage of the negative amplification stage and detecting when the PMOSFET of the differential pair of the negative amplification stage is cut off. The power output NMO is determined by a second detection means and a detection output of the second detection means.
A reverse bias is applied to the SFET and the power output NMOSF
A MOSFET power amplifier, comprising: second correction means for cutting off ET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30968493A JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30968493A JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07142939A JPH07142939A (en) | 1995-06-02 |
| JP3178494B2 true JP3178494B2 (en) | 2001-06-18 |
Family
ID=17996039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30968493A Expired - Fee Related JP3178494B2 (en) | 1993-11-17 | 1993-11-17 | MOSFET power amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3178494B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959475A (en) * | 1998-01-13 | 1999-09-28 | Xerox Corporation | Complementary push-pull CMOS source follower analog video buffer |
| JP2003092873A (en) * | 2001-09-19 | 2003-03-28 | Fuji Electric Co Ltd | Switching power supply circuit and its semiconductor integrated circuit |
| JP4826073B2 (en) * | 2004-08-05 | 2011-11-30 | 日本電気株式会社 | Differential amplifier and data driver for display device using the same |
| JP6728761B2 (en) * | 2015-03-20 | 2020-07-22 | セイコーエプソン株式会社 | Liquid ejection device, drive circuit and head unit |
-
1993
- 1993-11-17 JP JP30968493A patent/JP3178494B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07142939A (en) | 1995-06-02 |
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