JPH07131075A - Image device - Google Patents

Image device

Info

Publication number
JPH07131075A
JPH07131075A JP29446793A JP29446793A JPH07131075A JP H07131075 A JPH07131075 A JP H07131075A JP 29446793 A JP29446793 A JP 29446793A JP 29446793 A JP29446793 A JP 29446793A JP H07131075 A JPH07131075 A JP H07131075A
Authority
JP
Japan
Prior art keywords
image
wiring
pad
substrate
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29446793A
Other languages
Japanese (ja)
Inventor
Shunji Murano
俊次 村野
Koji Miyauchi
宏治 宮内
Toshihiro Yoshimura
俊宏 吉村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP29446793A priority Critical patent/JPH07131075A/en
Publication of JPH07131075A publication Critical patent/JPH07131075A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/788—Means for moving parts
    • H01L2224/78821—Upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/78822—Rotational mechanism
    • H01L2224/78823—Pivoting mechanism
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To prevent a pad on wire bonding from being damaged due to sinking, etc., of a hard printed-circuit board. CONSTITUTION:When load from a capillary 01 is directly applied to a hard printed-circuit board 2, the root of a sinking pad of the printed-circuit board 2 is cut. A copper-plated film 14 and a gold-plated film 16 are laminated on a copper foil 6 of individual wiring to constitute a thick pad 12, thus scattering force from the capillary 01. Also, the section of the pad 12 is in trapezoid shape, thus absorbing force from the capillary 01 due to the deformation of the pad 12.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の利用分野】この発明はＬＥＤヘッドやＥＬヘッ
ド，イメージセンサ等の画像装置に関し、特に画像アレ
イをプリント基板上に配置し、基板配線のボンディング
パッドにアレイの個々の画像素子をワイヤボンディング
した画像装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image device such as an LED head, an EL head, an image sensor, etc., and more particularly, an image array is arranged on a printed circuit board, and individual image elements of the array are wire-bonded to bonding pads of substrate wiring. Related to the imaging device.

【０００２】[0002]

【従来技術】ＬＥＤヘッドやＥＬヘッド，イメージセン
サ等の画像装置では、高密度の基板配線が必要とされる
ため、ガラス基板に薄膜配線を設けたものが用いられ
る。しかしながら薄膜配線は装置コストが大きく、かつ
成膜に時間を要するため量産性に劣る。そこで発明者
は、図１０〜図１２のように、安価なプリント基板２を
用いることを検討した。銅箔からなる個別配線４を同じ
膜厚のまま幅広にして幅広部６とし、ボンディングパッ
ドとして用いた。また幅広部６以外の部分は樹脂膜８で
被覆した。図１１のように、幅広部６にキャピラリー０
１で金線１０をワイヤボンドすると、幅広部６の損傷が
続出した。その後の検討により、幅広部６の損傷の原因
について、以下のことが判明した。 1) 用いた基板２（ガラスエポキシ基板）はボンディン
グ時の加熱等で軟化し、キャピラリー０１からの圧力
（図の白抜き矢印）で変形して幅広部６が沈み込み、幅
広部６の根元に剪断応力が集中して切断される。 2) キャピラリー０１を基板２に正確に垂直に立てるこ
とは難しく、僅かでも傾きが有ると図の白抜き矢印のよ
うに斜めの力が加わる。この力は幅広部６の根元に集中
し、図１１の力の向きの場合幅広部６を個別配線４の上
にまくれ上がらせるように働き、逆向きの場合幅広部６
を個別配線４から引き剥すように働き、いずれの場合も
幅広部６の根元が切断される。 3) ボンディング終了後に、特にセカンドボンド終了後
に、キャピラリー０１を引き上げワイヤ１０を引きちぎ
ると、図の太い黒抜き矢印の向きの力が加わり、幅広部
６の基板２への付着力が充分でないため、幅広部６が基
板２から剥離する。 4) ボンディング時のキャピラリー０１の振動（超音波
ボンドの場合、図の細い黒抜き矢印）は幅広部６に伝わ
って、幅広部６の剥離や根元の切断等の原因となる。 5) 基板配線の密度を１／２に低下させるため、図１２
のように画像アレイの両側に個別配線４，４を配置する
と、キャピラリー０１が傾いた際に幅広部６がさらに損
傷しやすくなる。 6) 個別配線４の厚さを増すことは配線ピッチの低下に
通じ、画像装置の場合好ましくない。 7) 1)〜5)の現象はプリント基板に特有のもので、ガラ
ス基板では生じない。2. Description of the Related Art In image devices such as LED heads, EL heads, and image sensors, high-density substrate wiring is required. Therefore, glass substrates provided with thin film wiring are used. However, the thin film wiring has a large device cost and requires a long time to form a film, which is inferior in mass productivity. Therefore, the inventor has considered using an inexpensive printed circuit board 2 as shown in FIGS. The individual wiring 4 made of copper foil was widened with the same film thickness to form a wide portion 6, which was used as a bonding pad. The portions other than the wide portion 6 were covered with the resin film 8. As shown in FIG. 11, the wide portion 6 has no capillary 0.
When the gold wire 10 was wire-bonded in No. 1, the wide portion 6 was continuously damaged. As a result of the subsequent examination, the following was found out regarding the cause of damage to the wide portion 6. 1) The used substrate 2 (glass epoxy substrate) was softened by heating during bonding, etc., and was deformed by the pressure from the capillary 01 (white arrow in the figure) to sink the wide portion 6, and at the base of the wide portion 6. Shear stress is concentrated and cut. 2) It is difficult to set the capillary 01 vertically to the substrate 2 accurately, and if there is a slight inclination, an oblique force is applied as shown by the white arrow in the figure. This force is concentrated at the base of the wide portion 6, and in the case of the force direction shown in FIG. 11, it works to raise the wide portion 6 above the individual wiring 4, and in the opposite direction, the wide portion 6
Is separated from the individual wiring 4, and in any case, the base of the wide portion 6 is cut. 3) When the capillary 01 is pulled up and the wire 10 is torn off after the bonding is completed, especially after the second bond is completed, the force in the direction of the thick black arrow in the figure is applied, and the adhesion of the wide portion 6 to the substrate 2 is not sufficient. The wide portion 6 is separated from the substrate 2. 4) The vibration of the capillary 01 at the time of bonding (in the case of ultrasonic bonding, a thin black arrow in the figure) is transmitted to the wide portion 6 and causes peeling of the wide portion 6 or cutting of the root. 5) In order to reduce the density of the board wiring by half,
When the individual wirings 4 and 4 are arranged on both sides of the image array as described above, the wide portion 6 is more likely to be damaged when the capillary 01 is tilted. 6) Increasing the thickness of the individual wiring 4 leads to a reduction in wiring pitch, which is not preferable in the case of an image device. 7) The phenomena 1) to 5) are peculiar to printed circuit boards and do not occur on glass substrates.

【０００３】[0003]

【発明の課題】この発明の課題は以下の点にある。 1) プリント基板を用いた画像装置において、画像装置
に必要な基板配線の密度が得られ、しかもワイヤボンデ
ィング性能が良好で、ボンディング時の圧力や剪断応
力，引っ張り力，振動等によるボンディングパッドの損
傷が無い、画像装置を提供する（請求項１〜６）。 2) ボンディング時の圧力や剪断応力，引っ張り力，振
動等への、ボンディングパッドの耐久性をさらに向上さ
せる（請求項４）。 3) ボンディングパッドの形成と基板の両面配線のため
のスルーホールとを、同じプロセスで形成できるように
する（請求項６）。 4) 基板配線の密度を１／２に低下させ、かつ画像アレ
イの共通電極を基板配線と分離して取り出すことを可能
にする（請求項６）。The problems of the present invention are as follows. 1) In an image device using a printed circuit board, the density of the board wiring required for the image device can be obtained, the wire bonding performance is good, and the bonding pad is damaged due to pressure, shear stress, tensile force, vibration, etc. at the time of bonding. There is no image device (claims 1 to 6). 2) To further improve the durability of the bonding pad against pressure, shearing stress, tensile force, vibration, etc. during bonding (claim 4). 3) The bonding pad and the through hole for double-sided wiring of the substrate can be formed in the same process (claim 6). 4) The density of the substrate wiring is reduced to 1/2, and the common electrode of the image array can be taken out separately from the substrate wiring (claim 6).

【０００４】[0004]

【発明の構成】この発明の画像装置は、画像アレイをプ
リント基板の主面上に配置して、その個々の画像素子
を、基板配線のボンディングパッドにワイヤボンディン
グした画像装置において、前記ボンディングパッドを、
銅箔と銅箔上に積層した銅メッキ膜とで構成したことを
特徴とする。好ましくは、ボンディングパッドの断面形
状を不均一にし、底面で断面積が大きく、表面で断面積
が小さな形状とする。さらに好ましくは、前記銅箔を厚
さ１２〜１５μｍ、前記銅メッキ膜を厚さ１５〜１８μ
ｍとし、銅メッキ膜上に金メッキ膜を積層する。また好
ましくは、ボンディングパッドは基板配線の他の部分よ
りも幅広とし、かつ該幅広部の両端とその周囲の基板と
を樹脂膜で被覆する。According to the image device of the present invention, the image array is arranged on the main surface of the printed board, and the individual image elements are wire-bonded to the bonding pads of the board wiring. ,
It is characterized by being composed of a copper foil and a copper plating film laminated on the copper foil. Preferably, the bonding pad has a non-uniform cross-sectional shape so that the bottom surface has a large cross-sectional area and the surface has a small cross-sectional area. More preferably, the copper foil has a thickness of 12 to 15 μm, and the copper plating film has a thickness of 15 to 18 μm.
m, and a gold plating film is laminated on the copper plating film. Further, preferably, the bonding pad is wider than the other part of the board wiring, and both ends of the wide part and the substrate around it are covered with a resin film.

【０００５】この発明の画像装置はまた、画像アレイを
プリント基板の主面上に配置して、その個々の画像素子
を基板配線のボンディングパッドにワイヤボンディング
した画像装置において、ボンディングパッドを、基板配
線上に金属ボールを固着して構成したことを特徴とす
る。In the image device according to the present invention, the image array is arranged on the main surface of the printed board, and the individual image elements are wire-bonded to the bonding pads of the board wiring. It is characterized in that a metal ball is fixed on the top.

【０００６】この発明の画像装置はまた、多数の画像ア
レイを基板の第１の主面上に列状に配置するとともに、
多数の個別配線からなる基板配線を前記主面上に設け、
各画像アレイの個々の画像素子を基板配線のボンディン
グパッドにワイヤボンディングした画像装置において、
前記基板配線を、画像アレイの列の一方の側に設けた第
１の基板配線と、他方の側に設けた第２の基板配線とで
構成し、これらの基板配線の少なくとも一方を画像アレ
イ２個毎に分断して、銅メッキ膜で内面を被覆したスル
ーホールと基板の第２の主面に設けた他の基板配線とを
介して相互に接続し、第１の主面に設けた基板配線に銅
メッキ膜を積層して前記ボンディングパッドを構成した
ことを特徴とする。The imager of this invention also arranges a number of image arrays in rows on the first major surface of the substrate, and
Providing a board wiring consisting of a large number of individual wirings on the main surface,
In the image device in which the individual image elements of each image array are wire-bonded to the bonding pad of the board wiring,
The board wiring is composed of a first board wiring provided on one side of a column of the image array and a second board wiring provided on the other side, and at least one of these board wiring is provided in the image array 2 A substrate provided on the first main surface, which is divided into pieces and connected to each other through a through hole whose inner surface is coated with a copper plating film and another substrate wiring provided on the second main surface of the substrate. It is characterized in that a copper plating film is laminated on the wiring to form the bonding pad.

【０００７】画像装置は実施例で示したＬＥＤヘッドの
他に、イメージセンサやＥＬヘッド等でも良い。The image device may be an image sensor, an EL head, or the like, in addition to the LED head shown in the embodiment.

【０００８】[0008]

【発明の作用】この発明では、基板配線のボンディング
パッドを、銅箔上に銅メッキ膜を積層して構成する。こ
の結果ボンディングパッドは肉厚になり、ワイヤボンデ
ィング時の圧力や剪断応力，引っ張り力，振動等に耐え
ることができる（請求項１）。ボンディング時の圧力等
をパッドの変形で吸収するため、パッドは断面形状が不
均一で、底面で断面積が大きく表面で断面積が小さなも
のとする（請求項２）。銅箔はボンディングフォースに
耐えるため１２μｍ以上の膜厚が好ましく、銅メッキ膜
は銅箔に比べ軟質で、ボンディング時に変形して、ボン
ディングフォースを吸収するため、１５μｍ以上の膜厚
が好ましい。基板上に高ピッチで配線を施すため、銅箔
と銅メッキ膜の合計膜厚は３０μｍ程度が好ましく、こ
こでは銅箔の膜厚上限を１５μｍ、銅メッキ膜の膜厚上
限を１８μｍとし、これらの合計膜厚を３０±３μｍと
する。さらに、銅メッキ膜の酸化を防止し、ワイヤボン
ディングを容易にするため金メッキ膜を積層する（請求
項３）。パッドを基板配線の他の部分よりも幅広にし、
かつパッドの両端部を樹脂膜で基板に押え込んでボンデ
ィング時のパッドの損傷を防止する（請求項４）。According to the present invention, the bonding pad for the substrate wiring is formed by laminating the copper plating film on the copper foil. As a result, the bonding pad becomes thick and can withstand pressure, shear stress, tensile force, vibration, etc. during wire bonding (claim 1). Since the pressure during bonding is absorbed by the deformation of the pad, the pad has a non-uniform cross-sectional shape and has a large cross-sectional area on the bottom surface and a small cross-sectional area on the surface (claim 2). The copper foil preferably has a film thickness of 12 μm or more in order to withstand the bonding force, and the copper plating film is softer than the copper foil and deforms during bonding to absorb the bonding force. Therefore, the film thickness of 15 μm or more is preferable. Since wiring is provided on the substrate at a high pitch, the total thickness of the copper foil and the copper plating film is preferably about 30 μm. Here, the upper limit of the thickness of the copper foil is 15 μm and the upper limit of the thickness of the copper plating film is 18 μm. The total film thickness is set to 30 ± 3 μm. Further, a gold plating film is laminated in order to prevent oxidation of the copper plating film and facilitate wire bonding (claim 3). Make the pad wider than the rest of the board wiring,
Moreover, both ends of the pad are pressed against the substrate by the resin film to prevent damage to the pad during bonding (claim 4).

【０００９】この発明ではまた、基板配線上に金属ボー
ルを固着し、ボンディングパッドとする（請求項５）。
このようにすれば、肉厚で金属ボールの変形によりボン
ディング時の衝撃を吸収できるボンディングパッドが得
られる。According to the present invention, metal balls are fixed on the substrate wiring to form bonding pads (claim 5).
By doing so, it is possible to obtain a bonding pad which is thick and can absorb the impact at the time of bonding due to the deformation of the metal ball.

【００１０】この発明ではまた、多数の個別配線からな
る基板配線を第１の基板配線と第２の基板配線とに分割
し、画像アレイの列の両側に１つずつ配置して基板配線
の密度を１／２に低下させ、ガラスエポキシ等の硬質プ
リント基板を用いることを可能にする。基板配線の少な
くとも一方は、画像アレイ２個毎に分断して、スルーホ
ールと基板の第２の主面に設けた他の基板配線を介して
相互に接続する。スルーホールは銅メッキ膜で導電化
し、同じ銅メッキ膜をボンディングパッド部に積層し、
パッドを肉厚にする（請求項６）。According to the present invention, the board wiring composed of a large number of individual wirings is divided into the first board wiring and the second board wiring, and one board wiring is arranged on each side of the column of the image array to arrange the board wiring density. Is reduced to 1/2, and it is possible to use a hard printed circuit board such as glass epoxy. At least one of the board wirings is divided for every two image arrays, and is connected to each other through the through hole and another board wiring provided on the second main surface of the board. The through hole is made conductive with a copper plating film, and the same copper plating film is laminated on the bonding pad section.
The pad is made thick (claim 6).

【００１１】[0011]

【実施例】図１〜図７に実施例の各ボンディングパッド
を示し、図８，図９にＬＥＤヘッドを例に基板配線や画
像アレイの配置を示す。最初にボンディングパッドにつ
いて説明する。EXAMPLES FIGS. 1 to 7 show the respective bonding pads of the examples, and FIGS. 8 and 9 show the arrangement of substrate wirings and image arrays by taking an LED head as an example. First, the bonding pad will be described.

【００１２】[0012]

【ボンディングパッド】図１において、２は硬質プリン
ト基板で、例えばガラスエポキシ基板を用い、４は個別
配線で、厚さ１２〜１５μｍの銅箔を用いる。銅箔４
は、基板２への密着力を高めるため裏面を粗しておき、
表面は平滑にする。８は樹脂膜でエポキシ等のソルダレ
ジスト膜を用い、好ましくはＬＥＤ光等を吸収する顔料
を混合し、反射防止膜に兼用する。０１はワイヤボンデ
ィング用のキャピラリーで、１０は、直径２０〜３０μ
ｍの金線である。１２はボンディングパッド、１４は銅
箔４に積層した銅メッキ膜で、１６は銅メッキ膜上に積
層した金メッキ膜である。銅箔４の表面が平滑（鏡面）
なため、金メッキ膜１６の表面も平滑で、（中間の銅メ
ッキ膜１４は平滑）、小さなボンディング荷重でワイヤ
ボンドできる。また金メッキ膜１６は銅メッキ膜１４の
酸化を防止すとともに金線１０の付着力を増し、金メッ
キ膜１６なしでは金線１０をパッド１２にボンディング
できない。ただし金メッキ膜１６をＰｄ等のメッキ膜に
変えても良い。[Bonding Pad] In FIG. 1, 2 is a hard printed board, for example, a glass epoxy board, 4 is individual wiring, and a copper foil having a thickness of 12 to 15 μm is used. Copper foil 4
Is roughened on the back side in order to increase the adhesion to the substrate 2,
Make the surface smooth. A resin film 8 is a solder resist film of epoxy or the like, preferably mixed with a pigment that absorbs LED light or the like, and also serves as an antireflection film. 01 is a capillary for wire bonding, and 10 is a diameter of 20 to 30 μm.
It is a gold wire of m. Reference numeral 12 is a bonding pad, 14 is a copper plating film laminated on the copper foil 4, and 16 is a gold plating film laminated on the copper plating film. The surface of the copper foil 4 is smooth (mirror surface)
Therefore, the surface of the gold plating film 16 is also smooth (the middle copper plating film 14 is smooth), and wire bonding can be performed with a small bonding load. Further, the gold plating film 16 prevents the copper plating film 14 from being oxidized and increases the adhesion of the gold wire 10, and the gold wire 10 cannot be bonded to the pad 12 without the gold plating film 16. However, the gold plating film 16 may be replaced with a plating film of Pd or the like.

【００１３】銅箔４を９μｍ厚とすると、厚さ１２μｍ
の銅メッキ膜１４を積層しても、ボンディング時の衝撃
でパッド１２が切断された。このことから銅箔４は１２
μｍ以上が必要である。次に銅メッキ膜１４は銅箔４に
比べ軟質で、変形によりボンディング時の衝撃を吸収す
る。厚さ１２〜１５μｍの銅箔４に対して、ボンディン
グパッド１２の切断を防止するには、厚さ１５μｍ以上
の銅メッキ膜１４が必要である。実施例での配線ルール
は、線幅が５０μｍ，ギャップが５０μｍで，銅箔４と
銅メッキ膜１４との合計膜厚が５０μｍではエッチング
が不能である。そこでこれらの合計膜厚を３０μｍ±３
μｍとするため、銅箔４を１２〜１５μｍとし、銅メッ
キ膜１４を１５〜１８μｍとした。If the thickness of the copper foil 4 is 9 μm, the thickness is 12 μm.
Even if the copper plating film 14 was laminated, the pad 12 was cut by the impact during bonding. From this, the copper foil 4 is 12
μm or more is required. Next, the copper plating film 14 is softer than the copper foil 4 and absorbs the impact during bonding due to deformation. For the copper foil 4 having a thickness of 12 to 15 μm, the copper plating film 14 having a thickness of 15 μm or more is necessary to prevent the cutting of the bonding pad 12. The wiring rule in the embodiment is that the line width is 50 μm, the gap is 50 μm, and the total film thickness of the copper foil 4 and the copper plating film 14 is 50 μm, etching is impossible. Therefore, the total film thickness of these is 30 μm ± 3
In order to set the thickness to μm, the copper foil 4 is set to 12 to 15 μm, and the copper plating film 14 is set to 15 to 18 μm.

【００１４】図２に示すように、パッド１２は長方形状
とし、底面部での幅Ｗ1を例えば９０〜１１０μｍ，長
さＬ1を１５０〜２００μｍとする。解像度３００ＤＰ
Ｉの画像装置で画像アレイの両側に個別配線を設ける
と、個別配線の配線ピッチは約１７０μｍで、パッド１
２，１２間に５０μｍのギャップを残しても、パッド１
２を配置できる。長さＬ1はワイヤボンドを容易にする
ため幅Ｗ1より大きくし、１５０〜２００μｍとした。
パッド１２はボンディング時に変形して応力を吸収する
ため肉厚かつ断面を台形状とし、底面で断面積が大き
く、表面で断面積が小さくなるようにした。パッド１２
の表面部の幅Ｗ2は例えば７０〜８０μｍとし、長さＬ2
は例えば１２０〜１８０μｍとする。線径２０〜３０μ
ｍの金線の場合、ボンディング後のボール直径は６０〜
８０μｍ程度となり、幅Ｗ2を７０〜８０μｍとする
と、パッド１２にボンディングできる。パッド１２の断
面を台形状にするには、例えば銅箔４と銅メッキ膜１４
のサイドエッチを利用し、低速でエッチングしてサイド
エッチさせ、端面からのエッチングで台形状にする。As shown in FIG. 2, the pad 12 has a rectangular shape, and the width W1 at the bottom is 90 to 110 .mu.m and the length L1 is 150 to 200 .mu.m. Resolution 300DP
When the individual wiring is provided on both sides of the image array in the image device of I, the wiring pitch of the individual wiring is about 170 μm, and the pad 1
Even if a 50 μm gap is left between 2 and 12, pad 1
2 can be placed. The length L1 is made larger than the width W1 to facilitate wire bonding and is set to 150 to 200 μm.
The pad 12 is thick and has a trapezoidal cross section in order to deform and absorb stress during bonding, and has a large cross-sectional area on the bottom surface and a small cross-sectional area on the surface. Pad 12
The width W2 of the surface portion of the is, for example, 70 to 80 μm, and the length L2
Is, for example, 120 to 180 μm. Wire diameter 20-30μ
In the case of a gold wire of m, the ball diameter after bonding is 60-
When the width W2 is about 70 to 80 μm, the pad 12 can be bonded. To make the cross section of the pad 12 trapezoidal, for example, the copper foil 4 and the copper plating film 14 are used.
Side etching is used to etch at a low speed to perform side etching, and the trapezoid is formed by etching from the end face.

【００１５】図３に、ワイヤボンディング時のパッド１
２の作用を示す。キャピラリー０１はパッド１２にボン
ディングフォースを加え、この時基板２は１００℃程度
に加熱され軟化している。プリント基板２にこの力が直
接加わると基板２の押圧部が沈み込み、パッド１２の根
元が切断される。しかし実施例では、軟質の銅メッキ膜
１４の変形でこの力を吸収し、かつ銅箔４を厚くして強
度を増している。またパッド１２の断面を台形状にし、
パッド１２が変形し易くしている。そしてパッド１２が
変形すれば、圧力を吸収できる。これらのためパッド１
２の根元での切断は生じない。キャピラリー０１が傾い
て配置されると、パッド１２を根元の個別配線４に対し
ずらそうとする力が働く。しかしこの力は銅メッキ膜１
４の変形で吸収され、パッド１２の根元の切断は生じな
い。ワイヤボンディングではこれ以外に、キャピラリー
０１から加わる超音波振動，キャピラリー０１の引き上
げ時にパッド１２に加わる引っ張り力がある。しかしこ
れらのものはいずれも、肉厚で変形し易い銅メッキ膜１
４で吸収され、パッド１２の損傷の原因とはならない。FIG. 3 shows a pad 1 for wire bonding.
The action of 2 is shown. The capillary 01 applies a bonding force to the pad 12, and at this time, the substrate 2 is heated to about 100 ° C. and softened. When this force is directly applied to the printed board 2, the pressing portion of the board 2 sinks and the root of the pad 12 is cut. However, in the embodiment, this force is absorbed by the deformation of the soft copper plating film 14, and the copper foil 4 is thickened to increase the strength. The pad 12 has a trapezoidal cross section,
The pad 12 is easily deformed. If the pad 12 is deformed, the pressure can be absorbed. Pad 1 for these
No cutting occurs at the root of 2. When the capillaries 01 are arranged so as to be inclined, a force acts to displace the pad 12 with respect to the individual wiring 4 at the base. However, this force is due to the copper plating film 1
It is absorbed by the deformation of No. 4, and the root of the pad 12 is not cut. In addition to this, in wire bonding, there are ultrasonic vibration applied from the capillary 01 and a tensile force applied to the pad 12 when the capillary 01 is pulled up. However, these are all copper plating films 1 that are thick and easily deformed.
4 is absorbed and does not cause damage to the pad 12.

【００１６】ボンディングパッド１２は肉厚で、断面が
不均一で変形し易いことが重要で、例えば図４のボンデ
ィングパッド１８のように、半球状の金ボール２０を幅
広部６に固着したものでも良い。金ボール２０を形成す
るには、金線にワイヤボールをトーチなどで形成し、ボ
ンディングしてボールを固着し、直ちに金線を切断すれ
ば良い。金ボール２０は直径が６０〜８０μｍ程度が好
ましく、ボンディング時の下向きの圧力や剪断応力，振
動，引っ張り力等を吸収する。金線に変えて、金−Ｐｄ
線等を用いても良い。It is important that the bonding pad 12 is thick, has a non-uniform cross section, and is easily deformed. For example, even if the hemispherical gold ball 20 is fixed to the wide portion 6 as in the bonding pad 18 of FIG. good. In order to form the gold ball 20, a wire ball may be formed on the gold wire with a torch or the like, the ball may be fixed by bonding, and the gold wire may be immediately cut. The gold ball 20 preferably has a diameter of about 60 to 80 μm and absorbs downward pressure, shearing stress, vibration, tensile force and the like during bonding. Change to gold wire, gold-Pd
You may use a line etc.

【００１７】図１〜図４では、肉厚で変形し易いパッド
１２，１８を用いてボンディング時の衝撃を吸収した
が、樹脂膜でパッド１２を基板２に押え込んで密着性を
向上させることを加えても良い。図１の配置では樹脂膜
８にはパッド１２を押え込む力が無い。これに対して図
５，図６のように、パッド１２の両端を樹脂膜８，２２
で押え込み、両側から基板２に密着させて固定すると、
ワイヤボンディング時の損傷をさらに小さくすることが
できる。In FIGS. 1 to 4, the pads 12 and 18 that are thick and easily deformed are used to absorb the impact during bonding. However, the pads 12 are pressed onto the substrate 2 by a resin film to improve the adhesion. May be added. In the arrangement shown in FIG. 1, the resin film 8 has no force for pressing the pad 12. On the other hand, as shown in FIGS. 5 and 6, both ends of the pad 12 are covered with the resin films 8 and 22.
Press down with, and stick it to the board 2 from both sides and fix it,
Damage during wire bonding can be further reduced.

【００１８】[0018]

【ボンディングパッドの製造工程】図７に、ボンディン
グパッド１２の製造工程を示す。裏面を粗面化し表面を
鏡面化した銅箔２４を基板２の両面に設け、スルーホー
ル２６をドリル加工する。スルーホール２６にＰｄ等の
触媒を付着させた後に、無電界銅メッキ膜２８を付着さ
せ、次いで電解メッキにより銅メッキ膜３０を設け、エ
ッチングする。図２のような台形状のパッド１２を得る
ため、サイドエッチを利用し、低速でエッチングして、
メッキ膜３０の端面からサイドエッチさせる。この後マ
スク８を形成し、金メッキ膜１６をパッド１２に設け、
マスク８には顔料を混合しておき、画像アレイからの光
の反射防止膜や個別配線４の保護膜とする。[Manufacturing Process of Bonding Pad] FIG. 7 shows a manufacturing process of the bonding pad 12. Copper foils 24 having a roughened back surface and a mirrored front surface are provided on both surfaces of the substrate 2, and the through holes 26 are drilled. After depositing a catalyst such as Pd on the through hole 26, an electroless copper plating film 28 is deposited, and then a copper plating film 30 is provided by electrolytic plating and etching is performed. In order to obtain the trapezoidal pad 12 as shown in FIG. 2, side etching is used and etching is performed at a low speed.
Side etching is performed from the end surface of the plated film 30. Thereafter, a mask 8 is formed, a gold plating film 16 is provided on the pad 12,
A pigment is mixed in the mask 8 to form an antireflection film for light from the image array and a protective film for the individual wiring 4.

【００１９】[0019]

【基板の全体配置】図８，図９に、ＬＥＤヘッドを例に
基板２の配置を示す。図８に示すように、基板２の第１
の主面上にＬＥＤアレイＬ１〜Ｌ４０を直線状に配列す
る。ここでは解像度３００ＤＰＩのＡ４対応とし、各Ｌ
ＥＤアレイＬ１〜Ｌ４０でのＬＥＤの配列ピッチを８
４.７μｍ，アレイ当りのＬＥＤの個数を６４個とす
る。第１の主面にはＬＥＤアレイの列の上下に２組の基
板配線３４，３６を設け、基板配線３４，３６はパッド
１２を除き樹脂膜８（図８では省略）で被覆する。実施
例ではＬＥＤアレイ単位での時分割駆動を行うので、基
板配線の総数は６４本となり、これを１／２ずつに分割
して、第１の基板配線３４と第２の基板配線３６とにそ
れぞれ３２本ずつの個別配線４を設ける。３８は、ボン
ディングパッド１２の列（以下単に「パッド列」）であ
る。パッド列３８は、２個のＬＥＤアレイ単位で配置さ
れ、パッドの数は６４個のＬＥＤの１／２を片側の配線
に接続し、かつＬＥＤアレイ２個を担当することから、
６４個となる。[Whole Arrangement of Substrate] FIGS. 8 and 9 show the arrangement of the substrate 2 using an LED head as an example. As shown in FIG. 8, the first of the substrate 2
The LED arrays L1 to L40 are linearly arranged on the main surface of. Here, the resolution is 300 DPI and A4 is supported, and each L
The LED array pitch in the ED arrays L1 to L40 is set to 8
It is 4.7 μm, and the number of LEDs per array is 64. Two sets of substrate wirings 34 and 36 are provided above and below the LED array column on the first main surface, and the substrate wirings 34 and 36 are covered with a resin film 8 (not shown in FIG. 8) except for the pads 12. In the embodiment, since the time-divisional driving is performed in LED array units, the total number of substrate wirings becomes 64, and this is divided into ½ to form the first substrate wiring 34 and the second substrate wiring 36. 32 individual wires 4 are provided for each. 38 is a row of bonding pads 12 (hereinafter simply referred to as "pad row"). The pad row 38 is arranged in units of two LED arrays, and since the number of pads is such that ½ of 64 LEDs is connected to the wiring on one side and two LED arrays are in charge,
It will be 64.

【００２０】４０，４０は基板２の左右に設けた基板配
線引き出し部で、それぞれ６４本の個別配線４からな
り、４２，４２は駆動ＩＣである。実施例での基板配線
３４，３６の特徴は、ＬＥＤアレイ２個毎に分断されて
いることにある。例えば基板配線３４はＬＥＤアレイ２
個毎に設けられ、ＬＥＤアレイの近傍にパッド列３８を
設けて終端としてある。このことは基板配線３６でも同
様で、パッド列３８が終端となり、パッド列３８はＬＥ
ＤアレイＬ１〜Ｌ４０の近傍に設けてある。分断した基
板配線３４，３６は図７に示したスルーホール２６と第
２の主面の個別配線を用いて、相互に接続する。基板配
線の引き出し部４０には、３２個のスルーホール２６を
並べたスルーホール列４６があり、これを第２の主面
（裏面）の配線を介して、基板配線３６に設けた３２個
のスルーホール２６（これを総称してスルーホール列５
２という）から接続する。同様に基板配線の引き出し部
４０には、３２個のスルーホール２６からなるスルーホ
ール列４８を設け、裏面の配線を介して基板配線３４の
スルーホール列５０へ接続する。スルーホール列５０で
の、スルーホールの個数は同様に３２個である。スルー
ホールは大きな配線面積を必要とするため、スルーホー
ル列５０，５２は好ましくは複数列設け、かつさらに好
ましくは基板配線３４，３６の方向に斜めに設ける。例
えば各スルーホール２６は周囲の配線とのギャップを含
めると、１個当たり約０.５ｍｍの配線幅を必要とす
る。実施例では、スルーホール列５０，５２を各２列と
し、かつ中央で折り返して実質的に４列とした。またス
ルーホール列５０，５２は基板配線３４，３６の方向に
約４５度傾けて配置した。Reference numerals 40 and 40 are board wiring lead-out portions provided on the left and right sides of the board 2, each of which is composed of 64 individual wirings 4, and 42 and 42 are drive ICs. A feature of the board wirings 34 and 36 in the embodiment is that they are divided for every two LED arrays. For example, the board wiring 34 is the LED array 2
Each pad is provided with a pad row 38 in the vicinity of the LED array as a termination. The same applies to the board wiring 36, and the pad row 38 is the termination, and the pad row 38 is LE.
It is provided near the D arrays L1 to L40. The divided substrate wirings 34 and 36 are connected to each other by using the through hole 26 shown in FIG. 7 and the individual wiring on the second main surface. The board wiring lead-out portion 40 has a through hole row 46 in which 32 through holes 26 are arranged, and the 32 through holes are provided on the board wiring 36 via the wiring on the second main surface (back surface). Through hole 26 (collectively referred to as through hole row 5
2) to connect. Similarly, the board wiring lead-out portion 40 is provided with a through hole row 48 composed of 32 through holes 26, and is connected to the through hole row 50 of the board wiring 34 via the wiring on the back surface. Similarly, the number of through holes in the through hole row 50 is 32. Since the through holes require a large wiring area, the through hole rows 50 and 52 are preferably provided in a plurality of rows, and more preferably, are provided obliquely in the direction of the board wirings 34 and 36. For example, each through hole 26 needs a wiring width of about 0.5 mm, including a gap with surrounding wiring. In the embodiment, each of the through hole rows 50 and 52 has two rows and is folded back at the center to substantially four rows. The through hole rows 50 and 52 are arranged so as to be inclined by about 45 degrees toward the board wirings 34 and 36.

【００２１】図９に裏面配線を示す。５４，５６は裏面
配線で、それぞれ個別配線を３２本平行に設けたものか
らなり、裏面配線５６はスルーホール列４６により基板
配線引き出し部４０に接続し、スルーホール列５２を介
して基板配線３６に接続する。裏面配線５０はスルーホ
ール列４８を介して基板配線引き出し部４０に接続し、
スルーホール列５０を介して基板配線３４に接続する。FIG. 9 shows the backside wiring. Reference numerals 54 and 56 denote rear surface wirings, each of which has 32 individual wirings provided in parallel. The rear surface wirings 56 are connected to the substrate wiring lead-out portion 40 by a through hole row 46, and the substrate wirings 36 are connected through a through hole row 52. Connect to. The back surface wiring 50 is connected to the board wiring drawing portion 40 through the through hole row 48,
It is connected to the board wiring 34 through the through hole row 50.

【００２２】図８に戻り、ＬＥＤアレイＬ１〜Ｌ４０の
底面には共通電極があり、基板２の第１の主面上で基板
配線３６，３６の隙間を介して共通電極端子６０に接続
する。共通電極端子６０にはパッド１２と同様に銅メッ
キ膜１４や金メッキ膜１６を積層し、半田付け等を容易
にしておくのが好ましい。樹脂膜８は共通電極端子６０
への半田付け時のソルダレジストにもなる。ＬＥＤヘッ
ドのこれ以外の構成、例えばハウジングやレンズアレイ
等は周知であり、ここでは説明を省略する。Returning to FIG. 8, there is a common electrode on the bottom surface of the LED arrays L1 to L40, which is connected to the common electrode terminal 60 on the first main surface of the substrate 2 through the gap between the substrate wirings 36, 36. It is preferable that a copper plating film 14 or a gold plating film 16 is laminated on the common electrode terminal 60 similarly to the pad 12 to facilitate soldering or the like. The resin film 8 is the common electrode terminal 60.
Also serves as a solder resist when soldering to. Other configurations of the LED head, such as a housing and a lens array, are well known and will not be described here.

【００２３】ＬＥＤアレイＬ１〜Ｌ４０の動作を示す。
ＬＥＤアレイ単位での時分割駆動を行い、各ＬＥＤアレ
イＬ１〜Ｌ４０のＬＥＤの数が各６４個なので、必要な
基板配線の本数は６４本である。実施例ではこれを基板
配線３４，３６にそれぞれ３２本ずつ分割し、各基板配
線３４，３６では信号線が中間で向きを変えて１回折り
返すので、個々の基板配線３４，３６当たりのパッド１
２の数は、３２×２の６４個となる。ガラスエポキシ基
板等の硬質プリント基板２を用い、厚さ１２〜１５μｍ
の銅箔に、厚さ１５〜１８μｍの銅メッキ膜を積層し、
エッチングで個別配線４を設けると、線幅が５０μｍ，
配線間のギャップが５０μｍで配線できる。このため基
板配線３４，３６の最小長さは６.４ｍｍとなり、個々
のＬＥＤアレイＬ１〜Ｌ４０の長さが５.４ｍｍで、ア
レイ２個で１０.８ｍｍとなるため、６.４ｍｍ長の基板
配線３４，３６を収容できる。このように、硬質プリン
ト基板２を用い、銅箔と銅メッキ膜とのエッチングで、
基板配線３４，３６を実現できる。The operation of the LED arrays L1 to L40 will be described.
Since time division driving is performed in LED array units and the number of LEDs in each LED array L1 to L40 is 64, the number of required board wirings is 64. In the embodiment, this is divided into 32 board wirings 34 and 36, and the signal lines in the board wirings 34 and 36 change their direction in the middle and return once. Therefore, the pad 1 per board wiring 34 or 36 is divided.
The number of 2 is 32 × 2 = 64. Using a hard printed circuit board 2 such as a glass epoxy board, a thickness of 12 to 15 μm
On the copper foil of 15 to 18 μm in thickness,
When the individual wiring 4 is provided by etching, the line width is 50 μm,
Wiring can be performed with a gap between wirings of 50 μm. Therefore, the minimum length of the board wirings 34 and 36 is 6.4 mm, the length of each LED array L1 to L40 is 5.4 mm, and the two arrays are 10.8 mm. Therefore, the board having a length of 6.4 mm is used. The wires 34 and 36 can be accommodated. In this way, by using the hard printed circuit board 2 and etching the copper foil and the copper plating film,
The board wirings 34 and 36 can be realized.

【００２４】スルーホール２６には１個当たり０.５ｍ
ｍの配線幅を必要とし、３２個を直線状に並べると１６
ｍｍが必要となる。そこで実施例では４列にしかも斜め
に配列する。１列当たりのスルーホールの数を８個と
し、４５度傾けて配列すると、配線幅は０.５×８÷１.
４１４の２.８ｍｍとなる。これ以外にスルーホールを
設けない２４本の配線幅２.４ｍｍがあり、１列当たり
合計５.２ｍｍで配線できる。ＬＥＤアレイＬ１〜Ｌ４
０の各々の長さは５.４ｍｍで、その１個当たり５.２ｍ
ｍのスルーホール列５０，５２等を２列に設けるので、
スルーホール２６を用いても無理なく配線できる。Each through hole 26 is 0.5 m
A wiring width of m is required, and if 32 pieces are arranged in a straight line, 16
mm is required. Therefore, in the embodiment, they are arranged in four rows and diagonally. If the number of through holes per row is 8 and they are arranged at an angle of 45 degrees, the wiring width is 0.5 × 8 ÷ 1.
It becomes 2.8 mm of 414. Besides this, there are 24 wiring widths of 2.4 mm without through holes, and a total of 5.2 mm can be wired per row. LED arrays L1 to L4
The length of each 0 is 5.4 mm, and each one is 5.2 m.
Since m through hole rows 50, 52, etc. are provided in two rows,
Even if the through hole 26 is used, the wiring can be performed without difficulty.

【００２５】基板配線３４，３６は、ＬＥＤアレイＬ１
〜Ｌ４０の付近にパッド列３８を設けている。このため
ボンディング距離が短くワイヤボンディングが容易にな
り、しかもアレイ１個当たり６４本のボンディングワイ
ヤの内で３２本が図の上側へ、３２本が図の下側へ向き
短絡の可能性も低い。また基板配線３６をＬＥＤアレイ
２個毎に分離したので、その間の隙間から共通電極端子
６０へ接続することができる。The board wirings 34 and 36 are connected to the LED array L1.
A pad row 38 is provided near to L40. For this reason, the bonding distance is short and wire bonding is facilitated. Further, out of 64 bonding wires per array, 32 wires are directed to the upper side of the drawing, 32 wires are directed to the lower side of the drawing, and the possibility of short circuit is low. Further, since the substrate wiring 36 is separated for every two LED arrays, it is possible to connect to the common electrode terminal 60 through the gap between them.

【００２６】[0026]

【発明の効果】この発明では以下の効果が得られる。 1) プリント基板を用いた画像装置において、画像装置
に必要な基板配線の密度が得られ、しかもワイヤボンデ
ィング性能が良好で、ボンディング時の圧力や剪断応
力，引っ張り力，振動等によるボンディングパッドの損
傷が無い画像装置を提供する（請求項１〜６）。 2) ボンディングパッドの変形で、ワイヤボンディング
時の圧力や種々の応力，引っ張り力，振動を吸収し、パ
ッドの損傷を防止する（請求項２，５）。 3) 銅メッキ膜でパッドを肉厚にし、ボンディング時の
変形を容易にするとともに、金メッキ膜でボンディング
を容易にし、かつ銅メッキ膜の酸化等を防止する（請求
項３）。 5) 樹脂膜で両側からパッドを基板に固定し、ボンディ
ング時の圧力や剪断応力，引っ張り力，振動等へのボン
ディングパッドの耐久性をさらに向上させる（請求項
４）。 6) ボンディングパッドの形成と基板の両面配線のため
のスルーホールとを、同じプロセスで形成する（請求項
６）。 7) 基板配線の密度を１／２に低下させ、かつ画像アレ
イの共通電極を基板配線と分離して取り出すことを可能
にし、プリント基板で画像装置の基板を構成する（請求
項６）。According to the present invention, the following effects can be obtained. 1) In an image device using a printed circuit board, the density of the board wiring required for the image device can be obtained, the wire bonding performance is good, and the bonding pad is damaged due to pressure, shear stress, tensile force, vibration, etc. at the time of bonding. There is provided an image device which does not have the above (claims 1 to 6). 2) Deformation of the bonding pad absorbs pressure, various stresses, tensile forces and vibrations during wire bonding to prevent damage to the pad (claims 2 and 5). 3) The pad is made thick with a copper plating film to facilitate deformation during bonding, the gold plating film facilitates bonding, and oxidation of the copper plating film is prevented (claim 3). 5) The pads are fixed to the substrate from both sides with a resin film to further improve the durability of the bonding pad against pressure, shear stress, tensile force, vibration, etc. during bonding (claim 4). 6) The formation of the bonding pad and the through hole for double-sided wiring of the substrate are formed in the same process (claim 6). 7) The density of the board wiring is reduced to 1/2, and the common electrode of the image array can be taken out separately from the board wiring, and the board of the image device is constituted by the printed board (claim 6).

【図面の簡単な説明】[Brief description of drawings]

【図１】 実施例の画像装置でのボンディングパッ
ドの断面図FIG. 1 is a sectional view of a bonding pad in an image device according to an embodiment.

【図２】 実施例の画像装置でのボンディングパッ
ドの平面図FIG. 2 is a plan view of a bonding pad in the image device of the embodiment.

【図３】 実施例でのワイヤボンディング時の力の
吸収を示す断面図FIG. 3 is a cross-sectional view showing absorption of force during wire bonding in an example.

【図４】 第２の実施例でのボンディングパッドの
側面図FIG. 4 is a side view of a bonding pad according to a second embodiment.

【図５】 第３の実施例でのボンディングパッドの
断面図FIG. 5 is a sectional view of a bonding pad according to a third embodiment.

【図６】 第３の実施例のボンディングパッドの平
面図FIG. 6 is a plan view of a bonding pad according to a third embodiment.

【図７】 第１の実施例でのボンディングパッドの
製造工程を示す工程図FIG. 7 is a process diagram showing a manufacturing process of a bonding pad in the first embodiment.

【図８】 実施例の画像装置に用いる基板の要部平
面図FIG. 8 is a plan view of a main part of a substrate used for the image device of the embodiment.

【図９】 実施例で用いた基板の第２の主面の要部
平面図FIG. 9 is a plan view of an essential part of a second main surface of a substrate used in an example.

【図１０】 従来例のボンディングパッドの平面図FIG. 10 is a plan view of a conventional bonding pad.

【図１１】 従来例でのボンディングパッドの切断を
示す断面図FIG. 11 is a cross-sectional view showing cutting of a bonding pad in a conventional example.

【図１２】 従来例での、両側へのワイヤボンディン
グとパッドの切断とを示す断面図FIG. 12 is a cross-sectional view showing wire bonding and pad cutting on both sides in a conventional example.

【符号の説明】[Explanation of symbols]

２ 硬質プリント基板 ４ 個別配線 ６ 幅広部 ８ 樹脂膜 １０ 金線 １２，１８ ボンディングパッド １４ 銅メッキ膜 １６ 金メッキ膜 ２０ 金ボール ２２ 樹脂膜 ２６ スルーホール ２８ 無電界メッキ膜 ３０ 銅メッキ膜 ３２ 金メッキ膜 ３４ 第１の基板配線 ３６ 第２の基板配線 Ｌ１〜Ｌ４０ ＬＥＤアレイ ３８ ボンディングパッド列 ４０ 基板配線引き出し部 ４２ 駆動ＩＣ ４６，４８ スルーホール列 ５０，５２ スルーホール列 ５４，５６ 裏面配線 ６０ 共通電極端子 2 hard printed circuit board 4 individual wiring 6 wide part 8 resin film 10 gold wire 12,18 bonding pad 14 copper plating film 16 gold plating film 20 gold ball 22 resin film 26 through hole 28 electroless plating film 30 copper plating film 32 gold plating film 34 First board wiring 36 Second board wiring L1 to L40 LED array 38 Bonding pad row 40 Board wiring lead-out section 42 Driving IC 46, 48 Through hole row 50, 52 Through hole row 54, 56 Backside wiring 60 Common electrode terminal

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 画像アレイをプリント基板の主面上に配
置して、その個々の画像素子を、基板配線のボンディン
グパッドにワイヤボンディングした画像装置において、 前記ボンディングパッドを、銅箔と銅箔上に積層した銅
メッキ膜とで構成したことを特徴とする、画像装置。1. An image device in which an image array is arranged on a main surface of a printed circuit board and individual image elements of the image array are wire-bonded to bonding pads of board wiring, wherein the bonding pads are formed on a copper foil and a copper foil. An image device, comprising: a copper-plated film laminated on. 【請求項２】 前記ボンディングパッドの断面形状を不
均一にし、底面で断面積が大きく、表面で断面積が小さ
な形状としたことを特徴とする、請求項１の画像装置。2. The image device according to claim 1, wherein the bonding pad has a non-uniform cross-sectional shape, and has a large cross-sectional area on the bottom surface and a small cross-sectional area on the surface. 【請求項３】 前記銅箔を厚さ１２〜１５μｍ、前記銅
メッキ膜を厚さ１５〜１８μｍとし、銅メッキ膜上に金
メッキ膜を積層したことを特徴とする、請求項１または
２の画像装置。3. The image according to claim 1, wherein the copper foil has a thickness of 12 to 15 μm, the copper plating film has a thickness of 15 to 18 μm, and a gold plating film is laminated on the copper plating film. apparatus. 【請求項４】 ボンディングパッドは基板配線の他の部
分よりも幅が広く、かつ該幅広部の両端とその周囲の基
板とを樹脂膜で被覆したことを特徴とする、請求項１の
画像装置。4. The image device according to claim 1, wherein the bonding pad has a width wider than other portions of the board wiring, and both ends of the wide portion and the substrate around it are covered with a resin film. . 【請求項５】 画像アレイをプリント基板の主面上に配
置して、その個々の画像素子を基板配線のボンディング
パッドにワイヤボンディングした画像装置において、 ボンディングパッドを、基板配線上に金属ボールを固着
して構成したことを特徴とする画像装置。5. An image device in which an image array is arranged on a main surface of a printed circuit board and individual image elements of the image array are wire-bonded to bonding pads of a board wiring, and the bonding pad and the metal ball are fixed on the board wiring. An image device having the above-mentioned configuration. 【請求項６】 多数の画像アレイを基板の第１の主面上
に列状に配置するとともに、多数の個別配線からなる基
板配線を前記主面上に設け、各画像アレイの個々の画像
素子を基板配線のボンディングパッドにワイヤボンディ
ングした画像装置において、 前記基板配線を、画像アレイの列の一方の側に設けた第
１の基板配線と、他方の側に設けた第２の基板配線とで
構成し、 これらの基板配線の少なくとも一方を画像アレイ２個毎
に分断して、銅メッキ膜で内面を被覆したスルーホール
と基板の第２の主面に設けた他の基板配線とを介して、
相互に接続し、 第１の主面に設けた基板配線に銅メッキ膜を積層して、
前記ボンディングパッドを構成した、 ことを特徴とする画像装置。6. A plurality of image arrays are arranged in a row on a first main surface of a substrate, and substrate wirings made up of a large number of individual wirings are provided on the main surface, and individual image elements of each image array are provided. In the image device in which the board wiring is wire-bonded to the bonding pad of the board wiring, the board wiring includes a first board wiring provided on one side of the column of the image array and a second board wiring provided on the other side. At least one of these substrate wirings is divided into two image arrays, and the through hole having the inner surface coated with a copper plating film and the other substrate wiring provided on the second main surface of the substrate are interposed. ,
Connected to each other, laminating a copper plating film on the board wiring provided on the first main surface,
An image device comprising the bonding pad.
JP29446793A 1993-10-28 1993-10-28 Image device Pending JPH07131075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29446793A JPH07131075A (en) 1993-10-28 1993-10-28 Image device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29446793A JPH07131075A (en) 1993-10-28 1993-10-28 Image device

Publications (1)

Publication Number Publication Date
JPH07131075A true JPH07131075A (en) 1995-05-19

Family

ID=17808159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29446793A Pending JPH07131075A (en) 1993-10-28 1993-10-28 Image device

Country Status (1)

Country Link
JP (1) JPH07131075A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007335782A (en) * 2006-06-19 2007-12-27 Fuji Electric Fa Components & Systems Co Ltd Semiconductor device module and manufacturing method thereof
JP2009506558A (en) * 2005-08-30 2009-02-12 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Method of manufacturing semiconductor device having planar contact forming portion and semiconductor device
WO2009063721A1 (en) 2007-11-16 2009-05-22 Toyota Jidosha Kabushiki Kaisha Semiconductor device
WO2009087561A1 (en) * 2008-01-09 2009-07-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP2015057826A (en) * 2013-09-16 2015-03-26 エルジー イノテック カンパニー リミテッド Light emitting device package

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009506558A (en) * 2005-08-30 2009-02-12 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング Method of manufacturing semiconductor device having planar contact forming portion and semiconductor device
JP2007335782A (en) * 2006-06-19 2007-12-27 Fuji Electric Fa Components & Systems Co Ltd Semiconductor device module and manufacturing method thereof
WO2009063721A1 (en) 2007-11-16 2009-05-22 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US8674511B2 (en) 2007-11-16 2014-03-18 Toyota Jidosha Kabushiki Kaisha Method of forming a semiconductor device with a contact pad on a sloped silicon dioxide surface
WO2009087561A1 (en) * 2008-01-09 2009-07-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device
US8169087B2 (en) 2008-01-09 2012-05-01 Toyota Jidosha Kabushiki Kaisha Semiconductor device
JP2015057826A (en) * 2013-09-16 2015-03-26 エルジー イノテック カンパニー リミテッド Light emitting device package

Similar Documents

Publication Publication Date Title
JP3579903B2 (en) Semiconductor element mounting structure, semiconductor device mounting structure, and liquid crystal display device
US6756663B2 (en) Semiconductor device including wiring board with three dimensional wiring pattern
JP4362996B2 (en) Piezoelectric / electrostrictive actuator having lattice arrangement and manufacturing method thereof
JP2004343030A (en) Wiring circuit board, manufacturing method thereof, circuit module provided with this wiring circuit board
JPH10200027A (en) Wiring member and lead frame comprising the same
JPH07131075A (en) Image device
US6465876B1 (en) Semiconductor device and lead frame therefor
JP3490303B2 (en) Semiconductor device package
JPH0547842A (en) Semiconductor device
US5877549A (en) UFBGA package equipped with interface assembly including a photosoluble layer
US6181000B1 (en) Lead frame for ball grid array, semiconductor device having it, and process for producing it
JPH02196476A (en) Led print head
JP2001024235A (en) Display device
EP0171783A2 (en) Module board and module using the same and method of treating them
JPH06278313A (en) Image device
JPH0547836A (en) Mounting structure of semiconductor device
JPH06166210A (en) Optical print head mounting structure
JPS6226317B2 (en)
JPH09270535A (en) Semiconductor element and linear light source using it
JPH08129344A (en) Image device
JP2918087B2 (en) Multilayer wiring board for mounting semiconductor chips
JP3987288B2 (en) Semiconductor element mounting structure and liquid crystal display device
JP3543870B2 (en) Imaging device
JP2003234427A (en) Wiring board, semiconductor device using the same and manufacturing method thereof
JP2766361B2 (en) Semiconductor device