JPH07118929B2 - Sync detector - Google Patents
Sync detectorInfo
- Publication number
- JPH07118929B2 JPH07118929B2 JP59126001A JP12600184A JPH07118929B2 JP H07118929 B2 JPH07118929 B2 JP H07118929B2 JP 59126001 A JP59126001 A JP 59126001A JP 12600184 A JP12600184 A JP 12600184A JP H07118929 B2 JPH07118929 B2 JP H07118929B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- input
- output
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P7/00—Arrangements for regulating or controlling the speed or torque of electric DC motors
- H02P7/06—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current
- H02P7/18—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power
- H02P7/24—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices
- H02P7/28—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices
- H02P7/2805—Arrangements for regulating or controlling the speed or torque of electric DC motors for regulating or controlling an individual dc dynamo-electric motor by varying field or armature current by master control with auxiliary power using discharge tubes or semiconductor devices using semiconductor devices whereby the speed is regulated by measuring the motor speed and comparing it with a given physical value
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Electric Motors In General (AREA)
- Control Of Direct Current Motors (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はDCモータの速度位相制御における同期検出回路
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection circuit in speed phase control of a DC motor.
従来例の構成とその問題点 近年、VTRあるいはビデオディスクの開発が盛んに行な
われ、それらの回転部分にDCモータが多く使用されるよ
うになってきており、それらのモータは速度位相制御に
よって回転精度が良好なものとなっている。またこれら
のシステムの動作は制御系と連動させて行なうことが多
く、その際、モータの基準信号に対する同期を検出する
ことが、システムコントロール系のシーケンスにおい
て、重要な役割を果すことが多く、モータの制御部分に
は、同期検出回路が付加されている。Conventional configuration and its problems In recent years, VTRs or video discs have been actively developed, and DC motors are often used for their rotating parts.These motors are rotated by speed phase control. The accuracy is good. In addition, the operation of these systems is often performed in conjunction with the control system. At that time, detection of synchronization with the reference signal of the motor often plays an important role in the sequence of the system control system. A synchronization detection circuit is added to the control part of the.
以下、同図を参照しながら従来の同期検出回路について
説明を行なう。The conventional sync detection circuit will be described below with reference to FIG.
第１図は従来の同期検出回路の構成を示すものである。
第１図において、１は位相比較器であり、その入力信号
Ａは基準信号であり、Ｂはモータの回転数が周波数に変
換された被比較信号で、出力信号Ｃが位相誤差信号であ
る。また２はモノマルチてあり、被比較信号Ｂが入力さ
れていてその出力信号Ｄはシリアル−パラレル変換器と
してのＮビットシフトレジスタ３のクロック入力端子に
入力されている。一方基準信号ＡはＮビットシフトレジ
スタ３のデータ入力端子に入力されていて、シフトレジ
スタのＮビットの出力がANDゲート４のそれぞれの入力
に入力されており、ANDゲート４の出力信号Ｅが同期検
出信号となる。FIG. 1 shows the configuration of a conventional synchronization detection circuit.
In FIG. 1, reference numeral 1 denotes a phase comparator, an input signal A thereof is a reference signal, B is a compared signal obtained by converting the number of rotations of a motor into a frequency, and an output signal C thereof is a phase error signal. Further, 2 is a mono-multi, and the compared signal B is inputted, and its output signal D is inputted to the clock input terminal of the N-bit shift register 3 as a serial-parallel converter. On the other hand, the reference signal A is input to the data input terminal of the N-bit shift register 3, the N-bit output of the shift register is input to each input of the AND gate 4, and the output signal E of the AND gate 4 is synchronized. It becomes a detection signal.
第２図は第１図のA,B,Dの信号のタイミングの関係を示
すもので、被比較信号Ｂが基準信号Ａに同期した時のタ
イミングの関係を示している。t1は１周期の時間であ
り、t2はＡ及びＢのHigh区間の時間である。FIG. 2 shows the timing relationship between the signals A, B and D in FIG. 1, and shows the timing relationship when the compared signal B is synchronized with the reference signal A. t 1 is the time of one cycle, and t 2 is the time of the high section of A and B.
第２図Ｄは第１図に示すモノマルチ２によって被比較信
号Ｂ（モータの回転数を周波数に変換した信号）をパル
ス幅（t4）に変換し、さらにその立ち上りまでの時間を
信号Ｂの立ち上りに対して、t3だけシフトし、信号Ａの
“High"区間の中央付近にその立ち上りがくるようにし
た信号であり、信号Ａの“High"区間がデータとして安
定にシフトレジスタ３に入力されるためのものである。
従って第２図に示す信号（A,B,D）の関係がＮ回連続し
た時、即第１図に示すシフトレジスタ３のデータ入力と
クロック入力に信号Ａと信号Ｄがそれぞれ入力された
時、第１図に示すシフトレジスタ３の出力がすべて“Hi
gh"となりANDゲート４の出力信号も“High"となってモ
ータが基準信号に対して同期したとみなすようになって
いる。FIG. 2D shows that the compared signal B (a signal obtained by converting the number of rotations of the motor into a frequency) is converted into a pulse width (t 4 ) by the monomulti 2 shown in FIG. Is a signal that is shifted by t 3 with respect to the rising edge of the signal A so that the rising edge comes near the center of the “High” section of the signal A, and the “High” section of the signal A is stably stored in the shift register 3 as data. It is for input.
Therefore, when the relationship of the signals (A, B, D) shown in FIG. 2 continues N times, immediately when the signal A and the signal D are input to the data input and clock input of the shift register 3 shown in FIG. 1, respectively. , The output of the shift register 3 shown in FIG.
gh "and the output signal of the AND gate 4 also becomes" High ", and the motor is considered to be synchronized with the reference signal.
しかしながら、同一のシステムに対してモータの回転速
度を速くした時、第２図における信号Ａ及びＢに対する
信号Ｄの位置関係が異なる。回転速度が速くなった時の
信号A,B,Dの位置関係を第３図に示す。However, when the rotational speed of the motor is increased for the same system, the positional relationship of the signal D with respect to the signals A and B in FIG. 2 is different. FIG. 3 shows the positional relationship of the signals A, B, D when the rotation speed becomes faster.
第３図ではモータの回転速度が速くなっているため、第
２図t1及びt2に相当する時間t1′及びt2′が短くなって
いるが、モノマルチ２によって決定されるt3及びt4は変
わらない。従って、A,B,Dの信号の位置関係は第３図に
示すごとく、Ｄの信号の立ち上りがＡの信号の“High"
区間から“Low"区間に逸脱してしまう可能性が生じる。
このような場合においては、第１図に示す構成では、AN
Dゲート４の出力が“Low"となり正しく同期しているに
もかかわらず、同期していないと見なされる問題点を生
じる。In FIG. 3, since the rotation speed of the motor is high, the times t 1 ′ and t 2 ′ corresponding to t 1 and t 2 in FIG. 2 are short, but t 3 determined by the monomulti 2 is 3 And t 4 remain unchanged. Therefore, the positional relationship among the A, B, and D signals is as shown in FIG. 3, when the rising edge of the D signal is "High" for the A signal.
There is a possibility of deviating from the section to the "Low" section.
In such a case, in the configuration shown in FIG.
Although the output of the D gate 4 becomes “Low” and the synchronization is correct, there is a problem that the output is regarded as not synchronized.
発明の目的 本発明はこうした問題を解消する目的でなされたもので
モータの回転速度に関係なく、この基準信号に同期した
ことを正しく検出する手段を提供するものである。SUMMARY OF THE INVENTION The present invention has been made for the purpose of solving such a problem and provides a means for correctly detecting synchronization with the reference signal regardless of the rotation speed of the motor.
発明の構成 本発明の同期検出装置は、基準信号をシリアルーパラレ
ル変換器のデータ入力に入力し、前記基準信号と同期し
た信号を入力信号とするノコギリ波発生回路とピークホ
ールド回路から成る電圧変換回路の出力分圧信号と、前
記ノコギリ波発生回路の出力信号を比較するためのコン
パレータと、前記コンパレータの出力信号の立ち上りも
しくは立ち下りのエッジの一方を検出し、かつパルス化
するためのエッジ検出回路を有し、前記エッジ検出回路
の出力信号を前記シリアルーパラレル変換器のクロック
とし、そのパラレル出力信号の論理積が同期検出信号と
なるように構成したものである。Configuration of the Invention The synchronization detection device of the present invention is a voltage conversion circuit comprising a sawtooth wave generation circuit and a peak hold circuit, which inputs a reference signal to a data input of a serial-parallel converter and uses a signal synchronized with the reference signal as an input signal. An output voltage division signal of the circuit, a comparator for comparing the output signal of the sawtooth wave generation circuit, and one of the rising edge or the falling edge of the output signal of the comparator, and edge detection for pulsing A circuit is provided, and the output signal of the edge detection circuit is used as the clock of the serial-parallel converter, and the logical product of the parallel output signals becomes the synchronization detection signal.
実施例の説明 以下本発明の一実施例について説明する。第４図は本発
明の一実施例における構成図を示したものである。第４
図において、５はモータの基準信号Ｆとモータの回転数
が周波数に変換された被比較信号Ｇを位相比較するため
の位相比較器で、その出力信号Ｍが位相誤差信号であ
る。６は矩形信号の“High"区間のみ一定の傾斜で電圧
が上昇し、“Low"区間ではリセットされる動作を行なう
ノコギリ波発生回路であり、信号Ｇ（モータの回転数が
周波数に変換された信号）が入力されている。７はノコ
ギリ波発生回路６の出力ピーク電圧をホールドするピー
クホールド回路であり、その出力電圧Ｉは８に示す分割
回路で1/2に分割され、この分割回路８の出力電圧Ｊは
コンパレータ９の＋入力端子に入力されている。一方コ
ンパレータ９の−入力端子にはノコギリ波発生回路６の
出力信号Ｈが入力されており、その電圧上昇部分の電圧
がＪの電圧（コンパレータ９の＋入力）レベルを越えた
時コンパレータ９の出力信号Ｋは“Low"から“High"に
変化する。さらに10に示すモノマルチはＫの信号の状態
の変化によってトリガされ、一定のパルス幅ｗを持った
信号Ｌを出力する。以上Ｆ〜Ｌまでの信号の関係を第５
図に示す。またＬは11に示すシフトレジスタのクロック
入力端子に入力され、また信号Ｆ（モータの基準信号）
はデータ入力端子に入力されていて、第５図に示すＦと
Ｌの関係を満足した時シフトレジスタの出力はすべて
“High"となるため、ANDゲート12の出力Ｎも“High"と
なって同期検出がなされたことになる。Description of Embodiments One embodiment of the present invention will be described below. FIG. 4 is a block diagram showing an embodiment of the present invention. Fourth
In the figure, reference numeral 5 is a phase comparator for phase-comparing a reference signal F of the motor and a compared signal G whose frequency of rotation of the motor is converted into a frequency, and an output signal M thereof is a phase error signal. Reference numeral 6 denotes a sawtooth wave generating circuit that performs an operation in which the voltage rises at a constant slope only in the "High" section of the rectangular signal and is reset in the "Low" section, and the signal G (the number of rotations of the motor is converted to frequency Signal) is being input. Reference numeral 7 is a peak hold circuit for holding the output peak voltage of the sawtooth wave generation circuit 6, and its output voltage I is divided into ½ by the division circuit shown by 8, and the output voltage J of this division circuit 8 is output from the comparator 9. It is input to the + input terminal. On the other hand, the output signal H of the sawtooth wave generation circuit 6 is input to the-input terminal of the comparator 9, and when the voltage of the voltage rising portion exceeds the voltage level of J (+ input of the comparator 9) level, the output of the comparator 9 The signal K changes from "Low" to "High". Further, the monomulti shown by 10 is triggered by a change in the state of the K signal and outputs a signal L having a constant pulse width w. The signal relationships from F to L above are
Shown in the figure. Also, L is input to the clock input terminal of the shift register shown by 11, and also signal F (motor reference signal)
Is input to the data input terminal, and when the relationship between F and L shown in FIG. 5 is satisfied, the output of the shift register is all "High", so the output N of the AND gate 12 is also "High". This means that synchronization has been detected.
以上のような構成によって、第５図に示すようにＦとＬ
の関係はモータの回転速度に関係なく、ＬがＦの“Hig
h"区間の中央に常に位置するため、前述したようなモー
タの回転速度によって、ＬがＦの“Low"区間に逸脱して
しまう恐れがなく、安定した同期検出が可能となるもの
である。With the above configuration, as shown in FIG.
Irrespective of the rotation speed of the motor, L is “Hig
Since it is always located in the center of the h "section, there is no risk of L deviating to the" Low "section of F due to the rotation speed of the motor as described above, and stable synchronization detection is possible.
発明の効果 以上のように、本発明によれば、モータの回転速度を変
化せしめた場合においても、同期状態にあるか否かが正
確に検出できるものである。EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to accurately detect whether or not the motor is in the synchronous state even when the rotation speed of the motor is changed.
第１図は従来における同期検出装置の構成図、第２図及
び第３図は第１図における各部の信号のタイミングを示
す波形図、第４図は本発明の一実施例における同期検出
装置の構成図、第５図は第４図における各部の信号の波
形及びそれらのタイミングを示した波形図である。 ６……ノコギリ波発生回路、７……ピークホールド回
路、８……電圧分割回路、９……コンパレータ、10……
モノマルチ。FIG. 1 is a block diagram of a conventional synchronization detecting device, FIGS. 2 and 3 are waveform diagrams showing timings of signals of respective parts in FIG. 1, and FIG. 4 is a diagram showing a synchronization detecting device according to an embodiment of the present invention. FIG. 5 is a waveform diagram showing the waveforms of the signals of the respective parts in FIG. 4 and their timings. 6 ... sawtooth wave generation circuit, 7 ... peak hold circuit, 8 ... voltage division circuit, 9 ... comparator, 10 ...
Mono multi.
Claims (1)
ル変換器のデータ入力に入力されていて、他方のパルス
信号の立ち上がりエッジから立ち下がりエッジまでの間
その出力電圧が単調増加するノコギリ波発生回路と適当
な時定数で放電するピークホールド回路から成る周期電
圧変換回路と、前記周期電圧変換回路の出力電圧を分圧
するための分圧回路を有し、前記ノコギリ波発生回路と
前記分圧回路の出力信号が入力信号となるコンパレータ
と、前記コンパレータの出力信号の一方のエッジを検出
し、パルス化するためのエッジ検出回路を有し、前記エ
ッジ検出回路の出力信号が前記シリアルパラレル変換器
のクロック入力に入力され、前記シリアルパラレル変換
器のパラレル出力の論理積が検出信号となることを特徴
とする同期検出装置。1. A sawtooth wave generation circuit in which one of two pulse signals is input to a data input of a serial-parallel converter and the output voltage of which is monotonically increased from the rising edge to the falling edge of the other pulse signal. And a periodic voltage conversion circuit composed of a peak hold circuit that discharges with an appropriate time constant, and a voltage division circuit for dividing the output voltage of the periodic voltage conversion circuit, and the sawtooth wave generation circuit and the voltage division circuit. A comparator having an output signal as an input signal, and an edge detection circuit for detecting one edge of the output signal of the comparator and converting it into a pulse, and the output signal of the edge detection circuit is a clock of the serial-parallel converter. A synchronous detection device characterized in that a logical product of the parallel outputs of the serial-parallel converter inputted to the input becomes a detection signal. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59126001A JPH07118929B2 (en) | 1984-06-19 | 1984-06-19 | Sync detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59126001A JPH07118929B2 (en) | 1984-06-19 | 1984-06-19 | Sync detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS614480A JPS614480A (en) | 1986-01-10 |
| JPH07118929B2 true JPH07118929B2 (en) | 1995-12-18 |
Family
ID=14924266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59126001A Expired - Lifetime JPH07118929B2 (en) | 1984-06-19 | 1984-06-19 | Sync detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118929B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5079377B2 (en) | 2007-04-13 | 2012-11-21 | フェリカネットワークス株式会社 | Information processing system, management information processing apparatus, and program |
-
1984
- 1984-06-19 JP JP59126001A patent/JPH07118929B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS614480A (en) | 1986-01-10 |
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