JPH07118553B2 - Alignment mark for electron beam direct writing and its manufacturing method - Google Patents
Alignment mark for electron beam direct writing and its manufacturing methodInfo
- Publication number
- JPH07118553B2 JPH07118553B2 JP2015732A JP1573290A JPH07118553B2 JP H07118553 B2 JPH07118553 B2 JP H07118553B2 JP 2015732 A JP2015732 A JP 2015732A JP 1573290 A JP1573290 A JP 1573290A JP H07118553 B2 JPH07118553 B2 JP H07118553B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- alignment mark
- electron beam
- direct writing
- beam direct
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Electron Beam Exposure (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、電子ビーム直接描画を集積回路、特に超伝導
集積回路に適用する場合において、集積回路のパターン
の重ね合わせを正確に行なうために使用されるアライメ
ント用マークおよびその作製方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention is intended to accurately perform pattern superposition of integrated circuits when electron beam direct writing is applied to integrated circuits, particularly superconducting integrated circuits. The present invention relates to an alignment mark used and a method for producing the same.
［従来の技術］ 従来、このようなアライメント用マークのための構造と
しては、第３図（ａ）に示すような、基板１上に深い溝
２を設けた構造、および第３図（ｂ）に示すような、基
板１上に金属膜の細線３を配置した構造があった。[Prior Art] Conventionally, as a structure for such an alignment mark, a structure in which a deep groove 2 is provided on a substrate 1 as shown in FIG. 3 (a), and FIG. 3 (b). There is a structure in which the thin wire 3 of the metal film is arranged on the substrate 1 as shown in FIG.
［発明が解決しようとする課題］ しかしながら、上記の従来技術のアライメント用マーク
のための構造では、第３図（ａ）に示したき上に深い溝
を設けた構造の場合は、溝の深さとしては、１μｍ程度
が必要で、その作製は、長時間のエッチングが必要なた
め、容易ではなく、また、基板そのものを加工するた
め、基板に汚れや欠陥が残り易い問題があった。一方、
第３図（ｂ）に示した基板上に金属膜の細線を配置した
構造の場合は、集積回路に用いられる膜とは別にアライ
メントマーク用の金属膜を堆積する必要があるため、工
程数が増加し、作製が複雑になる問題があった。本発明
は、作製が容易で、かつ高いコントラストの二次電子像
が得られるアライメントマークおよびその作製方法を提
供することを目的とする。[Problems to be Solved by the Invention] However, in the above-described structure for the alignment mark of the prior art, in the case of the structure shown in FIG. 3 (a) in which a deep groove is provided, the depth of the groove is increased. As a result, about 1 μm is required, and its fabrication is not easy because it requires etching for a long time, and since the substrate itself is processed, stains and defects are likely to remain on the substrate. on the other hand,
In the case of the structure shown in FIG. 3 (b) in which fine lines of a metal film are arranged on the substrate, it is necessary to deposit a metal film for an alignment mark in addition to the film used for the integrated circuit. There is a problem that the number increases and the fabrication becomes complicated. An object of the present invention is to provide an alignment mark that is easy to manufacture and that can obtain a secondary electron image with high contrast, and a manufacturing method thereof.
［課題を解決するための手段］ 上述した問題点を解決するために、本発明アライメント
マークは絶縁層と、該絶縁層上に形成されたジョセフソ
ン接合のための多層膜からなる導電層と、該導電層中に
設けられ、前記絶縁層に達する溝とからなることを特徴
とする。[Means for Solving the Problems] In order to solve the above-mentioned problems, the alignment mark of the present invention comprises an insulating layer, a conductive layer formed on the insulating layer and comprising a multilayer film for Josephson junction, A groove provided in the conductive layer and reaching the insulating layer.
本発明方法は基板上に絶縁膜を形成する工程と、該絶縁
膜上にジョセフソン接合多層膜を順次形成する工程と、
該多層膜中に前記絶縁膜に達する溝を設ける工程とを有
することを特徴とする。The method of the present invention comprises a step of forming an insulating film on a substrate, a step of sequentially forming a Josephson junction multilayer film on the insulating film,
And a step of providing a groove reaching the insulating film in the multilayer film.
［作用］ 本発明では、基板にアライメント用マークのための構造
を設けるのでなく、第１図に示すように、集積回路の作
製工程において用いられる絶縁膜４と導電膜５からなる
多層膜を利用する。すなわち導電膜５に溝15を設けてア
ライメント用マークのための構造とする。[Operation] In the present invention, a multilayer film made up of the insulating film 4 and the conductive film 5 used in the manufacturing process of the integrated circuit is used as shown in FIG. To do. That is, the groove 15 is provided in the conductive film 5 to form a structure for the alignment mark.
通常、電子ビーム直接描画装置においては、アライメン
ト用マークの位置の検出は、二次電子像を検出すること
によって行なわれる。絶縁膜と導電膜の境界において、
最もコントラストの大きい二次電子像が得られる。従っ
て、本発明の構造は、この条件に適合していることが分
かる。一般に、アライメントマークについて、二次電子
像のコントラストは、露光する層を重ねるに従って低下
する傾向にあるため、最初のコントラストが高いほど、
数多くの層を重ねることが可能となる。Usually, in the electron beam direct writing apparatus, the position of the alignment mark is detected by detecting the secondary electron image. At the boundary between the insulating film and the conductive film,
A secondary electron image with the highest contrast can be obtained. Therefore, it can be seen that the structure of the present invention meets this condition. Generally, with respect to the alignment mark, the contrast of the secondary electron image tends to decrease as the layers to be exposed are stacked, so that the higher the initial contrast,
It is possible to stack many layers.
［実施例］ 第２図に本発明の実施例を示す。[Embodiment] FIG. 2 shows an embodiment of the present invention.
直径5cmのSi基板６上に絶縁膜として厚さ200nmのSiO2膜
７をスパッタ法によって形成した。ついで、スパッタ法
によって、厚さ150nmのNb8,厚さ50nmのNbN膜9,厚さ0.7n
mのMgO膜10,厚さ50nmのNbN膜11,厚さ150nmのNb膜12から
なるジョセフソン接合多層膜13を形成した。さらにCF4
プラズマを用いたリアクティブイオンエッチングによっ
て、ジョセフソン接合多層膜13中に、SiO2膜７に達する
幅３μｍの溝14を形成した。室温において、ジョセフソ
ン接合多層膜中のNbは導電体であり、NbNは半導体なの
で、このジョセフソン接合多層膜は導電膜として機能
し、露出されたSiO2膜との間で高い二次電子像コントラ
ストを示した。このようなアライメント用マークを電子
ビーム直接描画に用いた場合、最大で５層の集積回路パ
ターンを重ね合わせることができた。An SiO 2 film 7 having a thickness of 200 nm was formed as an insulating film on a Si substrate 6 having a diameter of 5 cm by a sputtering method. Then, by sputtering, Nb8 with a thickness of 150 nm, NbN film 9 with a thickness of 50 nm, and a thickness of 0.7 n
A Josephson junction multilayer film 13 composed of an MgO film 10 of m, an NbN film 11 of 50 nm thickness, and an Nb film 12 of 150 nm thickness was formed. CF 4
A groove 14 having a width of 3 μm reaching the SiO 2 film 7 was formed in the Josephson junction multilayer film 13 by reactive ion etching using plasma. At room temperature, Nb in the Josephson junction multilayer film is a conductor and NbN is a semiconductor, so this Josephson junction multilayer film functions as a conductive film, and a high secondary electron image with the exposed SiO 2 film. It showed contrast. When such an alignment mark was used for electron beam direct writing, a maximum of five layers of integrated circuit patterns could be overlaid.
［発明の効果］ 以上説明したように、本発明の構造を用いれば、比較的
短い時間のエッチングですむため、アライメントマーク
の作製が容易である。また、基板そのものを加工しない
ため、集積回路の作製工程中で清浄な基板を保つことが
でき、回路を高い歩留りで製造できる。本発明の構造に
よるアライメントマークを用いて電子ビーム直接描画を
行う場合、コントラストの大きい二次電子像が得られる
ため、良好にマーク検出が行われる。このため、多くの
層の集積回路パターンを重ね合わせることができる。ま
た、ジョセフソン集積回路においては、本発明の構造を
形成するために、別途、特別の膜を堆積することなく、
ジョセフソン集積回路に用いられている導電膜及び絶縁
膜を用いることによって、本発明の構造を形成できるた
め、従来法に比べて極めて、簡便な方法である。[Effects of the Invention] As described above, when the structure of the present invention is used, etching can be performed in a relatively short time, and thus alignment marks can be easily manufactured. In addition, since the substrate itself is not processed, a clean substrate can be kept during the manufacturing process of the integrated circuit, and the circuit can be manufactured with a high yield. When the electron beam direct writing is performed using the alignment mark having the structure of the present invention, a secondary electron image with a large contrast is obtained, so that the mark can be detected well. Therefore, integrated circuit patterns of many layers can be overlapped. In addition, in the Josephson integrated circuit, in order to form the structure of the present invention, without specially depositing a special film,
Since the structure of the present invention can be formed by using the conductive film and the insulating film used in the Josephson integrated circuit, the method is extremely simpler than the conventional method.
第１図は本発明を説明する模式図、 第２図は本発明実施例の断面図、 第３図はアライメントマークの断面図である。 １…基板、２…溝、３…金属細線、４…絶縁膜、５…導
電膜、ｂ…Si基板、７…SiO2膜、8,12…Nb膜、9,11…Nb
N膜、10…MgO膜、13…ジョセフソン接合多層膜、14…
溝、15…溝。FIG. 1 is a schematic diagram for explaining the present invention, FIG. 2 is a sectional view of an embodiment of the present invention, and FIG. 3 is a sectional view of an alignment mark. 1 ... Substrate, 2 ... Groove, 3 ... Metal fine wire, 4 ... Insulating film, 5 ... Conductive film, b ... Si substrate, 7 ... SiO 2 film, 8, 12 ... Nb film, 9, 11 ... Nb
N film, 10 ... MgO film, 13 ... Josephson junction multilayer film, 14 ...
Groove, 15 ... Groove.
Claims (2)
フソン接合のための多層膜からなる導電層と、該導電層
中に設けられ、前記絶縁層に達する溝とからなることを
特徴とする電子ビーム直接描画用アライメントマーク。1. An insulating layer, a conductive layer made of a multilayer film for Josephson junction formed on the insulating layer, and a groove provided in the conductive layer and reaching the insulating layer. A featured alignment mark for direct electron beam writing.
膜上にジョセフソン接合多層膜を順次形成する工程と、
該多層膜中に前記絶縁層に達する溝を設ける工程とを有
することを特徴とする電子ビーム直接描画用アライメン
トマークの作製方法。2. A step of forming an insulating film on a substrate, and a step of sequentially forming a Josephson junction multilayer film on the insulating film,
And a step of providing a groove reaching the insulating layer in the multilayer film, the method for producing an alignment mark for electron beam direct writing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015732A JPH07118553B2 (en) | 1990-01-25 | 1990-01-25 | Alignment mark for electron beam direct writing and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2015732A JPH07118553B2 (en) | 1990-01-25 | 1990-01-25 | Alignment mark for electron beam direct writing and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03220784A JPH03220784A (en) | 1991-09-27 |
| JPH07118553B2 true JPH07118553B2 (en) | 1995-12-18 |
Family
ID=11896942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2015732A Expired - Lifetime JPH07118553B2 (en) | 1990-01-25 | 1990-01-25 | Alignment mark for electron beam direct writing and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118553B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2507906B2 (en) * | 1991-10-09 | 1996-06-19 | 工業技術院長 | Substrate alignment marker for Josephson integrated circuit substrate and its fabrication method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63308318A (en) * | 1987-06-10 | 1988-12-15 | Matsushita Electric Ind Co Ltd | Forming method for alignment mark |
-
1990
- 1990-01-25 JP JP2015732A patent/JPH07118553B2/en not_active Expired - Lifetime
Non-Patent Citations (2)
| Title |
|---|
| Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．４６〔１１〕（１９８５）Ｐ．１０９８−１１００ |
| 電子通信学会誌６６〔７〕（１９８３）Ｐ．７０１−７０４ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03220784A (en) | 1991-09-27 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |