JPH07118518B2 - Semiconductor memory - Google Patents
Semiconductor memoryInfo
- Publication number
- JPH07118518B2 JPH07118518B2 JP22212285A JP22212285A JPH07118518B2 JP H07118518 B2 JPH07118518 B2 JP H07118518B2 JP 22212285 A JP22212285 A JP 22212285A JP 22212285 A JP22212285 A JP 22212285A JP H07118518 B2 JPH07118518 B2 JP H07118518B2
- Authority
- JP
- Japan
- Prior art keywords
- signal line
- intersection
- parallel
- signal
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体メモリに関し、特に少なくとも一つの書
込み信号線対又は読出し信号線対を備えた半導体メモリ
に関する。The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory having at least one write signal line pair or read signal line pair.
第２図は従来の半導体メモリの一例を示すブロック図で
ある。FIG. 2 is a block diagram showing an example of a conventional semiconductor memory.
D1,D2,D3,D4;1,2,3,４はディジット線、Ｉは書
込み信号線を駆動する駆動回路、M1,M2,……,M12はそれ
ぞれ１ビット分のメモリセル、Ｏは読出し信号を出力す
る出力増幅器、RD,▲▼は読出し信号線対、S1,S2,S
3,S4は接線用回路、W1W2,W3はワード線、WR,▲▼は
書込み信号線対、Ｘは行デコーダ、Ｙは列デコーダ、
Y1,Y2,Y3,Y4は出力線である。D 1 , D 2 , D 3 , D 4 ; 1 , 1 , 2 , 3 and 4 are digit lines, I is a drive circuit for driving a write signal line, and M 1 , M 2 , ..., M 12 are 1 bit each. , O is an output amplifier that outputs a read signal, RD, ▲ ▼ are read signal line pairs, S 1 , S 2 , S
3 , S 4 are tangential circuits, W 1 W 2 , W 3 are word lines, WR, ▲ ▼ are write signal line pairs, X is a row decoder, Y is a column decoder,
Y 1 , Y 2 , Y 3 and Y 4 are output lines.
第３図は従来のメモリセルの一例の回路図で、抵抗負荷
型のスタティック型メモリセルを示す。FIG. 3 is a circuit diagram of an example of a conventional memory cell, showing a resistance load type static memory cell.
第４図は従来の接続用回路の一例の回路図で、書込み信
号WR,▲▼あるいは読出し信号線RD,▲▼とディ
ジット線D,とを接続する回路を示す。FIG. 4 is a circuit diagram of an example of a conventional connection circuit, showing a circuit for connecting the write signal WR, ▲ ▼ or the read signal line RD, ▲ ▼ to the digit line D.
これらの図を用いて従来例を説明する。A conventional example will be described with reference to these drawings.
メモリセルM1の内容を読出す場合には、行デコーダＸに
よりワード線W1が選択されると、ワード線W1に接続され
ている各メモリセルの内容がそれぞれのディジット線
,Dに微小電位変化として現われ（第３図のQ3,Q4が導
通している。）、列デコーダＹが動作して出力線Y1が高
電位となり、第４図のQ5が導通しディジット線D1,１
間の電位差が読出し信号線RD,▲▼にそれぞれ出力
され、差動増幅する出力増幅器Ｏが動作して、書込み信
号WRと▲▼は同一電位であるから読出し信号線RDと
▲▼のみの電位差を増幅し出力する。また、メモリ
セルM1に内容を書込む場合には、駆動回路Ｉを動作さ
せ、書込み信号線WRと▲▼との間に電位差が生じ、
後は読出し時と同じに、まずワード線W1が選択され、出
力線Y1が高電位となり、第４図のQ6,Q7が導通し、ディ
ジット線D1,１と書込み信号線WR,▲▼が接続し
て、書込み信号の電位産がディジット線D1,１を通し
てメモリセルM1に入力され、その内容が保持される。こ
の時、読出し信号線RDと▲▼との間に電位差が生じ
るが、出力増幅器Ｏは動作していないので他に影響はな
い。When the content of the memory cell M 1 is read, when the word line W 1 is selected by the row decoder X, the content of each memory cell connected to the word line W 1 is changed to the corresponding digit line.
, D appear as minute potential changes (Q 3 and Q 4 in FIG. 3 are conducting), the column decoder Y operates and the output line Y 1 becomes high potential, and Q 5 in FIG. 4 is conducting. Digit line D 1 , 1
The potential difference between the read signal lines RD and ▲ ▼ is output, the output amplifier O for differential amplification operates, and the write signals WR and ▲ ▼ have the same potential, so the potential difference between the read signal lines RD and ▲ ▼ only. Is amplified and output. When writing the contents to the memory cell M 1 , the drive circuit I is operated and a potential difference is generated between the write signal line WR and ▲ ▼.
After that, as in the case of reading, first, the word line W 1 is selected, the output line Y 1 becomes high potential, Q 6 and Q 7 in FIG. 4 become conductive, and the digit lines D 1 and 1 and the write signal line WR. , ▲ ▼ are connected, and the potential output of the write signal is input to the memory cell M 1 through the digit lines D 1 , 1 , and the content is held. At this time, a potential difference occurs between the read signal line RD and {circle around ()}, but since the output amplifier O is not operating, there is no other influence.
メモリの大容量化に伴いパターンの微細化が進むと、金
属配線用の幅や間隔に対して厚さが無視できなくなり、
隣接配線間の結合容量が増大する。例えば、256kビット
メモリでは配線の幅および間隔は１〜３μｍ、厚さ0.5
〜１μｍで、隣接配線間の容量は全配線容量の10〜40％
にもなる。このような微細パターンでは、第２図の回路
内の出力バスの平行な一対の読出し信号線RD,▲▼
のそれぞれと周辺の配線との間の各結合容量が異なるの
で、これら周辺の配線の電位が出力増幅器Ｏの動作完了
前に変化すると、読出し信号線RDと▲▼とに大きさ
の異なる雑音が生じてしまう。また、入力バスの平行な
一対の書込み信号線WR,▲▼についてもそれぞれと
周辺の配線との間の各結合容量が異なるので、これら周
辺の配線の電位がメモリセルＭに内容が保持される前に
変化すると、書込み信号線WRと▲▼にも大きさの異
なる雑音が生じてしまう。この雑音発生源としては、入
出力バスに近いワード線、列デコーダ駆動用の信号線あ
るいは入出力バス内の他の信号線などがある。As the miniaturization of patterns progresses with the increase in memory capacity, the thickness cannot be ignored with respect to the width and spacing for metal wiring.
The coupling capacitance between adjacent wirings increases. For example, in a 256 kbit memory, the wiring width and spacing are 1-3 μm and the thickness is 0.5
~ 1μm, the capacitance between adjacent wiring is 10-40% of the total wiring capacity
It also becomes. In such a fine pattern, a pair of parallel read signal lines RD, ▲ ▼ of the output bus in the circuit of FIG.
Since the respective coupling capacitances between the respective wirings and the peripheral wirings are different, if the potentials of these peripheral wirings change before the operation of the output amplifier O is completed, noises of different magnitudes appear on the read signal line RD and ▲ ▼. Will occur. Further, the pair of parallel write signal lines WR, ▲ ▼ of the input bus have different coupling capacitances between them and the peripheral wirings, so that the potential of these peripheral wirings is held in the memory cell M. If the change is made before, noises of different magnitudes are also generated in the write signal line WR and ▲ ▼. The noise source may be a word line near the input / output bus, a signal line for driving the column decoder, or another signal line in the input / output bus.
上述した従来の半導体メモリは、互いに逆相の信号を伝
達する読出し信号線対又は書込み信号線対と隣接する信
号伝達用配線間の結合容量が信号線対のそれぞれの信号
線に対して等しくなっていないので、信号線対に大きさ
の異なる雑音が生じ、出力増幅器が誤動作をしたり、メ
モリセルに誤つた情報が入力されたりするので、半導体
メモリの動作速度が低下するという欠点がある。In the conventional semiconductor memory described above, the coupling capacitance between the read signal line pair or the write signal line pair for transmitting signals of opposite phases and the adjacent signal transmission wiring is equal to each signal line of the signal line pair. However, since noise of different magnitudes is generated in the signal line pair, the output amplifier malfunctions, or incorrect information is input to the memory cell, which causes a drawback that the operation speed of the semiconductor memory decreases.
本発明の目的は、雑音が少なく高速動作可能な半導体メ
モリを提供することにある。It is an object of the present invention to provide a semiconductor memory that has low noise and can operate at high speed.
本発明の半導体メモリは、マトリックス状に配置された
複数のメモリセルのそれぞれに駆動回路の出力信号を接
続用回路を介して供給する互いに逆相の信号を伝達し全
長を等分する第１の交差箇所で互いに交差して位置を入
替えるとともに前記第１の交差箇所以外の部分で互いに
平行して隣接配置された第１の信号線及び第２の信号線
でなる書込み信号線対と、前記メモリセルに蓄積された
信号を前記接続用回路を介して読出して出力増幅器に供
給する互いに逆相の信号を伝達し一端から全長の四分の
一及び四分の三の長さだけそれぞれ離れた第２の交差箇
所及び第３の交差箇所でそれぞれ互いに交差して位置を
入替えるとともに前記第２の交差箇所及び第３の交差箇
所以外の部分で互いに平行して隣接配置された第３の信
号線及び第４の信号線でなる読出し信号線対とを有し、
前記第３の信号線及び第４の信号線の平行部が前記第１
の信号線及び第２の信号線の平行部と平行で前記第２の
交差箇所及び第３の交差箇所をそれぞれ前記第１の信号
線及び第２の信号線が前記第１の交差箇所によって等分
された各部分の長さの二分の一の箇所に対向して配置さ
れ、それによって前記第１の信号線及び第２の信号線が
それぞれ前記第３の信号線及び第４の信号線との間に有
する結合容量を等しくしたというものである。In the semiconductor memory of the present invention, the output signals of the drive circuit are supplied to each of the plurality of memory cells arranged in a matrix via the connection circuit, and signals of opposite phases are transmitted to equally divide the entire length. A write signal line pair made up of a first signal line and a second signal line, which cross each other at an intersection and switch positions, and are arranged adjacent to each other in parallel at a portion other than the first intersection, The signals stored in the memory cells are read out through the connection circuit and the signals of opposite phases to be supplied to the output amplifier are transmitted and are separated from one end by one-quarter and three-quarters of the total length, respectively. Third signals that are crossed with each other at the second intersection and the third intersection and exchange positions, and are arranged adjacent to each other in parallel with each other at portions other than the second intersection and the third intersection. Line and fourth belief And a read signal line pair comprising a line,
The parallel portion of the third signal line and the fourth signal line is the first portion.
Of the second signal line and the third signal line in parallel with the parallel portion of the signal line and the second signal line by the first signal line and the second signal line, respectively. The first signal line and the second signal line are arranged to face each other at a half of the length of each divided portion, so that the first signal line and the second signal line are respectively connected to the third signal line and the fourth signal line. That is, the coupling capacitances between the two are made equal.
次に、本発明の実施例について図面を参照して説明す
る。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.
第２図の従来例とメモリセル配置は同じであるが、出力
バスの一対の読出し信号線RDと▲▼は平行なまゝで
はなく、全長を二分する中央付近のａで交差し互いにそ
の位置を入替えて配置されている。また、入力バスの一
対の書込み信号線WRと▲▼は平行なままではなく、
左端から全長の1/4及び3/4の長さだけそれぞれ離れた２
箇所b1及びb2で交差し互いにその位置を入替えて配置さ
れている。Although the memory cell arrangement is the same as that of the conventional example of FIG. 2, the pair of read signal lines RD and ▲ ▼ of the output bus are not parallel to each other, but intersect at a near the center a that bisects the entire length, and their positions are mutually different. Are replaced with each other. Also, the pair of write signal lines WR and ▲ ▼ of the input bus do not remain parallel,
1/4 and 3/4 of the total length away from the left end 2
They intersect at points b 1 and b 2 and are arranged with their positions interchanged.
すなわち、書込み信号線WR,▲▼の交差箇所b1,b2は
いずれも読出し信号線RD,▲▼の交差箇所a1とずれ
ている。That is, the intersections b1 and b2 of the write signal line WR and ▲ ▼ are both displaced from the intersection a1 of the read signal line RD and ▲ ▼.
従って、読出し信号線RDと▲▼とはワード線W1,W2,
W3,書込み信号線WR,▲▼，列デコーダＹ内の信号線
等の任意の信号線と同じ結合容量を有している。同様に
書込み信号線WRと▲▼とはワード線W1,W2,W3、読出
し信号線RD,▲▼、列デコーダＹ内の信号線等の任
意の信号線と同じ結合容量を有している。なお、列デコ
ーダＹの長さは書込み信号線WR,▲▼の長さより若
干小さいがこれらの全長は大きいので実際上その差は無
視して差支えない。Therefore, the read signal line RD and ▲ ▼ are the word lines W 1 , W 2 ,
It has the same coupling capacitance as W 3 , the write signal line WR, and the arbitrary signal line such as the signal line in the column decoder Y. Similarly, the write signal lines WR and ▲ ▼ have the same coupling capacitance as the word lines W 1 , W 2 , W 3 , the read signal lines RD, ▲ ▼, and any signal line such as the signal line in the column decoder Y. ing. Although the length of the column decoder Y is slightly smaller than the length of the write signal lines WR, {circle around (3)}, their total length is large, so the difference can be practically ignored.
そういうわけで、出力増幅器Ｏの動作完了前にワード線
W1,W2,W3、列デコーダＹ内の信号線又は書込み信号線W
R,▲▼の電位が変動すると一対の読出し信号線RDと
▲▼とには大きさの等しい雑音が生じ、差動増幅を
行なう出力増幅器は誤動作しない。同様に、メモリセル
に情報を入力する場合にも、その入力動作時にワード線
W1,W2,W3、列デコーダＹ内の信号線又は読出し信号線R
D,▲▼の電位が変動すると、書込み信号線WRと▲
▼とには大きさの等しい雑音が生じるのでフリップ・
フロップ型のメモリセルに誤情報が書込まれることはな
い。Therefore, before the operation of the output amplifier O is completed, the word line
W 1 , W 2 , W 3 , signal line in column decoder Y or write signal line W
When the potentials of R and ▲ ▼ fluctuate, noise of equal magnitude is generated in the pair of read signal lines RD and ▲ ▼, and the output amplifier that performs differential amplification does not malfunction. Similarly, when inputting information to the memory cell, the word line
W 1 , W 2 , W 3 , signal line in column decoder Y or read signal line R
If the potential of D, ▲ ▼ fluctuates, write signal line WR and ▲
Since noises of the same magnitude are generated in ▼ and
No erroneous information is written in the flop type memory cell.
以上フリップ・フロップ型のメモリセルを有する場合に
ついて説明したが、メモリセルの型が異なっていても容
量結合による雑音は従来に比較して少くなるのであるか
ら誤情報が書込まれる可能性は大幅に低減されることは
いうまでもない。The case where the flip-flop type memory cell is provided has been described above. However, even if the type of the memory cell is different, the noise due to the capacitive coupling is smaller than that in the conventional case, and thus the possibility of writing erroneous information is large. Needless to say, it is reduced to.
又、入力バスと出力バス内にそれぞれ一対の信号線が存
在する場合について述べたが、互いに逆相の信号が伝達
される信号線の対の数はいくらあってもよい。Also, the case where a pair of signal lines exist in each of the input bus and the output bus has been described, but the number of pairs of signal lines through which signals of opposite phases are transmitted may be arbitrary.
以上説明したように、本発明は、書込み信号線対及び又
は読出し信号線対を一箇所以上で交差して互いにその位
置を入替えて配置することにより、これらの信号線対の
それぞれが他の任意の信号線との間に有する結合容量を
等しくかつ少なくできるので、信号線の電位変動に基く
容量結合による雑音が小さくなり、半導体メモリの高速
動作を可能にするという効果がある。As described above, according to the present invention, by arranging the write signal line pair and / or the read signal line pair at one or more locations and arranging the positions thereof interchangeably, each of these signal line pairs can be replaced with another arbitrary one. Since the coupling capacity between the signal line and the signal line can be made equal and small, noise due to capacitive coupling due to potential fluctuation of the signal line can be reduced, and high speed operation of the semiconductor memory can be achieved.
第１図は本発明の一実施例を示すブロック図、第２図は
従来の半導体メモリの一例を示すブロック図、第３図は
従来のメモリセルの一例の回路図、第４図は従来の接続
用回路の一例の回路図である。 D1,D2,D3,D4;1,2,3,４……ディジット線、Ｉ…
…駆動回路、M1,M2,……,M12……メモリセル、Ｏ……出
力増幅器、RD,▲▼……読出し信号線、S1,S2,S3,S4
……接続用回路、W1,W2,W3……ワード線、WR,▲▼
……書込み信号線、Ｘ……行デコーダ、Ｙ……列デコー
ダ、Y1,Y2,Y3,Y4……出力線。FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional semiconductor memory, FIG. 3 is a circuit diagram of an example of a conventional memory cell, and FIG. It is a circuit diagram of an example of a circuit for connection. D 1 , D 2 , D 3 , D 4 ; 1 , 2 , 3 , 4 ... Digit line, I ...
… Drive circuit, M 1 , M 2 , ……, M 12 …… Memory cell, O …… Output amplifier, RD, ▲ ▼ …… Read signal line, S 1 , S 2 , S 3 , S 4
...... Connection circuit, W 1 , W 2 , W 3 …… Word line, WR, ▲ ▼
...... write signal line, X ...... row decoder, Y ...... column decoder, Y 1, Y 2, Y 3, Y 4 ...... output line.
Claims (1)
セルのそれぞれに駆動回路の出力信号を接続用回路を介
して供給する互いに逆相の信号を伝達し全長を等分する
第１の交差箇所で互いに交差して位置を入替えるととも
に前記第１の交差箇所以外の部分で互いに平行して隣接
配置された第１の信号線及び第２の信号線でなる書込み
信号線対と、前記メモリセルに蓄積された信号を前記接
続用回路を介して読出して出力増幅器に供給する互いに
逆相の信号を伝達し一端から全長の四分の一及び四分の
三の長さだけそれぞれ離れた第２の交差箇所及び第３の
交差箇所でそれぞれ互いに交差して位置を入替えるとと
もに前記第２の交差箇所及び第３の交差箇所以外の部分
で互いに平行して隣接配置された第３の信号線及び第４
の信号線でなる読出し信号線対とを有し、前記第３の信
号線及び第４の信号線の平行部が前記第１の信号線及び
第２の信号線の平行部と平行で前記第２の交差箇所及び
第３の交差箇所をそれぞれ前記第１の信号線及び第２の
信号線が前記第１の交差箇所によって等分された各部分
の長さの二分の一の箇所に対向して配置され、それによ
って前記第１の信号線及び第２の信号線がそれぞれ前記
第３の信号線及び第４の信号線との間に有する結合容量
を等しくしたことを特徴とする半導体メモリ。1. A first crossing point for transmitting output signals of a drive circuit to a plurality of memory cells arranged in a matrix form via connection circuits and transmitting signals of opposite phases to divide the entire length equally. And a write signal line pair formed of a first signal line and a second signal line that are adjacent to each other in parallel with each other at positions other than the first intersecting point and that are interchanged in position, and the memory cell A second phase of reading the signal stored in the circuit through the connection circuit and transmitting signals of opposite phases to be supplied to the output amplifier, which are separated from one end by one-quarter and three-quarters of the total length, respectively. Crossing each other at the intersection and the third intersection and switching positions, and third signal lines that are arranged adjacent to each other in parallel to each other at portions other than the second intersection and the third intersection, and Fourth
A pair of read signal lines formed of signal lines, the parallel portion of the third signal line and the fourth signal line being parallel to the parallel portion of the first signal line and the second signal line. The second crossing point and the third crossing point are respectively opposite to the half point of the length of each part where the first signal line and the second signal line are equally divided by the first crossing point. The semiconductor memory is characterized in that the first signal line and the second signal line have the same coupling capacitance between them and the third signal line and the fourth signal line, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22212285A JPH07118518B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22212285A JPH07118518B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6281751A JPS6281751A (en) | 1987-04-15 |
| JPH07118518B2 true JPH07118518B2 (en) | 1995-12-18 |
Family
ID=16777506
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22212285A Expired - Lifetime JPH07118518B2 (en) | 1985-10-04 | 1985-10-04 | Semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118518B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63160092A (en) * | 1986-12-22 | 1988-07-02 | Mitsubishi Electric Corp | Semiconductor storage device |
| JPH0834300B2 (en) * | 1988-08-09 | 1996-03-29 | 三菱電機株式会社 | Semiconductor memory device having wiring structure |
| JP2508245B2 (en) * | 1989-03-07 | 1996-06-19 | 三菱電機株式会社 | Semiconductor memory device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS596067B2 (en) * | 1975-03-14 | 1984-02-08 | 株式会社日立製作所 | semiconductor memory |
| JPS59231852A (en) * | 1983-06-15 | 1984-12-26 | Hitachi Ltd | Semiconductor device |
| JPS6263465A (en) * | 1985-09-13 | 1987-03-20 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
-
1985
- 1985-10-04 JP JP22212285A patent/JPH07118518B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6281751A (en) | 1987-04-15 |
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