JPH07118486B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07118486B2 JPH07118486B2 JP60268538A JP26853885A JPH07118486B2 JP H07118486 B2 JPH07118486 B2 JP H07118486B2 JP 60268538 A JP60268538 A JP 60268538A JP 26853885 A JP26853885 A JP 26853885A JP H07118486 B2 JPH07118486 B2 JP H07118486B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- conductive material
- printed board
- package
- high thermal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Die Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 プリント板を基材とするICパッケージであって、ダイス
テージに高熱伝導材を接着することにより、熱的整合
性、低熱抵抗化、高密度グリッド化を実現する。DETAILED DESCRIPTION [Outline] An IC package using a printed board as a base material, which achieves thermal consistency, low thermal resistance, and high density grid by bonding a high thermal conductive material to a die stage. To do.
本発明は半導体装置に関し、さらに詳しく言えば、プリ
ント板を基材として熱的整合性、低熱抵抗化、高密度グ
リッド化を図ったICパッケージに関するものである。The present invention relates to a semiconductor device, and more particularly to an IC package that uses a printed board as a base material to achieve thermal matching, low thermal resistance, and high density grid.
〔従来の技術〕 集積回路が形成されたICチップを搭載したパッケージと
して、セラミックパッケージとプラスチックタイプパッ
ケージとが知られている。[Prior Art] Ceramic packages and plastic type packages are known as packages on which an IC chip having an integrated circuit is mounted.
第２図はセラミックパッケージを断面で示す図で、同図
において、31はICチップ、32はセラミック本体、33はメ
タライズ導体、34はリード、35はガラス,Au−Snあるい
はPb−Snのシール、36はセラミックまたはメタル製のキ
ャップ、37はワイヤで、ICチップ31に形成された集積回
路はワイヤ37、メタライズ導体33、リード34を経て図示
しない基板に設けられた電気回路に接続される。FIG. 2 is a cross-sectional view of a ceramic package, in which 31 is an IC chip, 32 is a ceramic body, 33 is a metallized conductor, 34 is a lead, 35 is glass, Au-Sn or Pb-Sn seal, 36 is a ceramic or metal cap, 37 is a wire, and the integrated circuit formed on the IC chip 31 is connected to an electric circuit provided on a substrate (not shown) through the wire 37, the metallized conductor 33, and the lead 34.
第３図はプラスチックタイプパッケージの断面図で、同
図において、41はICチップ、42は樹脂モールド、43はリ
ード、44はICチップ41の電極とリード43を接続するワイ
ヤ、45はICチップ41が接着されるステージである。FIG. 3 is a cross-sectional view of a plastic type package, in which 41 is an IC chip, 42 is a resin mold, 43 is a lead, 44 is a wire connecting the electrode of the IC chip 41 and the lead 43, and 45 is an IC chip 41. Is the stage where is glued.
〔発明が解決しようとする問題点〕 セラミックパッケージはコストが高い点に問題があり、
そのコストを低減すべくプラスチックタイプパッケージ
が開発されたが、ピンがグリッド状に配列されたピング
リッドアレー（PGA）は今なおセラミックパッケージを
用い、PGAをプラスチック化することはピンの数との関
係できわめて難しい。そこでPGAのコストを低減するこ
とが可能なパッケージが求められているが、未だ満足す
べきパッケージは公にされていない。[Problems to be Solved by the Invention] The ceramic package has a problem of high cost,
A plastic type package was developed to reduce the cost, but the pin grid array (PGA) in which the pins are arranged in a grid is still using the ceramic package, and making the PGA plastic is related to the number of pins. Is extremely difficult. Therefore, there is a demand for a package that can reduce the cost of PGA, but a satisfactory package has not yet been made public.
さらに、ICパッケージにおいてはICチップの発生する熱
の放熱に問題があり、ICチップにＣMOSデバイスが形成
されているときは放熱についてさほど問題はないが、バ
イポーラデバイスはかなりの熱を発生するので、その高
熱を放熱するについてプラスチックタイプパッケージは
十分でない。Furthermore, there is a problem in heat dissipation of heat generated by the IC chip in the IC package, and there is no problem in heat dissipation when the CMOS device is formed in the IC chip, but the bipolar device generates a considerable amount of heat. Plastic type package is not enough to dissipate its high heat.
本発明はこのような点に鑑みて創作されたもので、熱的
整合性、低熱抵抗化、高密度グリッド化が実現される半
導体装置のパッケージを提供することを目的とする。The present invention has been made in view of the above points, and an object thereof is to provide a package of a semiconductor device that achieves thermal matching, low thermal resistance, and high density grid.
上記課題は、ICチップの下部の第１の熱膨張係数を有す
るプリント板に空洞が形成され、空洞には第２の熱膨張
係数を有する低熱抵抗性の高熱伝導材が配置され、第１
の熱膨張係数と第２の熱膨張係数とは近似であることを
特徴とする半導体装置、および、ダイステージの下部領
域を含めプリント板にピンを挿通し、ダイステージのピ
ン上部に高熱伝導材を接着してなることを特徴とする半
導体装置を提供することによって解決される。The above problem is that a cavity is formed in a printed board having a first thermal expansion coefficient below the IC chip, and a low thermal resistance high thermal conductive material having a second thermal expansion coefficient is disposed in the cavity.
And the second coefficient of thermal expansion of the semiconductor device are approximate, and a pin is inserted into the printed board including the lower region of the die stage, and a high thermal conductive material is provided above the pin of the die stage. The problem is solved by providing a semiconductor device characterized by comprising:
第１図（ａ）ないし（ｅ）は本発明実施例の断面図で、
これらの図において、11はICパッケージの基材であるプ
リント板、12はICチップ、13はプリント板に接着されそ
の上にICチップ12が接着される高熱伝導材である。1 (a) to (e) are sectional views of an embodiment of the present invention.
In these figures, 11 is a printed board which is a base material of an IC package, 12 is an IC chip, and 13 is a high thermal conductive material which is adhered to the printed board and on which the IC chip 12 is adhered.
第１図（ａ）と（ｂ）の実施例において、シリコンの熱
膨張係数に近い熱膨張係数をもつ低熱抵抗性の高熱伝導
材13はプリント板11に形成されたダイステージ14に配置
され、 第１図（ｃ）の実施例においてプリント板11はダイステ
ージ14の下方が空洞になり、そこに高熱伝導材が配置さ
れ、 第１図（ｄ）のキャビティダウンタイプの実施例におい
ては、前記した空洞内に放熱フィン15が形成された高熱
伝導材が配置され、 第１図（ｅ）の実施例においては、プリント板11にピン
17挿通用の孔16があけられ、ダイステージ14に高熱伝導
材13が配置されている。In the embodiment shown in FIGS. 1 (a) and 1 (b), a low thermal resistance high thermal conductive material 13 having a thermal expansion coefficient close to that of silicon is arranged on a die stage 14 formed on the printed board 11, In the embodiment of FIG. 1 (c), the printed board 11 has a cavity below the die stage 14, and a high thermal conductive material is placed therein, and in the cavity down type embodiment of FIG. 1 (d), A high thermal conductive material having a radiation fin 15 formed therein is arranged in the hollow, and in the embodiment of FIG. 1 (e), the printed board 11 is pinned.
17 A hole 16 for insertion is formed, and a high heat conductive material 13 is arranged on a die stage 14.
高熱伝導材には下記に示す材料を用い、それらの熱伝導
率（W/m・゜Ｋ）、熱膨張係数（×10-6/℃）をプリント
板、ICチップ（シリコン）のそれと比較すると下記の値
が得られる。The following materials are used for the high thermal conductivity material, and their thermal conductivity (W / m · ° K) and thermal expansion coefficient (× 10 -6 / ° C) are compared with those of printed boards and IC chips (silicon). The following values are obtained.
上記の表から理解される如く、ICチップの発生する熱は
低熱抵抗の高熱伝導材13よって放熱され、他方ICチップ
31と高熱伝導材とは熱膨張係数が近似するから、ICチッ
プが熱サイクルによって膨張／収縮してもそれと同様に
高熱伝導材も膨張／収縮するので、ICチップにかかるス
トレスが軽減され、ICパッケージの信頼性が保障され
る。 As can be understood from the above table, the heat generated by the IC chip is radiated by the high thermal conductive material 13 having low thermal resistance, while the IC chip is
31 and the high thermal conductive material have similar thermal expansion coefficients, so even if the IC chip expands / contracts due to the thermal cycle, the high thermal conductive material also expands / contracts, so the stress on the IC chip is reduced and the IC The reliability of the package is guaranteed.
以下、図面を参照して本発明の実施例を詳細に説明す
る。Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
第１図（ａ）は本発明第１実施例を示し、プリント板11
は、第１の熱膨張係数を有する耐熱ガラエポ/BTレジン
／ポリイミド／銅コア材の多層構造のもので、従来のセ
ラミックに比べコストは約半分程節減される。プリント
板11には図示しない配線層が形成され、その配線層にIC
チップ12の電極（パッド）がワイヤ18で接続されピン17
への接続がとられる。プリント板のダム11aには、陽極
酸化したAlで作ったキャップ19がエポキシ系の接着樹脂
20で接着されている。FIG. 1 (a) shows a first embodiment of the present invention, which is a printed board 11
Has a multi-layer structure of heat-resistant glass epoxy / BT resin / polyimide / copper core material having the first coefficient of thermal expansion, and the cost is reduced by about half compared to conventional ceramics. A wiring layer (not shown) is formed on the printed board 11, and the IC is placed on the wiring layer.
The electrode (pad) of chip 12 is connected by wire 18 and pin 17
Connection is made to. On the dam 11a of the printed board, the cap 19 made of anodized Al is an epoxy adhesive resin.
It is glued at 20.
プリント板11のダイステージ14には第１の熱膨張係数に
近似する第２の熱膨張係数を有する高熱伝導材13が例え
ばエポキシ系の接着樹脂20で接着され、他方高熱伝導材
13には銀ペースト21でICチップ12が接着されている。エ
ポキシ系の接着樹脂は柔軟性をもっているので、高熱伝
導体のためのクッションとなる効果がある。A high thermal conductive material 13 having a second thermal expansion coefficient close to the first thermal expansion coefficient is adhered to the die stage 14 of the printed board 11 with, for example, an epoxy adhesive resin 20, while the high thermal conductive material is used.
The IC chip 12 is bonded to 13 with silver paste 21. Since the epoxy adhesive resin has flexibility, it has an effect of forming a cushion for the high thermal conductor.
本発明においては、ICチップ12が熱をもつと、その熱は
高熱伝導材13によって吸収され、その熱がプリント板11
にそのまま伝導されることが防止される。そして、熱サ
イクルによってICチップ12が膨張／収縮すると、高熱伝
導材の熱膨張係数はICチップのそれと近似するから、高
熱伝導材はICチップと共に膨張／収縮し、ICチップにス
トレスが加えられることが防止される。In the present invention, when the IC chip 12 has heat, the heat is absorbed by the high thermal conductive material 13, and the heat is absorbed by the printed board 11.
Is prevented from being directly transmitted to. When the IC chip 12 expands / contracts due to the thermal cycle, the coefficient of thermal expansion of the high thermal conductive material approximates that of the IC chip, so the high thermal conductive material expands / contracts together with the IC chip, and stress is applied to the IC chip. Is prevented.
第１図（ｂ）に示す実施例ではダム11aがないために、
キャップ19がプリント板本体の側部まで延在する構成と
なっている。ダム11aがなく、キャップ19が変型してい
る点を除くと、この実施例は第１図（ａ）の実施例とほ
ぼ同じ構造である。Since there is no dam 11a in the embodiment shown in FIG. 1 (b),
The cap 19 is configured to extend to the side of the printed board body. This embodiment has substantially the same structure as the embodiment of FIG. 1 (a) except that the dam 19a is not provided and the cap 19 is modified.
第１図（ｃ）に示される本発明の第２実施例において
は、ダイステージ14の下方に空洞22が形成され、この空
洞22内に高熱伝導材13が配置され、それはエポキシ系の
接着樹脂20によってプリント板11に接着されている。こ
れを除きその他の部分は第１図（ａ）の実施例と同様で
ある。In the second embodiment of the present invention shown in FIG. 1 (c), a cavity 22 is formed below the die stage 14, and a high thermal conductive material 13 is disposed in the cavity 22, which is an epoxy adhesive resin. It is adhered to the printed board 11 by 20. Except for this, the other parts are the same as those of the embodiment shown in FIG.
第１図（ｄ）の本発明の第３実施例においては、空洞22
にCu製のフィン15をもった高熱伝導材13が配置されるリ
ードレスチップキャリヤー（LCC）を示す。Cuは、熱膨
張係数が他の材料とは若干異なるが、フィンを作るにつ
いて加工性に優れる利点がある。この高熱伝導材もエポ
キシ系の接着樹脂でプリント板に接着する。なお、図の
片方のみに点線で示す如き形状のプリント板にピン17を
設けてPGAとしてもよい。第２と第３の実施例では、IC
チップの熱がほとんどプリント板11に伝わらない利点が
あり、第３図実施例ではフィン15によって放熱効果が高
められる。In the third embodiment of the present invention of FIG. 1 (d), the cavity 22
A leadless chip carrier (LCC) in which a high thermal conductive material 13 having fins 15 made of Cu is arranged is shown in FIG. Cu has a coefficient of thermal expansion slightly different from that of other materials, but has an advantage of excellent workability in forming fins. This high thermal conductive material is also adhered to the printed board with an epoxy adhesive resin. It should be noted that the PGA may be formed by providing the pin 17 on a printed board having a shape shown by a dotted line only on one side of the drawing. In the second and third embodiments, the IC
There is an advantage that almost no heat of the chip is transferred to the printed board 11, and in the embodiment of FIG. 3, the fin 15 enhances the heat radiation effect.
第１図（ｅ）に示される本願のもう１つの発明において
は、同図の上に示される如くプリント板11に所定数の孔
16をあける。孔16の内径はピン17の外径よりも小に設定
する。In another invention of the present application shown in FIG. 1 (e), a predetermined number of holes are formed in the printed board 11 as shown in the figure.
Open 16 The inner diameter of the hole 16 is set smaller than the outer diameter of the pin 17.
次いで、同図の中央に示される如く、図示しない当て板
を用いてピン17を孔16に挿通する。このとき、ダイステ
ージ14の表面はピン17が突出して凹凸になる。Then, as shown in the center of the figure, the pin 17 is inserted into the hole 16 using a contact plate (not shown). At this time, the pins 17 protrude and become uneven on the surface of the die stage 14.
次に同図の下に示される如く接着材を用いて高熱伝導材
13をキャビティに接着し、次いで例えば第１図（ａ）に
示される構造のパッケージを作る。従来、ダイステージ
にはピン17を設けることをしなかったが、この発明によ
ってダイステージにもピンを設けることが可能となり、
ピンの数の増大する（高密度グリッド化）に効果があ
る。高熱伝導材13は前記の実施例と同様、熱的整合性、
低熱抵抗化に効果があるだけでなく、ダイステージ表面
を平坦化しICチップの接着を確実なものにする効果があ
る。Next, as shown in the lower part of the figure, a high thermal conductive material is used by using an adhesive material.
13 is adhered to the cavity, and then a package having a structure shown in FIG. 1 (a) is prepared. Conventionally, the pin 17 was not provided on the die stage, but this invention makes it possible to provide the pin on the die stage,
It is effective for increasing the number of pins (high density grid). The high thermal conductive material 13 has the same thermal compatibility as in the above-mentioned embodiment,
Not only is it effective for lowering the thermal resistance, but it is also effective for flattening the die stage surface and ensuring IC chip adhesion.
以上述べてきたように、本発明によれば、プリント板を
基材とするICパッケージにおいて、ダイステージに高熱
伝導材を設けることにより、熱的整合性、低熱抵抗化、
高密度グリッド化が実現され,ICパッケージの信頼性を
向上するとともにその応用範囲を増大し、さらにはICパ
ッケージのコストを従来のセラミックパッケージに比べ
て約半分に低減する効果がある。As described above, according to the present invention, in an IC package using a printed board as a base material, by providing a high thermal conductive material on the die stage, thermal consistency, low thermal resistance,
High-density grid is realized, the reliability of IC package is improved, its application range is expanded, and the cost of IC package is reduced to about half compared with the conventional ceramic package.
第１図（ａ）は本発明の第１実施例の断面図、 第１図（ｂ）は第１実施例の変型例の断面図、 第１図（ｃ）は本発明第２実施例の断面図、 第１図（ｄ）は本発明第３実施例の断面図、 第１図（ｅ）は本願のもう１つの発明の実施例の断面
図、 第２図は従来のセラミックパッケージの断面図、 第３図は従来のプラスチックタイプパッケージの断面図
である。 第１図において、 11はプリント板、 11aはダム、 12はICチップ、 13は高熱伝導材、 14はダイステージ、 15はフィン、 16は孔、 17はピン、 18はワイヤ、 19はキャップ、 20はエポキシ系の接着樹脂、 21は銀ペースト、 22は空洞である。1 (a) is a sectional view of a first embodiment of the present invention, FIG. 1 (b) is a sectional view of a modified example of the first embodiment, and FIG. 1 (c) is a second embodiment of the present invention. Sectional drawing, FIG. 1 (d) is a sectional view of a third embodiment of the present invention, FIG. 1 (e) is a sectional view of another embodiment of the present invention, and FIG. 2 is a sectional view of a conventional ceramic package. FIG. 3 is a sectional view of a conventional plastic type package. In FIG. 1, 11 is a printed board, 11a is a dam, 12 is an IC chip, 13 is a high thermal conductive material, 14 is a die stage, 15 is a fin, 16 is a hole, 17 is a pin, 18 is a wire, 19 is a cap, 20 is an epoxy adhesive resin, 21 is a silver paste, and 22 is a cavity.
Claims (1)
ント板（11）にピン（17）を挿通し、ダイステージのピ
ン上部に高熱伝導材（13）を接着してなることを特徴と
する半導体装置。1. A pin (17) is inserted into a printed board (11) including a lower region of a die stage (14), and a high thermal conductive material (13) is adhered to an upper portion of the pin of the die stage. Semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60268538A JPH07118486B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60268538A JPH07118486B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62128535A JPS62128535A (en) | 1987-06-10 |
| JPH07118486B2 true JPH07118486B2 (en) | 1995-12-18 |
Family
ID=17459912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60268538A Expired - Lifetime JPH07118486B2 (en) | 1985-11-29 | 1985-11-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07118486B2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5787539U (en) * | 1980-11-17 | 1982-05-29 | ||
| JPS57107063A (en) * | 1980-12-25 | 1982-07-03 | Nec Corp | Semiconductor package |
| JPS57164541A (en) * | 1982-02-19 | 1982-10-09 | Hitachi Ltd | Electric device |
| JPS59112940U (en) * | 1983-12-07 | 1984-07-30 | 株式会社日立製作所 | semiconductor equipment |
-
1985
- 1985-11-29 JP JP60268538A patent/JPH07118486B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62128535A (en) | 1987-06-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |