JPH07114241B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH07114241B2 JPH07114241B2 JP61248754A JP24875486A JPH07114241B2 JP H07114241 B2 JPH07114241 B2 JP H07114241B2 JP 61248754 A JP61248754 A JP 61248754A JP 24875486 A JP24875486 A JP 24875486A JP H07114241 B2 JPH07114241 B2 JP H07114241B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- epitaxial layer
- conductivity type
- layer
- well region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000009792 diffusion process Methods 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000000926 separation method Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Non-Volatile Memory (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はMIS（金属−絶縁物−半導体）型不揮発性記憶
素子を備えた半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a MIS (metal-insulator-semiconductor) type nonvolatile memory element.
従来の技術 LSI技術の進歩に伴ない、半導体集積回路の高性能化，
高機能化が進む中で、同一チップ上にMIS型不揮発性記
憶素子を用いた電気的書き換え可能なROM（EEPROM）と
マイクロコンピュータなどの制御回路機能とを共存させ
る要求が高まっている。たとえば、MIS型不揮発性記憶
素子の１つとして、シリコン基板上にトンネリング媒体
となりうる薄い酸化膜を形成し、その上に窒化シリコン
膜を形成させ、さらにその上にゲート電極を形成したMN
OS（金属−窒化シリコン膜−酸化シリコン膜−半導体）
構造の不揮発性メモリトランジスタがよく知られている
が、このMNOSメモリトランジスタを用いたメモリ回路部
と、このメモリ回路をコントロールする制御回路部とを
同一チップに共存させたMNOSメモリ内蔵を１チップマイ
クロコンピュータがある。Conventional technology With the progress of LSI technology, high performance of semiconductor integrated circuits,
As the number of functions increases, the demand for coexistence of electrically rewritable ROM (EEPROM) using MIS type nonvolatile memory elements and control circuit functions such as microcomputers on the same chip is increasing. For example, as one of the MIS type nonvolatile memory elements, a thin oxide film which can be a tunneling medium is formed on a silicon substrate, a silicon nitride film is formed on the thin oxide film, and a gate electrode is formed on the MN.
OS (metal-silicon nitride film-silicon oxide film-semiconductor)
A non-volatile memory transistor with a structure is well known, but a memory circuit section using this MNOS memory transistor and a control circuit section for controlling this memory circuit coexist on the same chip. I have a computer.
このようなMIS型不揮発性記憶素子からなるメモリ回路
部と、MIS電界効果トランジスタからなる周辺回路部と
を同一基板上に共存させた半導体装置においては、メモ
リ以外の周辺回路を同一チップに集積するので、チップ
の消費電力が増加し、このためチップの温度上昇が起こ
り、同一チップ上に共存させた不揮発性メモリトランジ
スタの記憶保持特性に悪い影響を与え、これを防ぐた
め、周辺回路部は、できるだけ低消費電力化が可能なCM
OS（相補MOS）化することが必要である。In a semiconductor device in which a memory circuit section including such a MIS type nonvolatile memory element and a peripheral circuit section including an MIS field effect transistor coexist on the same substrate, peripheral circuits other than the memory are integrated on the same chip. Therefore, the power consumption of the chip increases, which causes the temperature of the chip to rise, which adversely affects the memory retention characteristics of the non-volatile memory transistors coexisting on the same chip. CM that can reduce power consumption as much as possible
It is necessary to make OS (complementary MOS).
こうした不揮発性記憶素子とCMOS素子を同一チップ上に
共存させた半導体装置を実現するには、不揮発性記憶素
子とCMOS素子とを電気的に分離する必要があり、従来は
第２図に示すように、一導電型の半導体基板１上に基板
と反対導電型のエピタキシャル層20を設け、前記エピタ
キシャル層20を基板と同一導電型の分離拡散層21により
分離し、この分離エピタキシャル層22に不揮発性記憶素
子を形成し、一方、CMOS素子はエピタキシャル層20とエ
ピタキシャル層内に形成したウエル領域23に形成して分
離する構造が通常であった。In order to realize a semiconductor device in which a nonvolatile memory element and a CMOS element coexist on the same chip, it is necessary to electrically separate the nonvolatile memory element and the CMOS element. Conventionally, as shown in FIG. , An epitaxial layer 20 of a conductivity type opposite to that of the substrate is provided on the semiconductor substrate 1 of a conductivity type, and the epitaxial layer 20 is separated by a separation diffusion layer 21 of the same conductivity type as the substrate. The memory element is usually formed, while the CMOS element is usually formed in the epitaxial layer 20 and the well region 23 formed in the epitaxial layer and separated.
発明が解決しようとする問題点 しかしながら、第２図に示すような従来の構造では、CM
OSのウエル領域23の空乏層と半導体基板１の空乏層が接
近して、ウエル領域23が半導体基板１と同電位とならな
いようにするために、エピタキシャル層20の厚みを十分
厚くする必要（通常15〜20μｍ）があるが、エピタキシ
ャル層20を厚くすると不揮発性記憶素子を分離する分離
拡散層21が非常に深い拡散層となり、それに伴い分離拡
散の横方向の拡散も非常に大きくなり、分離に要する面
積を増加させ、その結果、メモリ回路部の集積度があま
り上がらないといった欠点を有していた。Problems to be Solved by the Invention However, in the conventional structure as shown in FIG.
In order to prevent the depletion layer of the OS well region 23 and the depletion layer of the semiconductor substrate 1 from approaching each other and the well region 23 to have the same potential as the semiconductor substrate 1, the epitaxial layer 20 must be thick enough (normally 15 to 20 μm), but if the epitaxial layer 20 is thickened, the separation diffusion layer 21 for separating the non-volatile memory element becomes a very deep diffusion layer, and accordingly, the lateral diffusion of the separation diffusion also becomes very large. There is a drawback in that the required area is increased and, as a result, the degree of integration of the memory circuit portion does not increase so much.
本発明の目的は、MIS型不揮発性記憶素子およびCMOS回
路を同一チップ上に共存させる半導体装置において、MI
S型不揮発性素子の分離に必要な面積を減少させ、高集
積化をはかることができる構造を提供することにある。An object of the present invention is to provide a MIS-type nonvolatile memory element and a CMOS circuit in a semiconductor device that coexist on the same chip.
An object of the present invention is to provide a structure capable of achieving high integration by reducing the area required for separating S-type nonvolatile elements.
問題点を解決するための手段 上記目的を達成するために、本発明は一導電型半導体基
板に反対導電型の埋め込み拡散領域および前記半導体基
板上にこれと同一導電型のエピタキシャル層を備え、前
記エピタキシャル層に反対導電型の第１のウエル領域お
よび前記埋め込み拡散領域に達し、同エピタキシャル層
が分離された分離エピタキシャル層を形成する反対導電
型の第２のウエル領域を備え、前記第１のウエル領域に
前記半導体基板と同一導電型のMIS型不揮発性記憶素
子、前記第２のウエル領域および、前記分離エピタキシ
ャル層に、おのおの、相補的をなすMIS型電界効果トラ
ンジスタをそなえた半導体装置である。Means for Solving the Problems In order to achieve the above object, the present invention provides a semiconductor substrate of one conductivity type with a buried diffusion region of the opposite conductivity type and an epitaxial layer of the same conductivity type on the semiconductor substrate. The epitaxial layer includes a first well region of opposite conductivity type and a second well region of opposite conductivity type reaching the buried diffusion region and forming a separate epitaxial layer in which the same epitaxial layer is separated. In the semiconductor device, a MIS type nonvolatile memory element having the same conductivity type as that of the semiconductor substrate, a second well region, and the isolation epitaxial layer are provided with complementary MIS type field effect transistors, respectively.
作用 本発明の構造によれば、エピタキシャル層から埋め込み
拡散領域に達する第２のウエル領域内および、同ウエル
領域と埋め込み拡散領域とにより分離された分離エピタ
キシャル層内にCMOS素子が設けられているため、不揮発
性記憶素子はエピタキシャル層の第１のウエル領域内に
形成することで、セル面積を非常に小さくすることがで
きる。According to the structure of the present invention, the CMOS element is provided in the second well region reaching the buried diffusion region from the epitaxial layer and in the isolation epitaxial layer separated by the well region and the buried diffusion region. By forming the nonvolatile memory element in the first well region of the epitaxial layer, the cell area can be made extremely small.
実施例 以下、具体的な実施例を図面を用いて説明する。第１図
は本発明の一実施例である半導体装置の断面構造図であ
る。この実施例は、ｎ型シリコン基板１のＰ型の埋め込
み層２、および、その上にｎ型のエピタキシャル層３を
そなえている。ｎ型のシリコン基板１の不純物濃度とし
ては、たとえば２×1015cm-3程度のものを用い、ｎ型エ
ピタキシャル層３は、リンを不純物として、1015cm-3程
度の濃度で、厚みは７μｍとした。Example Hereinafter, a specific example will be described with reference to the drawings. FIG. 1 is a sectional structural view of a semiconductor device which is an embodiment of the present invention. In this embodiment, a P-type buried layer 2 of an n-type silicon substrate 1 and an n-type epitaxial layer 3 are provided thereon. The impurity concentration of the n-type silicon substrate 1 is, for example, about 2 × 10 15 cm −3 , and the n-type epitaxial layer 3 contains phosphorus as an impurity at a concentration of about 10 15 cm −3 and has a thickness of about 10 15 cm −3. It was 7 μm.
次に、エピタキシャル層３の表面から第１のＰ型ウエル
層４が形成され、さらに、エピタキシャル層３の表面か
ら埋め込み層２に達するように第２のＰ型ウエル層５が
形成されている。この第２のＰ型ウエル層５と埋め込み
層２とにより、第１図に示すように、エピタキシャル層
３を分離し、分離エピタキシャル層６が形成できる。本
実施例では、第１のＰ型ウエル層４と第２のウエル層５
とは同時に形成し、両ウエルの不純物表面濃度を約１×
1016cm-3、拡散深さを約５μｍとした。また、Ｐ型ウエ
ル層を形成する熱処理においては、Ｐ型の埋め込み層２
が上部に拡散するので、Ｐ型ウエル層５とＰ型埋め込み
層２とがオーバーラップするように熱処理条件を制御す
る。Next, the first P-type well layer 4 is formed from the surface of the epitaxial layer 3, and further the second P-type well layer 5 is formed so as to reach the buried layer 2 from the surface of the epitaxial layer 3. With the second P-type well layer 5 and the buried layer 2, the epitaxial layer 3 can be separated and the separated epitaxial layer 6 can be formed, as shown in FIG. In this embodiment, the first P-type well layer 4 and the second P-type well layer 5 are used.
Are formed at the same time, and the impurity surface concentration of both wells is about 1 ×
The diffusion depth was 10 16 cm -3 and the diffusion depth was about 5 μm. In the heat treatment for forming the P-type well layer, the P-type buried layer 2
Is diffused to the upper portion, the heat treatment conditions are controlled so that the P-type well layer 5 and the P-type buried layer 2 overlap each other.
以上のように形成された第１のＰ型ウエル層４の表面領
域に、ｎチャネル型のMNOS型不揮発性メモリトランジス
タを形成する。このトランジスタは、ｎ型拡散層7,8
を、それぞれ、ソース，ドレインとし、酸化シリコン膜
9,窒化シリコン膜10上にゲート電極11を設けた構造とな
っている。酸化シリコン膜９は、MNOS型メモリトランジ
スタのトンネリング媒体となりうるように、膜厚を約20
Åとした。さらに、酸化シリコン膜９上の窒化シリコン
膜10は、シラン（SiH4）とアンモニア（NH3）の化学反
応に基づく気相成長法により約500Å形成させ、ゲート
電極11としては、ポリシリコンの金属性電極を用いた。An n-channel MNOS nonvolatile memory transistor is formed in the surface region of the first P-type well layer 4 formed as described above. This transistor has n-type diffusion layers 7 and 8
As a source and a drain, respectively, and a silicon oxide film
9, The gate electrode 11 is provided on the silicon nitride film 10. The silicon oxide film 9 has a film thickness of about 20 so that it can be used as a tunneling medium for the MNOS type memory transistor.
Å Further, the silicon nitride film 10 on the silicon oxide film 9 is formed by a vapor phase growth method based on a chemical reaction of silane (SiH 4 ) and ammonia (NH 3 ) to about 500 Å, and the gate electrode 11 is made of polysilicon metal. A sex electrode was used.
さらに、第２のＰ型ウエル層５の表面領域に、ｎチャネ
ル型MOSトランジスタを形成する。このトランジスタ
は、ｎ型拡散層12,13をソース，ドレインとして、ゲー
ト絶縁膜14上にゲート電極15を設けた構造である。ゲー
ト絶縁膜14として二酸化シリコン膜を用い、ゲート電極
15として、たとえばポリシリコンの金属性電極を用い
る。Further, an n-channel MOS transistor is formed in the surface region of the second P-type well layer 5. This transistor has a structure in which a gate electrode 15 is provided on a gate insulating film 14 using the n-type diffusion layers 12 and 13 as sources and drains. A silicon dioxide film is used as the gate insulating film 14, and the gate electrode
For example, a metal electrode of polysilicon is used as 15.
また、分離エピタキシャル層６の表面領域に、Ｐチャネ
ル型のMOSトランジスタを形成する。このトランジスタ
は、Ｐ型拡散層16,17をそれぞれソース，ドレインとし
て、ゲート絶縁膜18上にゲート電極19を設けた構造であ
る。ゲート絶縁膜18としては、二酸化シリコン膜を用
い、ゲート電極19としては、たとえばポリシリコンの金
属性電極を用いる。Further, a P-channel type MOS transistor is formed in the surface region of the separation epitaxial layer 6. This transistor has a structure in which a gate electrode 19 is provided on a gate insulating film 18 using the P type diffusion layers 16 and 17 as a source and a drain, respectively. A silicon dioxide film is used as the gate insulating film 18, and a metal electrode made of, for example, polysilicon is used as the gate electrode 19.
最後に、上述のｎチャネルMOSトランジスタとＰチャネ
ルMOSトランジスタを相補的に接続することによりCMOS
回路を構成することができる。Finally, the n-channel MOS transistor and the P-channel MOS transistor described above are connected complementarily to each other to form a CMOS.
A circuit can be constructed.
本実施例ではMIS型不揮発性記憶素子として、MNOS型不
揮発性メモリトランジスタを用いた場合について述べた
が、ゲート絶縁膜として窒化シリコン膜の代りに、たと
えば酸化アルミニウム（Al2O3），酸化タンタル（Ta
2O3）等の高誘電体膜を用いてもよい。In this embodiment, the case where the MNOS type non-volatile memory transistor is used as the MIS type non-volatile memory element has been described. However, instead of the silicon nitride film as the gate insulating film, for example, aluminum oxide (Al 2 O 3 ) or tantalum oxide is used. (Ta
A high dielectric film such as 2 O 3 ) may be used.
発明の効果 以上のように、本発明の構造によれば、MIS型不揮発性
記憶素子およびCMOS素子の双方を備えた半導体装置にお
いて、ウエル領域を用いて分離エピタキシャル層を形成
することができるのでMIS型不揮発性記憶素子の分離に
必要な面積を大幅に減少させることが可能となり、高集
積化に大きく寄与することができる。EFFECTS OF THE INVENTION As described above, according to the structure of the present invention, the isolation epitaxial layer can be formed using the well region in the semiconductor device including both the MIS type nonvolatile memory element and the CMOS element. The area required for the separation of the nonvolatile memory element can be significantly reduced, which can greatly contribute to high integration.
第１図は本発明の一実施例である半導体装置の構造断面
図、第２図は従来の半導体装置の断面構造図である。 １……ｎ型シリコン基板、２……Ｐ型埋め込み層、３…
…ｎ型エピタキシャル層、4,5……Ｐ型ウエル層、６…
…分離エピタキシャル層、7,8……ｎ型拡散層、９……
酸化シリコン膜、10……窒化シリコン膜、11……ゲート
電極、12,13……ｎ型拡散層、14……ゲート絶縁膜、15
……ゲート電極、16,17……Ｐ型拡散層、18……ゲート
絶縁膜、19……ゲート電極。FIG. 1 is a structural sectional view of a semiconductor device which is an embodiment of the present invention, and FIG. 2 is a sectional structural view of a conventional semiconductor device. 1 ... n type silicon substrate, 2 ... P type buried layer, 3 ...
... n-type epitaxial layer, 4,5 ... P-type well layer, 6 ...
... Separation epitaxial layer, 7,8 ... n-type diffusion layer, 9 ...
Silicon oxide film, 10 ... Silicon nitride film, 11 ... Gate electrode, 12, 13 ... N-type diffusion layer, 14 ... Gate insulating film, 15
...... Gate electrode, 16,17 …… P-type diffusion layer, 18 …… Gate insulating film, 19 …… Gate electrode.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 29/788 29/792 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/788 29/792
Claims (2)
た一導電型の半導体基板上に、これと同一導電型のエピ
タキシャル層が形成され、前記エピタキシャル層に反対
導電型の第１のウエル領域および前記埋め込み拡散領域
に達し、同エピタキシャル層が分離された分離エピタキ
シャル層を形成する反対導電型の第２のウエル領域を備
え、前記第１のウエル領域にMIS型不揮発性記憶素子、
前記第２のウエル領域および前記分離エピタキシャル層
に、おのおの、相補対をなすMIS型電界効果トランジス
タをそなえた半導体装置。1. An epitaxial layer of the same conductivity type is formed on a semiconductor substrate of the same conductivity type in which a buried diffusion region of the opposite conductivity type is formed, and a first well region of the opposite conductivity type is formed in the epitaxial layer. And a second well region of the opposite conductivity type that reaches the buried diffusion region and forms a separate epitaxial layer in which the same epitaxial layer is separated, and the first well region has a MIS type nonvolatile memory element,
A semiconductor device in which a complementary pair of MIS field effect transistors are provided in the second well region and the isolation epitaxial layer, respectively.
化シリコン膜−酸化シリコン膜−半導体）型不揮発性記
憶素子であることを特徴とする特許請求の範囲第（１）
項記載の半導体装置。2. The MIS type non-volatile memory element is a MNOS (metal-silicon nitride film-silicon oxide film-semiconductor) type non-volatile memory element.
The semiconductor device according to the item.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61248754A JPH07114241B2 (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61248754A JPH07114241B2 (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63102370A JPS63102370A (en) | 1988-05-07 |
| JPH07114241B2 true JPH07114241B2 (en) | 1995-12-06 |
Family
ID=17182876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61248754A Expired - Lifetime JPH07114241B2 (en) | 1986-10-20 | 1986-10-20 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07114241B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0897163A (en) | 1994-07-28 | 1996-04-12 | Hitachi Ltd | Semiconductor wafer, manufacture thereof, semiconductor integrated circuit device, and manufacture thereof |
| JP3529549B2 (en) | 1996-05-23 | 2004-05-24 | 東芝マイクロエレクトロニクス株式会社 | Method for manufacturing semiconductor device |
| JP2003152102A (en) * | 2001-11-15 | 2003-05-23 | Hitachi Ltd | Method of manufacturing semiconductor integrated circuit device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58196045A (en) * | 1982-05-11 | 1983-11-15 | Toshiba Corp | Complementary mos semiconductor device |
| US4516313A (en) * | 1983-05-27 | 1985-05-14 | Ncr Corporation | Unified CMOS/SNOS semiconductor fabrication process |
-
1986
- 1986-10-20 JP JP61248754A patent/JPH07114241B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63102370A (en) | 1988-05-07 |
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