JPH07112259B2 - Display device - Google Patents
Display deviceInfo
- Publication number
- JPH07112259B2 JPH07112259B2 JP61227362A JP22736286A JPH07112259B2 JP H07112259 B2 JPH07112259 B2 JP H07112259B2 JP 61227362 A JP61227362 A JP 61227362A JP 22736286 A JP22736286 A JP 22736286A JP H07112259 B2 JPH07112259 B2 JP H07112259B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- liquid crystal
- elements
- display device
- supplied
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えば液晶表示素子を用いるデイスプレイ装
置に関する。The present invention relates to a display device using a liquid crystal display device, for example.
〔発明の概要〕 本発明はデイスプレイ装置に関し、相補型の素子を用い
て選択素子を形成することにより、信号選択の駆動信号
のレベルを小さくして装置の信頼性を向上させるように
するものである。[Summary of the Invention] The present invention relates to a display device, and by forming a selection element using complementary elements, the level of a drive signal for signal selection is reduced to improve the reliability of the apparatus. is there.
例えば液晶表示素子を用いたアクテイブマトリクス型の
デイスプレイ装置が種々提案されている。すなわち第５
図はその一例の要部の構成を示し、例えば画像データ信
号が１画素期間ごとに順次供給される水平画素数分のデ
ータ信号線Djと、１水平期間ごとに順次駆動パルス信号
が供給される走査線数分のアドレス信号線Aiとが直交し
て設けられ、これらの各交点にゲートがアドレス信号線
Aiに接続されたMOS選択素子Mijが設けられ、データ信号
線DjがこのMOS素子Mijのソースドレインを介して液晶表
示素子Cijの一端に接続される。なお液晶素子Cijの他端
は共通のターゲツト端子Ｔに接続される。For example, various active matrix type display devices using a liquid crystal display element have been proposed. That is, the fifth
The figure shows the configuration of the main part of the example. For example, the data signal lines Dj for the number of horizontal pixels to which the image data signal is sequentially supplied for each pixel period, and the driving pulse signals are sequentially supplied for each horizontal period. Address signal lines Ai corresponding to the number of scanning lines are provided orthogonally, and a gate is provided at each intersection of these address signal lines.
A MOS selection element Mij connected to Ai is provided, and the data signal line Dj is connected to one end of the liquid crystal display element Cij via the source / drain of the MOS element Mij. The other end of the liquid crystal element Cij is connected to a common target terminal T.
従つてこの装置において、任意のアドレス信号線Aiに駆
動（パルス）信号が供給されると、この信号線にゲート
の接続された選択素子Mijが導通され、データ信号線Dj
に順次供給される画像データが順次液晶素子Cijに供給
される。これによつていわゆる面走査された画像データ
がマトリツクス状に配された液晶素子Cijにて表示され
る。Therefore, in this device, when a drive (pulse) signal is supplied to an arbitrary address signal line Ai, the selection element Mij whose gate is connected to this signal line becomes conductive, and the data signal line Dj
The image data sequentially supplied to the liquid crystal element Cij are sequentially supplied to the liquid crystal element Cij. As a result, so-called surface-scanned image data is displayed on the liquid crystal elements Cij arranged in a matrix.
ところでこの装置において、例えば液晶表示素子を駆動
する場合には、液晶の劣化等を防止する目的でいわゆる
交流駆動が行われる。すなわち第６図に示すように、例
えば１フイールド毎にデータ信号線Djに供給されるデー
タ信号がターゲツト端子Ｔの電位VTに対して反転され
る。By the way, in this apparatus, for example, when driving a liquid crystal display element, so-called AC driving is performed for the purpose of preventing deterioration of the liquid crystal. That is, as shown in FIG. 6, for example, the data signal supplied to the data signal line Dj is inverted with respect to the potential V T of the target terminal T every one field, for example.
ところがその場合に、MOS素子Mijのゲートに供給される
駆動信号は、遮断時にデータ信号の最低電位VS1より低
く、導通時にデータ信号の最高電位VS2からさらに素子
のスレシヨルド電圧Vth分以上高いレベルが必要とされ
る。従つてこの駆動信号の振幅は |VS2−VS1|＋Vth となり、この信号の供給されるMOS素子Mijのゲート耐圧
を極めて大きくする必要があつた。またそれによつて装
置の信頼性が低下されてしまつていた。However, in that case, the drive signal supplied to the gate of the MOS element Mij is lower than the lowest potential V S1 of the data signal at the time of interruption and higher than the highest potential V S2 of the data signal at the time of conduction by more than the threshold voltage Vth of the element. Is required. Therefore, the amplitude of this drive signal becomes | V S2 −V S1 | + Vth, and the gate breakdown voltage of the MOS element Mij to which this signal is supplied needs to be made extremely large. Moreover, the reliability of the device has been deteriorated thereby.
さらに大レベルの駆動信号が用いられるためにいわゆる
クロツクノイズによるラデイエーシヨンの増加を生じ易
い。Further, since a large level drive signal is used, so-called clock noise easily causes an increase in radiation.
またMOS素子の遮断時のフイードスルーノイズによる信
号の保持電位の低下が生じやすいためにダイナミツクレ
ンジの低下やそれによる画像のコントラストの不足等の
おそれがあつた。Further, since the holding potential of the signal is likely to decrease due to the feedthrough noise when the MOS element is cut off, there is a possibility that the dynamic range is decreased and the contrast of the image is insufficient.
以上述べたように従来の技術では、大レベルの駆動信号
を用いるために、信頼性の低下やラデイエーシヨンの増
加、ダイナミツクレンジの低下を生じやすいなどの問題
点があつた。As described above, in the conventional technique, since a high level drive signal is used, there are problems that the reliability is decreased, the radiation is increased, and the dynamic range is decreased.
本発明は、垂直方向に延長されかつ平行に配設された複
数の第１の信号線Diと、水平方向に延長されかつ平行に
配設された複数の第２の信号線Aiとが設けられ、これら
の第1,第２の信号線の各交点にそれぞれ選択素子Mijを
介して画素電極Cijが設けられてなるデイスプレイ装置
において、上記選択素子がそれぞれ１対の相補型の素子
NMij,PMijで形成されると共に、これらがそれぞれ逆極
性の駆動信号（Ai,▲▼）で駆動されるようにした
ことを特徴とするデイスプレイ装置である。According to the present invention, a plurality of first signal lines Di extending in the vertical direction and arranged in parallel and a plurality of second signal lines Ai extending in the horizontal direction and arranged in parallel are provided. In a display device in which pixel electrodes Cij are provided at respective intersections of these first and second signal lines via selection elements Mij, the selection elements are each a pair of complementary elements.
The display device is characterized in that it is formed of NMij and PMij and that they are respectively driven by drive signals (Ai, ▲ ▼) of opposite polarities.
これによれば、相補型の素子を用いて、入力信号の高電
位期間と低電位期間とがそれぞれ異なる型式の素子を通
じて選択されるようにしたことによつて、これらの素子
に供給される駆動信号のレベルを入力信号の振幅に等し
い大きさまで低減することができる。According to this, since the high potential period and the low potential period of the input signal are selected through the elements of different types by using the complementary elements, the drive supplied to these elements is selected. The level of the signal can be reduced to a magnitude equal to the amplitude of the input signal.
第１図は配線図を示す。この図において、アドレス信号
線Aiが２本（Ai,▲▼）ずつ設けられると共に、MOS
選択素子MijがＮ型素子NijとＰ型素子PMijとの相補型の
素子で構成され、これらの素子NMijとPMijのゲートがそ
れぞれ信号線Aiと▲▼とに接続される。そしてこれ
らの素子NMijとPMijとのソースドレイン間を通じてデー
タ信号線Djと液晶表示素子Cijの一端とが接続される。
さらに液晶素子Cijの他端は共通のターゲツト端子Ｔに
接続される。FIG. 1 shows a wiring diagram. In this figure, two address signal lines Ai (Ai, ▲ ▼) are provided, and
The selection element Mij is composed of complementary elements of the N-type element Nij and the P-type element PMij, and the gates of these elements NMij and PMij are connected to the signal lines Ai and ▲ ▼, respectively. The data signal line Dj and one end of the liquid crystal display element Cij are connected through the source and drain of these elements NMij and PMij.
Further, the other end of the liquid crystal element Cij is connected to a common target terminal T.
そしてこの装置において、データ信号線Djに第２図Ａに
示すような信号が供給されていた場合に、アドレス信号
線Ai,▲▼には同図B,Cに示すような互いに逆極性の
駆動信号を供給して、素子NMijとPMijとがそれぞれのパ
ルス期間に導通されるようにする。In this device, when the data signal line Dj is supplied with a signal as shown in FIG. 2A, the address signal lines Ai and ▲ ▼ are driven with opposite polarities as shown in FIGS. A signal is provided to cause the elements NMij and PMij to conduct during their respective pulse periods.
従つてこの装置において、入力信号が各駆動信号のパル
ス期間に素子NMijとPMijとを通じて液晶素子Cijに供給
されると共に、入力信号の高電位期間にはＰ型素子PMij
が充分に導通し、低電位期間にはＮ型素子NMijが充分に
導通するので、それぞれの駆動信号の振幅を入力信号の
振幅 |VS2−VS1| に等しくすることができる。Therefore, in this device, the input signal is supplied to the liquid crystal element Cij through the elements NMij and PMij during the pulse period of each drive signal, and the P-type element PMij is supplied during the high potential period of the input signal.
Is sufficiently conductive, and the N-type element NMij is sufficiently conductive in the low potential period, so that the amplitude of each drive signal can be made equal to the amplitude | V S2 −V S1 | of the input signal.
また上述の装置において、入力信号の高電位期間（フイ
ールド）はＰ型素子PMij、低電位期間はＮ型素子NMijの
みが導通すればよいので、各アドレス信号線Aiと▲
▼の駆動信号は波形図のDEに示すようにフイールド毎に
交互に供給するようにしてもよい。さらにこの場合に、
各駆動信号の波高レベルは図中に示すように、入力信号
の高電位期間のペデスタルレベルをVS′２、低電位期間
のペデスタルレベルをVS′１、Ｐ型素子PMijのスレシヨ
ルド電圧をVthP、Ｎ型素子NMijのスレシヨルド電圧をV
thNとして、それぞれ VS′２−VthP Vs′１＋VthN とすることもできる。Further, in the above-described device, only the P-type element PMij is required to conduct during the high potential period (field) of the input signal, and only the N-type element NMij is required to conduct during the low potential period.
The drive signal of ▼ may be alternately supplied for each field as indicated by DE in the waveform diagram. Further in this case,
The peak level of each drive signal is, as shown in the figure, the pedestal level during the high potential period of the input signal is V S ′ 2 , the pedestal level during the low potential period is V S ′ 1 , and the threshold voltage of the P-type element PMij is V S ′. thP , N-type element NMij threshold voltage is V
The thN may be V S ′ 2 −V thP V s ′ 1 + V thN .
こうして表示が行われるわけであるが、上述の装置によ
れば駆動信号のレベルを小さくすることができるので、
各選択素子のゲート耐圧を大きくする必要がなく、装置
の信頼性が向上する。Although the display is performed in this manner, the above-mentioned device can reduce the level of the drive signal.
It is not necessary to increase the gate breakdown voltage of each selection element, and the reliability of the device is improved.
またクロツクノイズによるラデイエーシヨンの発生が低
減され、特に波形図のB,Cの信号を用いた場合には駆動
信号同士が相殺されるので、ラデイエーシヨンを略零に
することができる。Further, the generation of radiation due to clock noise is reduced, and particularly when signals B and C in the waveform diagram are used, the drive signals cancel each other out, so that the radiation can be made substantially zero.
さらに第３図は具体的な回路パターンの構成例を示し、
図においてＰ型素子PMijとＮ型素子NMijがそれぞれデー
タ信号線Djと液晶表示素子Cijを構成する透明電極との
間に設けられると共に、これらの素子PMijとNMijの中央
部に透明電極の上下に設けられたアドレス信号線Aiと▲
▼の延長部がそれぞれ設けられてゲートが形成され
る。Further, FIG. 3 shows an example of a concrete circuit pattern configuration,
In the figure, a P-type element PMij and an N-type element NMij are provided between the data signal line Dj and a transparent electrode which constitutes the liquid crystal display element Cij, respectively. Address signal line Ai and ▲ provided
Each of the extended portions of ▼ is provided to form a gate.
従つてこの構成によれば、隣接するアドレス信号線間で
逆極性の駆動信号が流されるので、各透明電極へのクロ
ツクノイズの飛込みが中和され、ダイナミツクレンジの
低下が防止される。Therefore, according to this configuration, since driving signals of opposite polarities are flown between the adjacent address signal lines, the jumping of clock noise into each transparent electrode is neutralized, and the reduction of the dynamic range is prevented.
なお第４図は選択素子の構成の他の例を示すものであつ
て、Ａはいわゆるダブルゲートとした場合で、特にデー
タ信号線Djと液晶表示素子Cij間の電荷の漏洩を低減さ
せることができる。またＢはダブルゲートの中点を互に
接続したものであつて、上述と同様に漏洩が低減される
と共に、特に製造工程中のラビング処理等による静電気
の発生に対する強度を向上させることができる。Note that FIG. 4 shows another example of the configuration of the selection element, where A is a so-called double gate, and in particular, leakage of charges between the data signal line Dj and the liquid crystal display element Cij can be reduced. it can. In addition, B is a structure in which the middle points of the double gate are connected to each other, and the leakage is reduced as described above, and in particular, the strength against the generation of static electricity due to the rubbing treatment during the manufacturing process can be improved.
なお、この装置はポリシリコン，アモルフアスシリコ
ン，クリスタルシリコン等の全てのMOS素子を用いた装
置に適用できる。This device can be applied to devices using all MOS elements such as polysilicon, amorphous silicon, and crystal silicon.
この発明によれば、相補型の素子を用いて、入力信号の
高電位期間と低電位期間とがそれぞれ異なる型式の素子
を通じて選択されるようにしたことによつて、これらの
素子に供給される駆動信号のレベルを入力信号の振幅に
等しい大きさまで低減することができるようになつた。According to the present invention, by using complementary elements, the high potential period and the low potential period of the input signal are selected through the elements of different types, so that these elements are supplied. It has become possible to reduce the level of the drive signal to a magnitude equal to the amplitude of the input signal.
第１図は本発明の一例の配線図、第２図〜第４図はその
説明のための図、第５図，第６図は従来の装置の説明の
ための図である。 Djはデータ信号線、Aiはアドレス信号線、NMijはＮ型素
子、PMijはＰ型素子、Cijは液晶表示素子、Ｔはターゲ
ツト端子である。FIG. 1 is a wiring diagram of an example of the present invention, FIGS. 2 to 4 are diagrams for explaining the same, and FIGS. 5 and 6 are diagrams for explaining a conventional device. Dj is a data signal line, Ai is an address signal line, NMij is an N-type element, PMij is a P-type element, Cij is a liquid crystal display element, and T is a target terminal.
Claims (1)
複数の第１の信号線と、水平方向に延長されかつ平行に
配設された複数の第２の信号線とが設けられ、これらの
第1,第２の信号線の各交点にそれぞれ選択素子を介して
画素電極が設けられてなるデイスプレイ装置において、 上記選択素子がそれぞれ１対の相補型の素子で形成され
ると共に、 これらがそれぞれ逆極性の駆動信号で駆動されるように
したことを特徴とするデイスプレイ装置。1. A plurality of first signal lines extending vertically and arranged in parallel, and a plurality of second signal lines extending horizontally and arranged in parallel are provided. In a display device in which a pixel electrode is provided at each intersection of these first and second signal lines via a selection element, the selection element is formed of a pair of complementary elements, respectively. The display device is characterized in that each is driven by a drive signal of opposite polarity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61227362A JPH07112259B2 (en) | 1986-09-26 | 1986-09-26 | Display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61227362A JPH07112259B2 (en) | 1986-09-26 | 1986-09-26 | Display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6382177A JPS6382177A (en) | 1988-04-12 |
| JPH07112259B2 true JPH07112259B2 (en) | 1995-11-29 |
Family
ID=16859608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61227362A Expired - Fee Related JPH07112259B2 (en) | 1986-09-26 | 1986-09-26 | Display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07112259B2 (en) |
Families Citing this family (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69112698T2 (en) * | 1990-05-07 | 1996-02-15 | Fujitsu Ltd | High quality display device with active matrix. |
| EP0486284A3 (en) * | 1990-11-13 | 1993-09-01 | Sel Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US6893906B2 (en) | 1990-11-26 | 2005-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| US7154147B1 (en) | 1990-11-26 | 2006-12-26 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and driving method for the same |
| KR950001360B1 (en) * | 1990-11-26 | 1995-02-17 | 가부시키가이샤 한도오따이 에네루기 겐큐쇼 | Electric optical device and driving method thereof |
| TW209895B (en) | 1990-11-26 | 1993-07-21 | Semiconductor Energy Res Co Ltd | |
| JP2979655B2 (en) * | 1991-01-14 | 1999-11-15 | 松下電器産業株式会社 | Driving method of active matrix substrate |
| EP0499979A3 (en) | 1991-02-16 | 1993-06-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device |
| JP2794499B2 (en) * | 1991-03-26 | 1998-09-03 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
| US6975296B1 (en) | 1991-06-14 | 2005-12-13 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| US6778231B1 (en) | 1991-06-14 | 2004-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical display device |
| US5414442A (en) * | 1991-06-14 | 1995-05-09 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method of driving the same |
| JP2651972B2 (en) | 1992-03-04 | 1997-09-10 | 株式会社半導体エネルギー研究所 | Liquid crystal electro-optical device |
| JP3520417B2 (en) | 2000-12-14 | 2004-04-19 | セイコーエプソン株式会社 | Electro-optical panels and electronics |
| JP2009198981A (en) * | 2008-02-25 | 2009-09-03 | Seiko Epson Corp | Driving circuit of electrooptical device, driving method of electrooptical device, electrooptical device and electronic apparatus |
-
1986
- 1986-09-26 JP JP61227362A patent/JPH07112259B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6382177A (en) | 1988-04-12 |
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