JPH07107127A - Fsk demodulator - Google Patents
Fsk demodulatorInfo
- Publication number
- JPH07107127A JPH07107127A JP24784493A JP24784493A JPH07107127A JP H07107127 A JPH07107127 A JP H07107127A JP 24784493 A JP24784493 A JP 24784493A JP 24784493 A JP24784493 A JP 24784493A JP H07107127 A JPH07107127 A JP H07107127A
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- signal
- circuit
- phase signal
- phase
- quadrature
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主として無線通信の受
信機に用いられる直接変換方式のＦＳＫ復調器に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct conversion type FSK demodulator mainly used in a receiver for wireless communication.
【０００２】[0002]
【従来の技術】最近、無線周波搬送波上の周波数偏移変
調（フリケンシー・シフト・キーイング：ＦＳＫ）信号
を用いた直接変換受信機が集積回路化に適した受信機の
構成として検討されている。2. Description of the Related Art Recently, a direct conversion receiver using a frequency shift keying (FSK) signal on a radio frequency carrier has been studied as a receiver structure suitable for integration into an integrated circuit.
【０００３】例えば特開昭５５−１４７０１号公報に記
載されている構成が知られている。以下、図１２を参照
して従来の直接変換方式のＦＳＫ受信機について説明す
る。図１２において、１はＦＳＫ信号、１Ａはアンテ
ナ、１Ｂはアンプ、２、３はミキサ、４はローパスフィ
ルタ、５は９０度移相器、６は局部発振器、７はリッミ
タアンプ、８はＤフリップフロップ、９は復調出力であ
る。For example, the configuration described in Japanese Patent Laid-Open No. 55-14701 is known. Hereinafter, a conventional direct conversion FSK receiver will be described with reference to FIG. In FIG. 12, 1 is an FSK signal, 1A is an antenna, 1B is an amplifier, 2 is a mixer, 4 is a low-pass filter, 5 is a 90-degree phase shifter, 6 is a local oscillator, 7 is a limiter amplifier, and 8 is a D flip-flop. , 9 are demodulation outputs.
【０００４】以上のように構成されたＦＳＫ復調器につ
いて、以下その動作について説明する。アンテナ１Ａを
介して入力されたＦＳＫ信号１はアンプ１Ｂを介してそ
れぞれミキサ２、３に供給される。局部発振器５の信号
は２分配され、第１の信号は９０度移相器を通してミキ
サ２に、第２の信号は直接ミキサ３に供給され、それぞ
れＦＳＫ信号１と混合することにより、入力信号をダウ
ンコンバートし、ベースバンド信号のみを通過するロー
パスフィルタ３によって、互いに９０度位相の異なる同
位相信号（Ｉ）と直交位相信号（Ｑ）を得る。Ｉ信号と
Ｑ信号は、それぞれリミッタアンプ７により２値化され
る。そして、ＤフリップフロップのＤ入力にＩ信号、ク
ロック入力にＱ信号を入力し、Ｄフリップフロップの出
力信号を用いてデータの復調を行う。The operation of the FSK demodulator configured as described above will be described below. The FSK signal 1 input via the antenna 1A is supplied to the mixers 2 and 3 via the amplifier 1B, respectively. The signal of the local oscillator 5 is divided into two, the first signal is supplied to the mixer 2 through the 90-degree phase shifter, the second signal is directly supplied to the mixer 3, and the input signal is mixed with the FSK signal 1 respectively. The in-phase signal (I) and the quadrature-phase signal (Q) which are 90 degrees out of phase with each other are obtained by the low-pass filter 3 which is down-converted and passes only the baseband signal. The I signal and the Q signal are binarized by the limiter amplifier 7. Then, the I signal is input to the D input of the D flip-flop and the Q signal is input to the clock input, and the data is demodulated using the output signal of the D flip-flop.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記従
来のＦＳＫ復調器では、データレートの高速化などによ
り、周波数偏移とデータレートの比に１／２をかけた値
で表される変調指数が小さくなると復調精度が劣化す
る。また、局部発振器の発振周波数が搬送波周波数から
ずれるほど復調器の受信感度が劣化するという課題を有
していた。However, in the above-mentioned conventional FSK demodulator, the modulation index represented by the value obtained by multiplying the ratio of the frequency deviation and the data rate by 1/2 is used due to the increase in the data rate. When it becomes smaller, the demodulation accuracy deteriorates. Further, there is a problem that the reception sensitivity of the demodulator deteriorates as the oscillation frequency of the local oscillator deviates from the carrier frequency.
【０００６】本発明は、上記従来の課題を解決するもの
で、変調指数の低下にともなう復調精度の劣化と、局部
発振器の周波数ずれにともなう受信感度の劣化の度合い
を減少させるＦＳＫ復調器を提供することを目的とする
ものである。The present invention solves the above-mentioned conventional problems, and provides an FSK demodulator that reduces the degree of deterioration in demodulation accuracy due to a decrease in modulation index and the degree of deterioration in reception sensitivity due to a frequency shift of a local oscillator. The purpose is to do.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に、本発明のＦＳＫ復調器は、同位相信号を２値化する
第１のリミッタアンプと、直交位相信号を２値化する第
２のリミッタアンプと、前記第１、第２のリミッタアン
プの出力信号の排他的論理和をとる排他的論理和回路か
らなる倍周直交位相信号発生回路と、前記同位相信号及
び前記直交位相信号から、前記倍周直交位相信号発生回
路の出力信号と同じ周波数で、かつ、直交関係にあり、
送信データによっては出力信号が変化しない信号を出力
する倍周同位相信号発生回路と、前記倍周直交位相信号
発生回路と前記倍周同位相信号発生回路の出力信号から
復調信号を得る復調回路とを有するものである。In order to achieve the above object, an FSK demodulator of the present invention comprises a first limiter amplifier for binarizing an in-phase signal and a second limiter amplifier for binarizing a quadrature-phase signal. From the in-phase signal and the quadrature-phase signal, and a limiter amplifier and a frequency-divided quadrature-phase signal generation circuit including an exclusive-OR circuit that takes an exclusive-OR of output signals of the first and second limiter amplifiers. , At the same frequency as the output signal of the frequency quadrature quadrature signal generation circuit, and in a quadrature relationship,
A frequency-divided in-phase signal generation circuit that outputs a signal whose output signal does not change depending on transmission data; and a demodulation circuit that obtains a demodulated signal from the output signals of the frequency-doubled quadrature phase signal generation circuit and the frequency-divided in-phase signal generation circuit. Is to have.
【０００８】[0008]
【作用】本発明は、２つの直交信号を２値化し、排他的
論理和演算を行うことにより、周波数が２倍で、送信デ
ータにより位相の遅れ進みの状態が反転する信号、つま
り、Ｑ信号を２逓倍したとみなせる倍周直交位相信号を
得るとともに、一方、倍周直交位相信号と同じ周波数を
有し、送信データにより位相の遅れ進みの状態が変わら
ない、Ｉ信号を２逓倍したとみなせる倍周同位相信号を
得ることにより、直交関係を有する倍周直交位相信号と
倍周同位相信号から復調信号を得ることで、周波数偏移
を２倍にした復調結果と同様の効果があり、変調指数は
等価的に２倍とみなせ、復調精度が向上する。また、変
調指数が等価的に２倍になることで局部発振器の周波数
ずれによる受信感度の劣化を減少させることができる。According to the present invention, two orthogonal signals are binarized and an exclusive OR operation is performed, so that the frequency is doubled and the phase lag / lead state is inverted by the transmission data, that is, the Q signal. Is obtained as a doubled quadrature phase signal, and on the other hand, it can be regarded as a doubled I signal which has the same frequency as the doubled quadrature phase signal and in which the state of the phase delay or advance does not change due to the transmission data. By obtaining the demodulated signal from the doubled quadrature signal and the doubled in-phase signal having the quadrature relationship by obtaining the doubled in-phase signal, there is the same effect as the demodulation result in which the frequency shift is doubled. The modulation index can be equivalently regarded as double, and the demodulation accuracy is improved. Further, since the modulation index is equivalently doubled, it is possible to reduce the deterioration of the reception sensitivity due to the frequency shift of the local oscillator.
【０００９】[0009]
【実施例】（実施例１）以下、本発明の第１の実施例に
ついて、図１を参照しながら説明する。図１において、
１０１はアンテナや増幅器（図示せず）を介して入力し
たＦＳＫ信号の入力端子、１０２はミキサ、１０３はロ
ーパスフィルタ、１０８は９０度移相器、１０９は局部
発振器で、以上は図１２で示した構成と同様のものであ
る。１１１は倍周直交位相発生回路で、おのおのローパ
スフィルタ１０３Ａ、１０３Ｂの出力を制限増幅するこ
とで２値化するリミッタアンプ１０４Ａ，１０４Ｂ、そ
のリミッタアンプ１０４Ａ，１０４Ｂの排他的論理和を
求める排他的論理和回路１０５により構成されている。
１１０は後述する倍周同位相発生回路、１０６は復調回
路、１０７は復調回路出力である。(Embodiment 1) Hereinafter, a first embodiment of the present invention will be described with reference to FIG. In FIG.
Reference numeral 101 is an input terminal for an FSK signal input through an antenna or an amplifier (not shown), 102 is a mixer, 103 is a low-pass filter, 108 is a 90-degree phase shifter, 109 is a local oscillator, and the above is shown in FIG. It is similar to the configuration described above. Reference numeral 111 denotes a frequency-multiplied quadrature phase generation circuit, which is a limiter amplifier 104A, 104B that binarizes each output of the low-pass filters 103A, 103B by limiting amplification, and an exclusive logic for obtaining an exclusive OR of the limiter amplifiers 104A, 104B. It is composed of a summing circuit 105.
Reference numeral 110 is a frequency-doubled in-phase generation circuit described later, 106 is a demodulation circuit, and 107 is an output of the demodulation circuit.
【００１０】以上のように構成されたＦＳＫ復調器につ
いて、以下その動作を説明する。まず、ＦＳＫ信号入力
端子１０１に入力されたＦＳＫ信号は直交ミキサ１０２
とローパスフィルタ１０３によって、互いに９０度位相
の異なる同位相信号（Ｉ）と直交位相信号（Ｑ）に変換
される。倍周直交位相信号発生回路１１１は、Ｉ信号と
Ｑ信号を入力とし、それぞれの信号をリミッタアンプ１
０４により２値化し、それらの排他的論理和１０５をと
ることにより、Ｑ信号を２逓倍したとみなせる倍周直交
位相信号（Ｑ２）が発生する。The operation of the FSK demodulator configured as described above will be described below. First, the FSK signal input to the FSK signal input terminal 101 is input to the quadrature mixer 102.
And the low-pass filter 103 convert them into an in-phase signal (I) and a quadrature-phase signal (Q) which are 90 degrees out of phase with each other. The double quadrature quadrature signal generation circuit 111 receives the I signal and the Q signal as input, and outputs the respective signals to the limiter amplifier 1.
By binarizing by 04 and taking the exclusive OR 105 of them, the frequency-divided quadrature phase signal (Q2) which can be regarded as being doubled is generated.
【００１１】図２は倍周直交位相信号発生回路１１１の
各部の波形である。図２（ａ）、（ｂ）に示すように、
送信データがスペースの時とマークの時が生じる。そし
てその送信データによってＱ信号の位相は１８０度ずれ
る。このようなＱ信号の位相変化により、Ｑ２信号の位
相も１８０度ずれるため、Ｑ２信号は送信データによっ
て位相の遅れ進みが生じる。FIG. 2 shows the waveform of each part of the frequency-doubled quadrature phase signal generation circuit 111. As shown in FIGS. 2A and 2B,
There are times when the transmitted data is space and times when it is marked. Then, the phase of the Q signal is shifted by 180 degrees due to the transmitted data. Due to such a phase change of the Q signal, the phase of the Q2 signal is also shifted by 180 degrees, so that the Q2 signal is delayed in phase due to the transmission data.
【００１２】一方、倍周同位相信号発生回路１１０は、
Ｉ信号及びＱ信号から、倍周直交位相信号発生回路１１
１の出力信号Ｑ２と同じ周波数で、かつ、直交関係にあ
り、送信データによっては出力信号が変化しない２逓倍
したＩ信号とみなせる倍周同位相信号（Ｉ２）を出力す
る回路である。これら直交関係をもつＩ２信号とＱ２信
号を復調回路１０６の入力信号とすることによって、等
価的に変調指数は２倍になり、復調回路１０６は送信デ
ータに応じて、Ｉ２信号とＱ２信号間の位相の遅れ進み
を判定することによって、出力信号を得ることができ
る。On the other hand, the frequency-divided in-phase signal generation circuit 110 is
Frequency-doubled quadrature phase signal generation circuit 11 based on I and Q signals
This is a circuit that outputs a frequency-divided in-phase signal (I2) that has the same frequency as the output signal Q2 of 1 and has an orthogonal relationship and that can be regarded as a doubled I signal in which the output signal does not change depending on the transmission data. By using the I2 signal and the Q2 signal having these orthogonal relations as the input signals of the demodulation circuit 106, the modulation index is equivalently doubled, and the demodulation circuit 106 is between the I2 signal and the Q2 signal according to the transmission data. An output signal can be obtained by determining the phase delay.
【００１３】以上のように、本実施例によれば、Ｉ信号
とＱ信号を２逓倍したとみなせる信号を復調回路１０６
に入力するため、変調指数は等価的に倍になり、復調精
度を向上し、局部発振器１０９の周波数ずれによる受信
感度の劣化の度合いを減少できる。As described above, according to this embodiment, a signal which can be regarded as a signal obtained by multiplying the I signal and the Q signal by 2 is demodulated.
, The modulation index is equivalently doubled, the demodulation accuracy is improved, and the degree of deterioration of the reception sensitivity due to the frequency shift of the local oscillator 109 can be reduced.
【００１４】（実施例２）次に、本発明の第２の実施例
について図３を参照しながら説明する。図３は倍周同位
相信号発生回路１１０の、より具体的な構成を示すもの
である。図３において、３０１はＩ信号入力端子、３０
２はＱ信号入力端子、３０３はそれぞれの端子３０１、
３０２に入力されたＩ、Ｑ信号を加算する加算回路、一
方、３０４はそれぞれの端子３０１、３０２に入力され
たＩ、Ｑ信号の一方から他方を減算する減算回路、３０
５は図１の１０４と同様なリミッタアンプ、３０６は排
他的論理和回路である。(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 shows a more specific configuration of the frequency doubled in-phase signal generation circuit 110. In FIG. 3, 301 is an I signal input terminal, 30
2 is a Q signal input terminal, 303 is each terminal 301,
An adder circuit for adding I and Q signals input to 302, on the other hand, a subtraction circuit 304 for subtracting the other from one of the I and Q signals input to the respective terminals 301 and 302, 30
Reference numeral 5 is a limiter amplifier similar to 104 in FIG. 1, and 306 is an exclusive OR circuit.
【００１５】以上のように構成された倍周同位相信号発
生回路１１０ａについて、以下その動作を説明する。The operation of the frequency-doubled in-phase signal generation circuit 110a configured as described above will be described below.
【００１６】図４は倍周同位相信号発生回路１１０ａに
おける各部の波形である（なお、同図（ａ）、（ｂ）に
示すように、送信データがスペースの時とマークの時が
生じる）。Ｉ信号とＱ信号は加算回路３０１と減算回路
３０２にそれぞれ入力され、Ｉ信号に対し±４５度位相
が異なる信号ｃ，ｄがつくられる。これらの信号ｃ，ｄ
をリッミタアンプ３０５によって、２値化したものが信
号ｅ，ｆであり、それらの排他的論理和回路３０６によ
り排他的論理和を得ることによってＱ２信号と同じ周波
数で直交関係を有し、かつ、送信データによっては出力
信号が変化しないＩ２信号が発生する。FIG. 4 shows waveforms at various parts in the frequency-doubled in-phase signal generation circuit 110a (note that, as shown in FIGS. 4A and 4B, the transmission data is a space and a mark is generated). . The I signal and the Q signal are input to the adding circuit 301 and the subtracting circuit 302, respectively, and signals c and d having a phase difference of ± 45 degrees with respect to the I signal are generated. These signals c, d
The signals e and f are binarized by the limiter amplifier 305, and an exclusive OR is obtained by the exclusive OR circuit 306 of them to have an orthogonal relationship at the same frequency as the Q2 signal, and the signal is transmitted. An I2 signal whose output signal does not change is generated depending on the data.
【００１７】以上のように、本実施例によれば、加算回
路３０３と減算回路３０４により、Ｉ信号を±４５度ず
らした信号を発生させ、それらの信号をリッミタアンプ
３０５により２値化し、排他的論理和回路３０６で排他
的論理和を得ることにより、Ｉ２信号をつくることがで
きる。As described above, according to this embodiment, the adder circuit 303 and the subtractor circuit 304 generate signals with the I signal shifted by ± 45 degrees, and binarize these signals by the limiter amplifier 305 to exclusively generate them. The I2 signal can be generated by obtaining an exclusive OR with the OR circuit 306.
【００１８】なお、本実施例において、加算回路３０３
をＩ信号を４５度移相する回路に、減算回路３０４をＩ
信号を−４５度移相する回路に置き換えることによって
も、同様な波形が得られ、Ｉ２信号をつくることができ
る。また、この場合、Ｉ信号の代わりにＱ信号を用いて
も同様な出力が得られる。In this embodiment, the adder circuit 303
To the circuit that shifts the I signal by 45 degrees and the subtraction circuit 304
By replacing the signal with a circuit that shifts the phase by -45 degrees, a similar waveform is obtained and the I2 signal can be generated. Further, in this case, a similar output can be obtained by using the Q signal instead of the I signal.
【００１９】（実施例３）次に、本発明の第３の実施例
について図５を参照しながら説明する。図５は図３に示
した倍周同位相信号発生回路とは別な構成を示したもの
である。図５において、５０１はＩ信号入力端子、５０
２はＱ信号入力端子、５０３、５０４は入力されたＩ，
Ｑ信号の一方の電圧値を他方の電圧値と比較する電圧比
較器、５０５は入力信号の符号を反転させる反転回路、
５０６は電圧比較器５０３及び５０４の比較結果である
出力の排他的論理和を求める排他的論理和回路である。(Embodiment 3) Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 5 shows a configuration different from that of the frequency doubled in-phase signal generation circuit shown in FIG. In FIG. 5, 501 is an I signal input terminal, and 50
2 is a Q signal input terminal, 503 and 504 are input I,
A voltage comparator that compares one voltage value of the Q signal with the other voltage value, 505 an inverting circuit that inverts the sign of the input signal,
An exclusive-OR circuit 506 obtains an exclusive-OR of outputs which are comparison results of the voltage comparators 503 and 504.
【００２０】以上のように構成された倍周同位相信号発
生回路１１０ｂについて、以下その動作を説明する。図
６は倍周同位相信号発生回路１１０ｂにおける各部の波
形である（なお、同図（ａ）、（ｂ）に示すように、送
信データがスペースの時とマークの時が生じる）。Ｉ信
号とＱ信号は分配され２つの電圧比較器５０３、５０４
に入力されるが、そのうち一方の電圧比較器５０４には
反転回路５０５により、Ｉ信号の符号を反転した信号ｈ
が入力される。電圧比較器５０３、５０４は基準電圧に
対し、参照電圧が高いときハイレベル、低いときローレ
ベルを出力する。この場合、Ｉ信号が参照電圧、Ｑ信号
が基準電圧であっても、また、その逆であっても良い。
各電圧比較器出力信号ｇ，ｉの排他的論理和をとった出
力信号はＱ２信号と同じ周波数で直交関係を有し、か
つ、送信データによっては出力信号が変化しないＩ２信
号となる。The operation of the frequency doubled in-phase signal generation circuit 110b configured as described above will be described below. FIG. 6 shows the waveform of each part in the frequency-doubled in-phase signal generation circuit 110b (note that, as shown in (a) and (b) of the figure, there are times when the transmission data is a space and times when it is a mark). The I signal and the Q signal are distributed and divided into two voltage comparators 503 and 504.
The voltage h is obtained by inverting the sign of the I signal by the inverting circuit 505 in one of the voltage comparators 504.
Is entered. The voltage comparators 503 and 504 output a high level when the reference voltage is high and a low level when the reference voltage is low, with respect to the reference voltage. In this case, the I signal may be the reference voltage and the Q signal may be the reference voltage, or vice versa.
The output signal obtained by taking the exclusive OR of the voltage comparator output signals g and i has an orthogonal relationship at the same frequency as the Q2 signal, and becomes an I2 signal that does not change depending on the transmission data.
【００２１】以上のように、本実施例によれば、電圧比
較器と、反転回路と、排他的論理和回路とを用いること
により、Ｑ２信号と同じ周波数で直交関係を有し、か
つ、送信データによっては出力信号が変化しないＩ２信
号をつくることができる。As described above, according to this embodiment, by using the voltage comparator, the inverting circuit, and the exclusive OR circuit, there is an orthogonal relationship at the same frequency as the Q2 signal and the transmission is performed. Depending on the data, it is possible to create an I2 signal whose output signal does not change.
【００２２】また、Ｉ信号入力端子５０１にＱ信号を、
一方、Ｑ信号入力端子５０２にＩ信号を入力としても同
様な出力信号を得ることができる。A Q signal is applied to the I signal input terminal 501,
On the other hand, even if the I signal is input to the Q signal input terminal 502, a similar output signal can be obtained.
【００２３】（実施例４）次に、本発明の第４の実施例
について図７を参照しながら説明する。図７は図１に示
した倍周同位相信号発生回路１１０の、さらに別な構成
を示したものである。図７において７０１はＩ信号入力
端子、７０２はＱ信号入力端子、７０３、７０４は絶対
値回路、７０５は電圧比較器である。(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 shows another configuration of the frequency-divided in-phase signal generation circuit 110 shown in FIG. In FIG. 7, 701 is an I signal input terminal, 702 is a Q signal input terminal, 703 and 704 are absolute value circuits, and 705 is a voltage comparator.
【００２４】以上のように構成された倍周同位相信号発
生回路について、以下その動作を説明する。図８は倍周
同位相信号発生回路における各部の波形である（なお、
同図（ａ）、（ｂ）に示すように、送信データがスペー
スの時とマークの時が生じる）。Ｉ信号とＱ信号は、信
号が負になる部分を反転することにより入力信号の絶対
値をとる絶対値回路７０３、７０４にそれぞれ入力され
る。各絶対値回路７０３、７０４の出力信号ｊ、ｋの電
圧を比較する電圧比較器７０５に送出することにより、
その出力信号は、Ｑ２信号と同じ周波数で直交関係を有
し、かつ、送信データによっては出力信号が変化しない
Ｉ２信号となる。この場合、波形ｊが電圧比較器の基準
電圧であっても、参照電圧であっても同様の出力が得ら
れる。The operation of the frequency doubled in-phase signal generation circuit configured as described above will be described below. FIG. 8 shows the waveform of each part in the frequency-doubled in-phase signal generation circuit (note that
As shown in (a) and (b) of the same drawing, there are times when the transmission data is a space and times when it is a mark). The I signal and the Q signal are input to absolute value circuits 703 and 704, respectively, which take the absolute value of the input signal by inverting the negative portion of the signal. By sending the output signals j and k of the absolute value circuits 703 and 704 to the voltage comparator 705 for comparing,
The output signal is an I2 signal that has the same frequency as that of the Q2 signal and has an orthogonal relationship, and the output signal does not change depending on the transmission data. In this case, the same output can be obtained regardless of whether the waveform j is the reference voltage or the reference voltage of the voltage comparator.
【００２５】以上のように、本実施例によれば、電圧比
較器と絶対値回路を用いることにより、Ｑ２信号と同じ
周波数で直交関係を有し、かつ、送信データによっては
出力信号が変化しないＩ２信号をつくることができる。As described above, according to the present embodiment, by using the voltage comparator and the absolute value circuit, the Q2 signal has the same frequency and the orthogonal relationship, and the output signal does not change depending on the transmission data. I2 signal can be generated.
【００２６】また、本実施例の絶対値回路７０３、７０
４を入力信号の自乗演算を行う自乗回路に置き換えて
も、同様な波形が得られ、Ｉ２信号をつくることができ
る。Also, the absolute value circuits 703 and 70 of this embodiment are provided.
Even if 4 is replaced with a squaring circuit that performs square calculation of the input signal, a similar waveform can be obtained and the I2 signal can be produced.
【００２７】（実施例５）次に、本発明の第５の実施例
について図９を参照しながら説明する。図９は自１に示
した倍周同位相信号発生回路１１０の、さらに別な構成
を示すものである。図９において、９０１はＩ信号入力
端子、９０２は絶対値回路、９０３は電圧比較器、９０
４は基準電圧入力端子である。(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 shows another configuration of the frequency-divided in-phase signal generation circuit 110 shown in FIG. In FIG. 9, 901 is an I signal input terminal, 902 is an absolute value circuit, 903 is a voltage comparator, 90
Reference numeral 4 is a reference voltage input terminal.
【００２８】以上のように構成された倍周同位相信号発
生回路１１０ｄについて、以下その動作を説明する。な
お、図９の倍周同位相信号発生回路の構成を用いる場
合、自動利得制御回路により、入力ＦＳＫ信号の最大電
圧値を常に一定にする。これにより、Ｉ信号の最大電圧
値も常に一定になる。The operation of the frequency-multiplied in-phase signal generation circuit 110d configured as described above will be described below. When the configuration of the frequency-doubled in-phase signal generation circuit of FIG. 9 is used, the maximum voltage value of the input FSK signal is always made constant by the automatic gain control circuit. As a result, the maximum voltage value of the I signal is always constant.
【００２９】図１０は倍周同位相信号発生回路１１０ｄ
における各部の波形である。Ｉ信号を倍周同位相信号発
生回路１１０ｄの入力とし、Ｉ信号の絶対値を出力する
絶対値回路９０２によって、信号Ｌが得られる。この波
形の最大ピーク電圧Ｖｍに対し、電圧比較器９０３の基
準電圧Ｖｓを２-1/2Ｖｍに設定することにより、電圧比
較器９０３の出力信号としてＱ２信号と同じ周波数で直
交関係を有し、かつ、送信データによっては出力信号が
変化しないＩ２信号が得られる。FIG. 10 shows a frequency-doubled in-phase signal generation circuit 110d.
It is a waveform of each part in. A signal L is obtained by an absolute value circuit 902 which receives the I signal as an input to the frequency-doubled in-phase signal generation circuit 110d and outputs the absolute value of the I signal. By setting the reference voltage Vs of the voltage comparator 903 to 2 −1/2 Vm with respect to the maximum peak voltage Vm of this waveform, the output signal of the voltage comparator 903 has an orthogonal relationship at the same frequency as the Q2 signal. Moreover, an I2 signal whose output signal does not change depending on the transmission data can be obtained.
【００３０】以上のように、本実施例によれば、ＦＳＫ
復調器が入力ＦＳＫ信号に対して自動利得制御している
場合、Ｉ信号を入力として電圧比較器９０３と絶対値回
路９０２を用いることにより、Ｉ２信号を発生すること
ができる。As described above, according to this embodiment, the FSK
When the demodulator is performing automatic gain control on the input FSK signal, the I2 signal can be generated by using the voltage comparator 903 and the absolute value circuit 902 with the I signal as an input.
【００３１】なお、本実施例では、Ｉ信号を倍周同位相
信号発生器１１０ｄの入力信号としたが、Ｑ信号を入力
信号としても同様の出力信号Ｉ２が得られる。In this embodiment, the I signal is the input signal of the frequency-doubled in-phase signal generator 110d, but the same output signal I2 can be obtained by using the Q signal as the input signal.
【００３２】また、本実施例において、絶対値回路９０
２を自乗回路に置き換えても同様な波形が得られ、Ｉ２
信号をつくることができる。Further, in the present embodiment, the absolute value circuit 90
Even if 2 is replaced with a squaring circuit, a similar waveform is obtained, and I2
Can make a signal.
【００３３】（実施例６）次に、本発明の第６の実施例
について図１１を参照しながら説明する。図１１は図１
に示したＦＳＫ復調器の、別な構成を示したものであ
る。図１１において、１０１はアンテナや増幅器（図示
せず）を介して入力したＦＳＫ信号の入力端子、１０２
はミキサ、１０３はローパスフィルタ、１０８は９０度
移相器、１０９は局部発振器で、１１１は倍周直交位相
発生回路で、１１０は倍周同位相発生回路、１０６は復
調回路、１０７は復調回路出力で、以上は図１に示した
ものと同様のものである。図１１において、図１の構成
と異なる点は、１１２はＦＳＫ入力信号から受信電界の
強度を検出する受信電界強度検出回路１１２と、復調回
路入力制御回路１１３の制御に基づきローパスフィルタ
１０３の出力先を変化させるスイッチ回路１１４を新た
に設けた点である。(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to FIG. 11 is shown in FIG.
6 shows another configuration of the FSK demodulator shown in FIG. In FIG. 11, 101 is an input terminal for an FSK signal input via an antenna or an amplifier (not shown), 102
Is a mixer, 103 is a low-pass filter, 108 is a 90-degree phase shifter, 109 is a local oscillator, 111 is a frequency doubled quadrature phase generation circuit, 110 is a frequency doubled in-phase generation circuit, 106 is a demodulation circuit, and 107 is a demodulation circuit. At output, the above is similar to that shown in FIG. 11 is different from the configuration of FIG. 1 in that the reference numeral 112 denotes a reception electric field strength detection circuit 112 that detects the strength of the reception electric field from the FSK input signal, and an output destination of the low pass filter 103 based on the control of the demodulation circuit input control circuit 113. This is the point that a switch circuit 114 for changing is newly provided.
【００３４】以上のように構成されたＦＳＫ復調器につ
いて、以下その動作を説明する。第２から第６の実施例
に示した倍周同位相発生回路１１０の構成では、Ｉ信号
及びＱ信号のアナログ情報をもとにＩ２信号をつくって
いる。そのため、ＦＳＫ信号の電界強度によっては増幅
器の飽和などによって、Ｉ、Ｑ信号が歪んでしまい、倍
周同位相信号発生回路１１０の出力信号がＱ２信号と直
交関係を保てなくなる。そこで、本実施例の復調器は、
受信電界強度検出回路１１２によって入力ＦＳＫ信号の
入力レベルを検出し、そのレベルが一定値を越えた場
合、復調回路入力制御回路１１３の制御信号により、ス
イッチ回路１１４を制御し、復調回路１０６に対する入
力信号をＩ２、Ｑ２信号から、Ｉ、Ｑ信号に切り替える
ようにしている。The operation of the FSK demodulator configured as described above will be described below. In the configuration of the double frequency in-phase generator circuit 110 shown in the second to sixth embodiments, the I2 signal is created based on the analog information of the I signal and the Q signal. Therefore, depending on the electric field strength of the FSK signal, the I and Q signals are distorted due to saturation of the amplifier or the like, and the output signal of the frequency-doubled in-phase signal generation circuit 110 cannot maintain the orthogonal relationship with the Q2 signal. Therefore, the demodulator of this embodiment is
The reception electric field strength detection circuit 112 detects the input level of the input FSK signal, and when the level exceeds a certain value, the control signal of the demodulation circuit input control circuit 113 controls the switch circuit 114 to input to the demodulation circuit 106. The signal is switched from the I2 and Q2 signals to the I and Q signals.
【００３５】以上のように、本実施例によれば、ＦＳＫ
信号の受信電界強度を検出し、そのレベルによって復調
回路に対する入力をＩ２、Ｑ２信号からＩ、Ｑ信号に切
り替えることにより、倍周直交信号Ｉ２、Ｑ２を復調回
路入力とした際、増幅器の飽和によって、Ｉ、Ｑ信号が
歪んでいる場合の特性劣化を減少させることができる。As described above, according to this embodiment, the FSK
By detecting the received electric field strength of the signal and switching the input to the demodulation circuit from the I2, Q2 signal to the I, Q signal according to the level, when the doubled quadrature signals I2, Q2 are used as the demodulation circuit input, the saturation of the amplifier causes It is possible to reduce characteristic deterioration when the I, Q signals are distorted.
【００３６】[0036]
【発明の効果】以上のように、本発明は、Ｉ信号とＱ信
号を２逓倍したとみなせる直交信号を用いて、復調回路
により復調信号を得ることにより、変調指数が等価的に
２倍になり、復調出力のジッタが減少し、復調精度が向
上する。また、局部発振器の発振周波数が搬送波周波数
とずれることにより受信感度の劣化を減少することがで
きる。As described above, according to the present invention, the modulation index is equivalently doubled by obtaining the demodulated signal by the demodulation circuit using the quadrature signal which can be regarded as the I signal and the Q signal which are doubled. Therefore, the jitter of the demodulation output is reduced and the demodulation accuracy is improved. Further, it is possible to reduce the deterioration of reception sensitivity due to the deviation of the oscillation frequency of the local oscillator from the carrier frequency.
【図１】本発明の第１の実施例におけるＦＳＫ復調器の
ブロック結線図FIG. 1 is a block connection diagram of an FSK demodulator according to a first embodiment of the present invention.
【図２】本発明の第１の実施例におけるＦＳＫ復調器の
要部波形図FIG. 2 is a waveform diagram of essential parts of the FSK demodulator according to the first embodiment of the present invention.
【図３】本発明の第２の実施例におけるＦＳＫ復調器の
ブロック結線図FIG. 3 is a block connection diagram of an FSK demodulator according to a second embodiment of the present invention.
【図４】本発明の第２の実施例におけるＦＳＫ復調器の
要部波形図FIG. 4 is a waveform diagram of essential parts of an FSK demodulator according to a second embodiment of the present invention.
【図５】本発明の第３の実施例におけるＦＳＫ復調器の
ブロック結線図FIG. 5 is a block connection diagram of an FSK demodulator according to a third embodiment of the present invention.
【図６】本発明の第３の実施例におけるＦＳＫ復調器の
要部波形図FIG. 6 is a waveform diagram of essential parts of an FSK demodulator according to a third embodiment of the present invention.
【図７】本発明の第４の実施例におけるＦＳＫ復調器の
ブロック結線図FIG. 7 is a block connection diagram of an FSK demodulator according to a fourth embodiment of the present invention.
【図８】本発明の第４の実施例におけるＦＳＫ復調器の
要部波形図FIG. 8 is a waveform diagram of essential parts of an FSK demodulator according to a fourth embodiment of the present invention.
【図９】本発明の第５の実施例におけるＦＳＫ復調器の
ブロック結線図FIG. 9 is a block connection diagram of an FSK demodulator according to a fifth embodiment of the present invention.
【図１０】本発明の第５の実施例におけるＦＳＫ復調器
の要部波形図FIG. 10 is a waveform diagram of essential parts of an FSK demodulator according to a fifth embodiment of the present invention.
【図１１】本発明の第６の実施例におけるＦＳＫ復調器
のブロック結線図FIG. 11 is a block connection diagram of an FSK demodulator according to a sixth embodiment of the present invention.
【図１２】従来のＦＳＫ復調器の構成を示すブロック結
線図FIG. 12 is a block connection diagram showing a configuration of a conventional FSK demodulator.
１ ＦＳＫ信号入力端子 ２、３ ミキサ ４ ローパスフィルタ ５ ９０度移相器 ６ 局部発振器 ７ リッミタアンプ ８ Ｄフリップフロップ ９ 復調出力 １０１ ＦＳＫ信号入力端子 １０２ ミキサ １０３ ローパスフィルタ １０４ リミッタアンプ １０５ 排他的論理和回路 １０６ 復調回路 １０７ 復調回路出力 １０８ ９０度移相器 １０９ 局部発振器 １１０ 倍周同位相発生回路 １１１ 倍周直交位相発生回路 ３０１ Ｉ信号入力端子 ３０２ Ｑ信号入力端子 ３０３ 加算回路 ３０４ 減算回路 ３０５ リミッタアンプ ３０６ 排他的論理和回路 ５０１ Ｉ信号入力端子 ５０２ Ｑ信号入力端子 ５０３、５０４ 電圧比較器 ５０５ 反転回路 ５０６ 排他的論理和回路 ７０１ Ｉ信号入力端子 ７０２ Ｑ信号入力端子 ７０３、７０４ 絶対値回路 ７０５ 電圧比較器 ９０１ Ｉ信号入力端子 ９０２ 絶対値回路 ９０３ 電圧比較器 ９０４ 基準電圧入力端子 １１２ 受信電界強度検出回路、 １１３ 復調回路入力制御回路、 １１４ スイッチ回路 1 FSK signal input terminal 2, 3 mixer 4 low-pass filter 5 90 degree phase shifter 6 local oscillator 7 limiter amplifier 8 D flip-flop 9 demodulation output 101 FSK signal input terminal 102 mixer 103 low-pass filter 104 limiter amplifier 105 exclusive OR circuit 106 Demodulation circuit 107 Demodulation circuit output 108 90 degree phase shifter 109 Local oscillator 110 Double frequency in-phase generation circuit 111 Double frequency quadrature phase generation circuit 301 I signal input terminal 302 Q signal input terminal 303 Adder circuit 304 Subtractor circuit 305 Limiter amplifier 306 Exclusive OR circuit 501 I signal input terminal 502 Q signal input terminal 503, 504 Voltage comparator 505 Inversion circuit 506 Exclusive OR circuit 701 I signal input terminal 702 Q signal input terminal 703, 704 Absolute value circuit 705 Voltage Comparator 901 I signal input terminal 902 Absolute value circuit 903 Voltage comparator 904 Reference voltage input terminal 112 Received electric field strength detection circuit 113 Demodulation circuit input control circuit 114 Switch circuit
───────────────────────────────────────────────────── フロントページの続き (72)発明者 横崎 克司 神奈川県横浜市港北区綱島東四丁目３番１ 号 松下通信工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsushi Yokozaki 4-3-1, Tsunashima-higashi, Kohoku-ku, Yokohama-shi, Kanagawa Matsushita Communication Industrial Co., Ltd.
Claims (10)
交位相信号を得る直交ミキサ及びローパスフィルタと、
前記同位相信号を２値化する第１のリミッタアンプと、
前記直交位相信号を２値化する第２のリミッタアンプ
と、前記第１、第２のリミッタアンプにより２値化した
信号の排他的論理和を得る第１の排他的論理和回路から
なる倍周直交位相信号発生回路と、前記同位相信号及び
前記直交位相信号から、前記直交位相信号発生回路の出
力信号と同じ周波数で、かつ直交関係にあり、送信デー
タによっては、出力信号が変化しない信号を得る倍周同
位相信号発生回路と、前記直交位相信号発生回路と前記
倍周同位相信号発生回路の出力信号から復調信号を得る
復調回路とを具備するＦＳＫ復調器。1. A quadrature mixer and a low-pass filter for obtaining an in-phase signal and a quadrature-phase signal from a frequency shift keying signal,
A first limiter amplifier for binarizing the in-phase signal,
A frequency multiplication circuit including a second limiter amplifier for binarizing the quadrature phase signal and a first exclusive OR circuit for obtaining an exclusive OR of the signals binarized by the first and second limiter amplifiers. From the quadrature phase signal generation circuit, the in-phase signal and the quadrature phase signal, the same frequency as the output signal of the quadrature phase signal generation circuit, and in a quadrature relationship, depending on the transmission data, a signal whose output signal does not change An FSK demodulator comprising: a frequency-divided in-phase signal generation circuit for obtaining, a quadrature-phase signal generation circuit, and a demodulation circuit for obtaining a demodulated signal from an output signal of the frequency-doubled in-phase signal generation circuit.
と直交位相信号を加算する加算回路と、前記同位相信号
と前記直交位相信号を減算する減算回路と、前記加算回
路の出力信号を２値化する第３のリミッタアンプと、前
記減算回路の出力信号を２値化する第４のリミッタアン
プと、前記第３、第４のリミッタアンプにより２値化し
た信号の排他的論理和をとる第２の排他的論理和回路を
具備することを特徴とする請求項１記載のＦＳＫ復調
器。2. A frequency-divided in-phase signal generation circuit, an addition circuit for adding the in-phase signal and the quadrature phase signal, a subtraction circuit for subtracting the in-phase signal and the quadrature-phase signal, and an output signal of the addition circuit. A limiter amplifier for binarizing the signal, a fourth limiter amplifier for binarizing the output signal of the subtraction circuit, and an exclusive OR of the signals binarized by the third and fourth limiter amplifiers. The FSK demodulator according to claim 1, further comprising a second exclusive OR circuit for
たは同位相信号の内、どちらか一方の信号の位相を４５
度移相する第１の移相器と、前記第１の移相器に対する
入力と同じ信号を−４５度移相する第２の移相器と、前
記第１の移相器の出力信号を２値化する第５のリミッタ
アンプと、前記第２の移相器の出力信号を２値化する第
６のリミッタアンプと、前記第５、第６のリミッタアン
プにより２値化した信号の排他的論理和をとる第３の排
他的論理和回路を具備することを特徴とする請求項１記
載のＦＳＫ復調器。3. The frequency-divided in-phase signal generation circuit sets the phase of either one of the quadrature signal and the in-phase signal to 45.
A first phase shifter for shifting the phase, a second phase shifter for shifting the same signal as the input to the first phase shifter by −45 degrees, and an output signal of the first phase shifter. Exclusion of a binarized fifth limiter amplifier, a sixth limiter amplifier that binarizes the output signal of the second phase shifter, and a binarized signal of the fifth and sixth limiter amplifiers. 2. The FSK demodulator according to claim 1, further comprising a third exclusive OR circuit that takes a logical OR.
の電圧と直交位相信号の電圧を比較する第１の電圧比較
器と、前記同位相信号と前記直交位相信号の内、どちら
か一方の信号の符号を反転する反転回路と、前記同位相
信号と前記直交位相信号のうち、前記反転回路の入力信
号ではない信号の電圧と前記反転回路の出力信号の電圧
を比較する第２の電圧比較器と、前記第１と第２の電圧
比較器の出力信号の排他的論理和をとる第４の排他的論
理和回路を具備することを特徴とする請求項１記載のＦ
ＳＫ復調器。4. The frequency-divided in-phase signal generation circuit includes one of a first voltage comparator for comparing the voltage of the in-phase signal and the voltage of the quadrature signal, and one of the in-phase signal and the quadrature-phase signal. A second inverting circuit for inverting the sign of one of the signals, and a second voltage for comparing the voltage of a signal that is not the input signal of the inverting circuit and the voltage of the output signal of the inverting circuit among the in-phase signal and the quadrature-phase signal. 2. The F according to claim 1, further comprising a voltage comparator and a fourth exclusive OR circuit that takes an exclusive OR of the output signals of the first and second voltage comparators.
SK demodulator.
の絶対値をとる第１の絶対値回路と、直交位相信号の絶
対値をとる第２の絶対値回路と、前記第１と前記第２の
絶対値回路の出力信号の電圧を比較する第３の電圧比較
器とを具備することを特徴とする請求項１記載のＦＳＫ
復調器。5. A frequency-doubled in-phase signal generation circuit includes a first absolute-value circuit that takes an absolute value of an in-phase signal, a second absolute-value circuit that takes an absolute value of a quadrature-phase signal, and the first and second circuits. The FSK according to claim 1, further comprising a third voltage comparator for comparing the voltages of the output signals of the second absolute value circuits.
Demodulator.
の自乗をとる第１の自乗回路と、直交位相信号の自乗を
とる第２の自乗回路と、前記第１と前記第２の自乗回路
の出力信号の電圧を比較する第４の電圧比較器とを具備
することを特徴とする請求項１記載のＦＳＫ復調器。6. The frequency-doubled in-phase signal generation circuit includes a first squaring circuit that squares an in-phase signal, a second squaring circuit that squares a quadrature-phase signal, and the first and second circuits. The FSK demodulator according to claim 1, further comprising a fourth voltage comparator for comparing the voltages of the output signals of the squaring circuits.
または直交位相信号の内、どちらか一方の信号の絶対値
をとる第３の絶対値回路と、前記第３の絶対値回路の出
力信号の電圧と基準電圧を比較する第５の電圧比較器と
を具備することを特徴とする請求項１記載のＦＳＫ復調
器。7. A frequency-doubled in-phase signal generation circuit includes a third absolute-value circuit for taking an absolute value of either one of the in-phase signal and the quadrature-phase signal, and the third absolute-value circuit. The FSK demodulator according to claim 1, further comprising a fifth voltage comparator for comparing the voltage of the output signal with the reference voltage.
または直交位相信号の内、どちらか一方の信号の自乗を
とる第３の自乗回路と、前記第３の自乗回路の出力信号
の電圧と基準電圧を比較する第６の電圧比較器とを具備
することを特徴とする請求項１記載のＦＳＫ復調器。8. A frequency-doubled in-phase signal generation circuit includes a third squaring circuit that squares one of an in-phase signal and a quadrature-phase signal, and an output signal of the third squaring circuit. The FSK demodulator according to claim 1, further comprising a sixth voltage comparator for comparing the voltage and the reference voltage.
調信号の振幅を一定幅に制御する自動利得制御回路を有
することを特徴とする請求項１記載のＦＳＫ復調器。9. The FSK demodulator according to claim 1, further comprising an automatic gain control circuit that controls the amplitude of the input frequency shift keying signal to a constant width before the quadrature mixer.
度に比例した信号を出力する受信電界強度検出回路と、
前記受信電界強度検出回路の出力信号が一定値を超える
ことにより、制御信号を出力する復調回路入力制御回路
と、前記復調回路入力制御回路の出力信号により、復調
回路に対する入力信号を同位相信号と直交位相信号に切
り替えるスイッチ回路とを有することを特徴とする請求
項１記載のＦＳＫ復調器。10. A received electric field strength detection circuit for outputting a signal proportional to the received electric field strength of an input frequency shift keying signal,
A demodulation circuit input control circuit that outputs a control signal when the output signal of the received electric field strength detection circuit exceeds a certain value, and an input signal to the demodulation circuit is an in-phase signal by the output signal of the demodulation circuit input control circuit. The FSK demodulator according to claim 1, further comprising a switch circuit for switching to a quadrature phase signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24784493A JPH07107127A (en) | 1993-10-04 | 1993-10-04 | Fsk demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24784493A JPH07107127A (en) | 1993-10-04 | 1993-10-04 | Fsk demodulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07107127A true JPH07107127A (en) | 1995-04-21 |
Family
ID=17169511
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24784493A Pending JPH07107127A (en) | 1993-10-04 | 1993-10-04 | Fsk demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07107127A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006319897A (en) * | 2005-05-16 | 2006-11-24 | Oki Electric Ind Co Ltd | Demodulation circuit and demodulation method |
| CN106108949A (en) * | 2016-08-29 | 2016-11-16 | 深圳市理邦精密仪器股份有限公司 | Fetal rhythm audio signal processor and fetal monitoring equipment |
-
1993
- 1993-10-04 JP JP24784493A patent/JPH07107127A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006319897A (en) * | 2005-05-16 | 2006-11-24 | Oki Electric Ind Co Ltd | Demodulation circuit and demodulation method |
| JP4560440B2 (en) * | 2005-05-16 | 2010-10-13 | Ｏｋｉセミコンダクタ株式会社 | Demodulation circuit and demodulation method |
| KR101243753B1 (en) * | 2005-05-16 | 2013-03-14 | 오끼 덴끼 고오교 가부시끼가이샤 | Demodulation circuit and demodulation method |
| CN106108949A (en) * | 2016-08-29 | 2016-11-16 | 深圳市理邦精密仪器股份有限公司 | Fetal rhythm audio signal processor and fetal monitoring equipment |
| CN106108949B (en) * | 2016-08-29 | 2019-09-17 | 深圳市理邦精密仪器股份有限公司 | Fetal rhythm audio signal processor and fetal monitoring equipment |
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