JPH07106953A - Frequency divider - Google Patents
Frequency dividerInfo
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- JPH07106953A JPH07106953A JP5247847A JP24784793A JPH07106953A JP H07106953 A JPH07106953 A JP H07106953A JP 5247847 A JP5247847 A JP 5247847A JP 24784793 A JP24784793 A JP 24784793A JP H07106953 A JPH07106953 A JP H07106953A
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- pulse
- signal
- circuit
- counter
- frequency divider
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、主として高周波多チャ
ンネル無線機等を構成するＰＬＬ周波数シンセサイザに
用いられる分周器に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency divider mainly used in a PLL frequency synthesizer which constitutes a high frequency multi-channel radio or the like.
【０００２】[0002]
【従来の技術】ＰＬＬ周波数シンセサイザは、多チャン
ネル無線機の重要な構成要素であり、各種無線機器・装
置に広く利用されている。ＰＬＬ周波数シンセサイザの
チャンネル切替時間を短縮するには、比較周波数を上げ
てループ利得を高くすることが有効である。しかし、整
数の分周数の分周器を用いたＰＬＬ周波数シンセサイザ
においては、比較周波数の上限はチャンネル間隔により
一義的に決定される。2. Description of the Related Art A PLL frequency synthesizer is an important constituent element of a multi-channel radio and is widely used in various radio equipments and devices. In order to shorten the channel switching time of the PLL frequency synthesizer, it is effective to raise the comparison frequency and raise the loop gain. However, in a PLL frequency synthesizer using a frequency divider with an integer frequency division number, the upper limit of the comparison frequency is uniquely determined by the channel interval.
【０００３】一方、分数の分周数をもつ分周器を用いる
ことで、比較周波数はチャンネル間隔により制限されな
くなり、比較周波数を高く設定することが可能となる。
以下従来の分数の分周数をもつ分周器について説明す
る。On the other hand, by using a frequency divider having a frequency division number, the comparison frequency is not limited by the channel interval, and the comparison frequency can be set high.
Hereinafter, a conventional frequency divider having a frequency division number will be described.
【０００４】図６（ａ）は従来の分数の分周数をもつ分
周器のブロック構成図である。図６（ａ）において、６
０１は分数の分周数をもつ分周器、６０２は設定値Ｍの
カウンタ、６０３はＡＮＤ回路でである。図６（ｂ）は
図６（ａ）中のｉ，ｊ，ｋ各点での信号のタイミング図
で、ｉは入力信号、ｊはカウンタ６０２の出力信号、ｋ
は分周器６０１の出力信号である。カウンタ６０２は入
力信号ｉをカウントし、信号ｊのようにＭ周期毎に１周
期の間はＬｏｗ出力となる。ＡＮＤ回路６０３は、入力
信号ｉとカウンタ６０２の出力信号ｊの論理積をとった
信号ｋを出力する。信号ｋは、Ｍ周期毎に１周期分のパ
ルスが除去されて入力信号ｉのＭ周期の間にＭ−１個の
パルスを含むので、分周器６０１の分周数はＭ／（Ｍ−
１）と分数の分周数になる。FIG. 6A is a block diagram of a conventional frequency divider having a frequency division number. In FIG. 6A, 6
Reference numeral 01 is a frequency divider having a frequency division number, 602 is a counter having a set value M, and 603 is an AND circuit. FIG. 6B is a timing chart of signals at points i, j, and k in FIG. 6A, where i is an input signal, j is an output signal of the counter 602, and k is a signal.
Is an output signal of the frequency divider 601. The counter 602 counts the input signal i, and outputs a Low signal for one cycle every M cycles like the signal j. The AND circuit 603 outputs a signal k that is the logical product of the input signal i and the output signal j of the counter 602. In the signal k, one cycle pulse is removed every M cycles and M-1 pulses are included during M cycles of the input signal i. Therefore, the frequency division number of the frequency divider 601 is M / (M−
1) and the division number of the fraction.
【０００５】[0005]
【発明が解決しようとする課題】従来の分数の分周数を
もつ分周器を用いた場合、カウンタの設定周期毎に１個
のパルスを除去する。このため、分周器の段数が少ない
場合に分周数の分解能が低く、ＰＬＬ周波数シンセサイ
ザを構成した場合に十分な周波数設定精度が得られない
という課題を有していた。When a conventional frequency divider having a frequency division number is used, one pulse is removed at each counter setting cycle. Therefore, when the number of stages of the frequency divider is small, the resolution of the frequency division number is low, and there is a problem that sufficient frequency setting accuracy cannot be obtained when the PLL frequency synthesizer is configured.
【０００６】本発明は上記課題を解決するもので、分数
分周器の段数を増やすことなく、周波数設定精度の高い
ＰＬＬ周波数シンセサイザを実現する分周器を提供する
ことを目的とする。The present invention solves the above problems, and an object of the present invention is to provide a frequency divider that realizes a PLL frequency synthesizer with high frequency setting accuracy without increasing the number of stages of the fractional frequency divider.
【０００７】[0007]
【課題を解決するための手段】この目的を達成するため
本発明は、入力信号をカウントしてパルス除去信号とパ
ルス付加信号を出力するパルス制御回路と、前記パルス
除去信号で制御されてパルス除去を行なうパルス除去回
路と、前記パルス付加信号で制御されてパルス付加を行
なうパルス付加回路とを設け、入力信号を分周する動作
を制御することで、分周数の分母および分子を制御する
構成を有している。To achieve this object, the present invention provides a pulse control circuit for counting an input signal and outputting a pulse removal signal and a pulse addition signal, and a pulse removal circuit controlled by the pulse removal signal. And a pulse addition circuit that performs pulse addition under the control of the pulse addition signal and controls the operation of dividing the input signal to control the denominator and numerator of the frequency division number. have.
【０００８】[0008]
【作用】本発明は上記構成により、少ない分数分周器の
段数で分周器の分解能を上げることが可能であり、周波
数設定精度が高く、かつ、チャンネル切替時間の短いＰ
ＬＬ周波数シンセサイザを実現することを可能とする。According to the present invention, with the above configuration, it is possible to increase the resolution of the frequency divider with a small number of stages of the fractional frequency divider, the frequency setting accuracy is high, and the channel switching time is short.
It is possible to realize an LL frequency synthesizer.
【０００９】[0009]
【実施例】（実施例１）以下本発明の第１の実施例につ
いて、図面を参照しながら説明する。図１は本発明の第
１の実施例における分周器のブロック結線図である。(Embodiment 1) A first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block connection diagram of a frequency divider according to the first embodiment of the present invention.
【００１０】図１において、１０１は分数の分周数をも
つ分周器であり、当該分周器１は以下の通り構成されて
いる。In FIG. 1, 101 is a frequency divider having a frequency division number, and the frequency divider 1 is constructed as follows.
【００１１】１０２はパルス制御回路、１０３はパルス
除去回路、１０４はパルス付加回路、１０５は入力端
子、１０６は出力端子、１０７はＬｏｗ入力の場合は分
周器１０１がパルス除去を行いＨｉ入力の場合はパルス
付加を行なう切替信号入力端子、１０８は設定Ｍのカウ
ンタ回路である。さらに、１０９はＮＯＴ回路、１１０
はＡＮＤ回路、１１１はＪＫ−ＦＦ回路、１１２はＥＸ
ＯＲ回路である。Reference numeral 102 is a pulse control circuit, 103 is a pulse removing circuit, 104 is a pulse adding circuit, 105 is an input terminal, 106 is an output terminal, and 107 is a Low input. In the case, a switching signal input terminal for adding a pulse, and 108 is a counter circuit of setting M. Further, 109 is a NOT circuit, 110
Is an AND circuit, 111 is a JK-FF circuit, and 112 is an EX
It is an OR circuit.
【００１２】図２は、図１中のａ，ｂ，ｃ，ｄ，ｅ、ｆ
各点での信号のタイミング図で、ａは入力信号、ｂはパ
ルス付加／除去切替信号、ｃはパルス除去信号、ｄはパ
ルス付加信号、ｅはパルス除去回路の出力、ｆは分周器
１０１の出力である。FIG. 2 shows a, b, c, d, e and f in FIG.
In the timing chart of the signal at each point, a is an input signal, b is a pulse addition / removal switching signal, c is a pulse removal signal, d is a pulse addition signal, e is the output of the pulse removal circuit, and f is the frequency divider 101. Is the output of.
【００１３】以上のように構成された分数の分周数をも
つ分周器について図２を用いてその動作を説明する。The operation of the frequency divider having the fractional division number configured as described above will be described with reference to FIG.
【００１４】まず、パルス制御回路１０２において、カ
ウンタ回路１０８は、入力信号ａをカウントして、Ｍ周
期毎に１周期の間出力がＬｏｗになる信号ｃを出力す
る。カウンタ回路１０８の出力をＮＯＴ回路１０９で反
転した信号と入力信号ａと切替信号ｂとの論理積をＡＮ
Ｄ回路１１０でとり、パルス付加信号ｄとして出力す
る。First, in the pulse control circuit 102, the counter circuit 108 counts the input signal a and outputs a signal c whose output becomes Low for one cycle every M cycles. The logical product of the signal obtained by inverting the output of the counter circuit 108 by the NOT circuit 109, the input signal a, and the switching signal b is AN.
It is taken by the D circuit 110 and output as the pulse added signal d.
【００１５】パルス除去回路１０３では、パルス除去信
号ｃがＬｏｗの場合は入力信号ａのパルスの立ち上がり
でＪＫ−ＦＦ回路１１１の出力が反転し、パルス除去信
号ｃがＨｉの場合は入力信号ａのパルスの立ち上がりに
対してＪＫ−ＦＦ回路１１１の出力は変化しないため、
入力信号ａのパルスの内でパルス除去信号ｃがＨｉの間
に入力したパルスを除去した後で２分周した信号ｅを出
力する。In the pulse removing circuit 103, when the pulse removing signal c is Low, the output of the JK-FF circuit 111 is inverted at the rising edge of the pulse of the input signal a, and when the pulse removing signal c is Hi, the input signal a is changed. Since the output of the JK-FF circuit 111 does not change with respect to the rising edge of the pulse,
Among the pulses of the input signal a, a pulse e that is input while the pulse removal signal c is Hi is removed, and then a signal e divided by 2 is output.
【００１６】パルス付加回路１０４では、ＥＸＯＲ回路
１１２でパルス除去回路１０３の出力信号ｅにパルス付
加信号ｄを加えることで、パルス付加を行った信号ｆを
出力し、入力信号ａを分周した信号ｆを出力する。In the pulse addition circuit 104, the EXOR circuit 112 adds the pulse addition signal d to the output signal e of the pulse removal circuit 103 to output the pulse-added signal f and divide the input signal a. Output f.
【００１７】上記動作により、切替信号ｂがＬｏｗの場
合は、Ｍ個毎に１個の入力パルスを除去した後に２分周
した信号が出力され、分周器１０１の分周数は２×Ｍ／
（Ｍ−１）となる。一方、切替信号ｂがＨｉの場合は、
Ｍ個毎に１個の入力パルスを付加した信号を２分周した
信号が出力され、分周器１０１の分周数は２×Ｍ／（Ｍ
＋１）となる。According to the above operation, when the switching signal b is Low, a signal obtained by dividing one input pulse for every M pulses and then dividing the frequency by two is output, and the frequency division number of the frequency divider 101 is 2 × M. /
(M-1). On the other hand, when the switching signal b is Hi,
A signal obtained by dividing the signal to which one input pulse is added for every M is divided into two, and the frequency division number of the frequency divider 101 is 2 × M / (M
+1).
【００１８】以上のように本実施例によれば、パルス制
御回路１０２と、パルス除去回路１０３と、パルス付加
回路１０４を設け、パルス制御回路１０２で入力信号を
カウントしてパルス除去信号とパルス付加信号を生成
し、パルス除去信号で入力信号の分周動作を制御するこ
とでパルスを除去する、あるいは、パルス除去回路１０
３の出力にパルス付加信号を加えてパルスを付加するこ
とにより、分周数の分母および分子が制御でき、本構成
の分数分周器を用いることで周波数設定精度が高く、か
つ、チャンネル切替時間の短いＰＬＬ周波数シンセサイ
ザの実現を可能とする。As described above, according to this embodiment, the pulse control circuit 102, the pulse removal circuit 103, and the pulse addition circuit 104 are provided, and the pulse control circuit 102 counts the input signal to add the pulse removal signal and the pulse addition signal. A pulse is removed by generating a signal and controlling the frequency dividing operation of the input signal with the pulse removal signal, or the pulse removal circuit 10
The denominator and the numerator of the frequency division number can be controlled by adding a pulse by adding a pulse addition signal to the output of 3, and by using the fractional frequency divider of this configuration, the frequency setting accuracy is high and the channel switching time is high. It enables the realization of a short PLL frequency synthesizer.
【００１９】（実施例２）以下、本発明の第２の実施例
について、図面を参照しながら説明する。図３は本発明
の第２の実施例における分周器のブロック結線及び要部
波形図である。(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 3 is a block connection diagram and a waveform diagram of essential parts of a frequency divider according to a second embodiment of the present invention.
【００２０】図３（ａ）において、３０１は分数の分周
数をもつ分周器であり、当該分周器３０１において、３
０２はパルス制御回路、３０３は設定Ｍのカウンタ回
路、３０４はプリセット端子を備えた設定Ｃのカウンタ
回路、３０５、３０６はＡＮＤ回路、３０７はＯＲ回路
である。In FIG. 3A, reference numeral 301 denotes a frequency divider having a frequency division number of a fraction.
Reference numeral 02 is a pulse control circuit, 303 is a setting M counter circuit, 304 is a setting C counter circuit having a preset terminal, 305 and 306 are AND circuits, and 307 is an OR circuit.
【００２１】図３（ｂ）は、図３（ａ）中のａ、ｂ、
ｃ、ｄ、ｇ、ｈ各点での信号のタイミング図で、ｇはカ
ウンタ３０３の出力、ｈはカウンタ３０４の出力であ
る。FIG. 3B shows a, b, and a in FIG.
In the timing chart of signals at points c, d, g, and h, g is the output of the counter 303 and h is the output of the counter 304.
【００２２】なお、以下の説明では、Ｍ／Ｃを切り上げ
た整数をｎとおく。また、図１と同じ構成要素について
は説明は省略する。In the following description, n is an integer obtained by rounding up M / C. The description of the same components as those in FIG. 1 is omitted.
【００２３】以上のように構成された分周器について実
施例１と異なる動作について説明する。まず、カウンタ
回路３０３は、入力信号ａをカウントしてＭ周期毎に１
周期の間出力がＬｏｗになる信号ｇを出力する。カウン
タ回路３０４は、入力信号ａをカウントしてＣ周期毎に
１周期の間出力がＬｏｗになるが、カウンタ回路３０３
のＬｏｗ出力でプリセットされる信号ｈを出力する。Ａ
ＮＤ回路３０５で、カウンタ回路３０３、３０４の出力
の論理積をとることで、周期Ｍの間に分散してｎ周期分
Ｌｏｗとなる期間があるパルス除去信号ｃを出力する。
ＮＯＴ回路３０７でパルス除去信号ｃを反転した信号
と、入力信号ａと、切替信号ｂの論理積をＡＮＤ回路３
０６でとり、パルス付加信号ｄとして出力する。The operation of the frequency divider configured as described above, which is different from that of the first embodiment, will be described. First, the counter circuit 303 counts the input signal a and outputs 1 every M cycles.
A signal g whose output is Low during the cycle is output. The counter circuit 304 counts the input signal a and the output becomes Low for one cycle every C cycles, but the counter circuit 303
The signal h preset by the Low output is output. A
The ND circuit 305 outputs the pulse removal signal c which has a period in which it is distributed during the period M and is Low for n periods by taking the logical product of the outputs of the counter circuits 303 and 304.
A logical product of the signal obtained by inverting the pulse removal signal c in the NOT circuit 307, the input signal a, and the switching signal b is AND circuit 3
At 06, it is output as a pulse added signal d.
【００２４】パルス除去信号ｃでパルス除去回路１０３
を制御してパルス除去を行い、パルス付加信号ｄでパル
ス付加回路１０４を制御してパルス付加を行なうこと
で、入力信号ａを分周した信号ｆを出力する。The pulse removal circuit 103 receives the pulse removal signal c.
To remove the pulse and control the pulse adding circuit 104 with the pulse adding signal d to add the pulse, thereby outputting the signal f obtained by dividing the input signal a.
【００２５】上記動作により、本実施例の分数分周器で
は、切替信号ｂがＬｏｗの場合は、Ｍ周期の間にｎ個の
パルスを除去した後で２分周した信号が出力され、分周
数は２×Ｍ／（Ｍ−ｎ）となる。With the above operation, in the fractional frequency divider of the present embodiment, when the switching signal b is Low, a signal obtained by dividing n pulses during the M period and then dividing by 2 is output, and divided. The number of cycles is 2 × M / (M−n).
【００２６】一方、切替信号ｂがＨｉの場合は、Ｍ周期
の間にｎ個のパルスを付加した後で２分周した信号が出
力され、分周数は２×Ｍ／（Ｍ＋ｎ）となる。On the other hand, when the switching signal b is Hi, a signal obtained by adding n pulses during the M period and then dividing the frequency by 2 is output, and the frequency division number is 2 × M / (M + n). .
【００２７】以上のように本実施例の分数分周器によれ
ば、第１のカウンタと、第１のカウンタでプリセットさ
れる第２のカウンタとを設けることで、複数のパルス除
去、あるいは、複数のパルス付加を行ない、分周数の分
子および分母を制御できる。本構成の分数分周器を用い
ることで、少ない分数分周器の段数で、周波数設定精度
が高く、かつ、チャネル切替時間の短いＰＬＬ周波数シ
ンセサイザの実現が可能になる。As described above, according to the fractional frequency divider of this embodiment, by providing the first counter and the second counter preset by the first counter, a plurality of pulses can be removed or a plurality of pulses can be removed. Multiple pulses can be added to control the numerator and denominator of the frequency division number. By using the fractional frequency divider of this configuration, it is possible to realize a PLL frequency synthesizer with high frequency setting accuracy and short channel switching time with a small number of stages of the fractional frequency divider.
【００２８】（実施例３）以下本発明の分周器の第３の
実施例について、図面を参照しながら説明する。図４は
本発明の第３の実施例における分周器のブロック結線図
である。(Embodiment 3) A third embodiment of the frequency divider of the present invention will be described below with reference to the drawings. FIG. 4 is a block connection diagram of a frequency divider according to the third embodiment of the present invention.
【００２９】図４において、４０１は分数の分周数をも
つ分数分周器であり、当該分周器４０１において、４０
２、４０３、４０４はパルス制御回路、４０７はＡＮＤ
回路、４０８はＯＲ回路、４１１、４１２、４１３はパ
ルス除去／付加の動作を切り替える切替信号入力端子で
ある。図１と同様の構成要素の説明は省略する。In FIG. 4, reference numeral 401 denotes a fractional frequency divider having a fractional frequency division number.
2, 403 and 404 are pulse control circuits, 407 is an AND
A circuit, 408 is an OR circuit, and 411, 412, and 413 are switching signal input terminals for switching between pulse removal / addition operations. Description of the same components as in FIG. 1 is omitted.
【００３０】以上のように構成された分周器について、
以下実施例１と異なる動作について説明する。まず、Ａ
ＮＤ回路４０７では、パルス制御回路４０２、４０３、
４０４のパルス除去信号出力の論理積をとり、パルス除
去回路４０５に入力することで、パルス制御回路４０
２、４０３、４０４のそれぞれのパルス除去信号に対応
するパルスを除去する。Regarding the frequency divider configured as described above,
The operation different from that of the first embodiment will be described below. First, A
In the ND circuit 407, the pulse control circuits 402, 403,
By taking the logical product of the pulse removal signal outputs of 404 and inputting it to the pulse removal circuit 405, the pulse control circuit 40
The pulses corresponding to the respective pulse removal signals 2, 403 and 404 are removed.
【００３１】一方、ＯＲ回路４０８では、パルス制御回
路４０２、４０３、４０４のパルス付加信号出力の論理
和をとり、パルス除去回路４０６に入力することで、パ
ルス制御回路４０２、４０３、４０４のそれぞれのパル
ス付加信号に対応してパルス付加を行なう。On the other hand, in the OR circuit 408, the logical addition of the pulse-added signal outputs of the pulse control circuits 402, 403, 404 is calculated and input to the pulse removal circuit 406, so that each of the pulse control circuits 402, 403, 404. Pulses are added according to the pulse addition signal.
【００３２】以上のように本実施例の分数分周器によれ
ば、複数のパルス制御回路を備え、個々のパルス制御回
路のパルス除去信号を合成してパルス除去回路を制御
し、個々のパルス制御回路のパルス付加信号を合成して
パルス付加回路を制御することで、分数の分周数をもつ
分周器を多段に接続した分周器を構成することが可能と
なる。As described above, according to the fractional frequency divider of the present embodiment, a plurality of pulse control circuits are provided, the pulse removal signals of the individual pulse control circuits are combined to control the pulse removal circuits, and the individual pulse control circuits are controlled. By synthesizing the pulse addition signals of the control circuit and controlling the pulse addition circuit, it becomes possible to construct a frequency divider in which frequency dividers having a frequency division number are connected in multiple stages.
【００３３】（実施例４）以下本発明の分周器の第４の
実施例について、図面を参照しながら説明する。図５は
本発明の第４の実施例における分周器のブロック結線図
である。(Fourth Embodiment) A fourth embodiment of the frequency divider of the present invention will be described below with reference to the drawings. FIG. 5 is a block connection diagram of a frequency divider according to the fourth embodiment of the present invention.
【００３４】図５において、５０１は分数の分周数をも
つ分周器であり、当該分周器５０１において、５０２、
５０３、５０４はパルス制御回路、５１１はＡＮＤ回路
である。パルス制御回路５０２は、パルス除去／付加動
作を切り替える切替信号入力端子５１２と、カウンタ回
路５１３と、ＮＯＴ回路５１４と、ＡＮＤ回路５１５で
構成される。パルス制御回路５０３は、パルス除去／付
加動作を切り替える切替信号入力端子５１６と、カウン
ト・イネーブル端子を備えたカウンタ回路５１７と、Ｎ
ＯＴ回路５１８と、ＡＮＤ回路５１９で構成される。パ
ルス制御回路５０４は、パルス除去／付加動作を切り替
える切替信号入力端子５２０と、カウント・イネーブル
端子を備えたカウンタ回路５２１と、カウンタ・イネー
ブル端子とプリセット端子を備えたカウンタ回路５２２
と、ＡＮＤ回路５２３、５２４と、ＮＯＴ回路５２５で
構成される。なお、図１、４と同様の構成要素の説明は
省略した。In FIG. 5, reference numeral 501 is a frequency divider having a frequency division number, and in the frequency divider 501, 502,
Reference numerals 503 and 504 are pulse control circuits and 511 is an AND circuit. The pulse control circuit 502 includes a switching signal input terminal 512 that switches between pulse removal / addition operations, a counter circuit 513, a NOT circuit 514, and an AND circuit 515. The pulse control circuit 503 has a switching signal input terminal 516 for switching between pulse removal / addition operation, a counter circuit 517 having a count enable terminal, and N.
It is composed of an OT circuit 518 and an AND circuit 519. The pulse control circuit 504 has a switching signal input terminal 520 for switching between pulse removal / addition operations, a counter circuit 521 having a count enable terminal, and a counter circuit 522 having a counter enable terminal and a preset terminal.
, AND circuits 523 and 524, and a NOT circuit 525. Note that the description of the same components as those in FIGS.
【００３５】以上のように構成された分周器について、
以下実施例１、２、３と異なる動作いついて説明する。Regarding the frequency divider configured as described above,
The operation different from the first, second and third embodiments will be described below.
【００３６】まず、パルス制御回路５０３において、パ
ルス制御回路５０２のパルス除去信号をカウンタ回路５
１７のカウント・イネーブル入力とすることで、パルス
制御回路５０２でパルス除去またはパルス付加の対象と
なる入力パルスは、カウンタ回路５１７でカウントされ
ず、パルス制御回路５０３の動作に影響しない。First, in the pulse control circuit 503, the pulse removal signal of the pulse control circuit 502 is supplied to the counter circuit 5.
With the count enable input of 17, the input pulse to be pulse-removed or pulse-added by the pulse control circuit 502 is not counted by the counter circuit 517 and does not affect the operation of the pulse control circuit 503.
【００３７】一方、パルス制御回路５０４において、パ
ルス制御回路５０２、５０３のパルス除去信号出力の論
理積をＡＮＤ回路５１１でとり、カウンタ回路５２１、
５２２のカウント・イネーブル端子入力とすることで、
パルス制御回路５０２、５０３のいずれかでパルス除去
またはパルス付加の対象となるパルスは、カウンタ回路
５２１、５２２でカウントされず、パルス制御回路５０
４の動作に影響しない。On the other hand, in the pulse control circuit 504, the AND circuit 511 calculates the logical product of the pulse removal signal outputs of the pulse control circuits 502 and 503, and the counter circuit 521,
By inputting the count enable terminal of 522,
The pulse to be removed or added by any of the pulse control circuits 502 and 503 is not counted by the counter circuits 521 and 522, and the pulse control circuit 50 does not count.
4 does not affect the operation.
【００３８】上記動作により、カウンタ回路５１３、５
１７、５２１、５２２の設定がそれぞれＭ１、Ｍ２、Ｍ
３、Ｃ３で、Ｍ３／Ｃ３を切り上げた整数をｎ３とおく
とき、すでにパルス除去およびパルス付加の対象となっ
たパルスは、後段のパルス制御回路の動作には影響せ
ず、分周器５０１の分周数は切替信号入力端子５１２、
５１６、５２０の入力にしたがって、２×Ｍ１／（Ｍ１
±１）×Ｍ２／（Ｍ２±１）×Ｍ３／（Ｍ３±ｎ）の値
をとる。By the above operation, the counter circuits 513, 5
The settings of 17, 521 and 522 are M1, M2 and M, respectively.
When the integer obtained by rounding up M3 / C3 in 3 and C3 is set to n3, the pulse already subjected to pulse removal and pulse addition does not affect the operation of the pulse control circuit in the subsequent stage, and the pulse of the frequency divider 501 of The frequency division number is the switching signal input terminal 512,
According to the input of 516 and 520, 2 × M1 / (M1
The value is ± 1) × M2 / (M2 ± 1) × M3 / (M3 ± n).
【００３９】以上のように本実施例の分周器によれば、
カウント・イネーブル端子を備えたカウンタ回路で構成
されたパルス制御回路を用いることで、分周数が個々の
パルス制御回路を構成するカウンタ回路の設定値により
容易に表される多段構成の分周器を実現できる。As described above, according to the frequency divider of this embodiment,
By using a pulse control circuit composed of a counter circuit having a count enable terminal, the frequency division number is easily expressed by the setting value of the counter circuit which constitutes each pulse control circuit. Can be realized.
【００４０】[0040]
【発明の効果】以上のように本発明は、パルス制御回路
と、パルス付加回路と、パルス除去回路を設けること
で、パルス除去、あるいはパルス付加を行い分周数の分
子および分母を制御し、本発明の分周器を用いること
で、周波数設定精度が高く、かつ、チャンネル切替時間
の短いＰＬＬ周波数シンセサイザの実現を可能にするも
のである。As described above, according to the present invention, the pulse control circuit, the pulse addition circuit, and the pulse removal circuit are provided to perform pulse removal or pulse addition to control the numerator and denominator of the frequency division number, By using the frequency divider of the present invention, it is possible to realize a PLL frequency synthesizer with high frequency setting accuracy and short channel switching time.
【図１】本発明の第１の実施例における分周器のブロッ
ク結線図FIG. 1 is a block connection diagram of a frequency divider according to a first embodiment of the present invention.
【図２】本発明の第１の実施例における分周器の動作タ
イミング図FIG. 2 is an operation timing chart of the frequency divider according to the first embodiment of the present invention.
【図３】（ａ）本発明の第２の実施例における分周器の
ブロック結線図 （ｂ）本発明の第２の実施例における分周器の動作タイ
ミング図FIG. 3A is a block connection diagram of a frequency divider according to a second embodiment of the present invention. FIG. 3B is an operation timing chart of a frequency divider according to a second embodiment of the present invention.
【図４】本発明の第３の実施例における分周器のブロッ
ク結線図FIG. 4 is a block connection diagram of a frequency divider according to a third embodiment of the present invention.
【図５】本発明の第４の実施例における分周器のブロッ
ク結線図FIG. 5 is a block connection diagram of a frequency divider according to a fourth embodiment of the present invention.
【図６】（ａ）従来の分数の分周数をもつ分周器のブロ
ック結線図 （ｂ）従来の分数の分周数をもつ分周器の動作タイミン
グ図FIG. 6A is a block connection diagram of a frequency divider having a conventional fractional division number; and FIG. 6B is an operation timing diagram of a frequency divider having a conventional fractional frequency division number.
１０１ 分周器 １０２ パルス制御回路 １０３ パルス除去回路 １０４ パルス付加回路 １０７ 切替信号入力端子 ３０４ カウンタ回路 ５１７ カウンタ回路 ５２２ カウンタ回路 101 frequency divider 102 pulse control circuit 103 pulse removal circuit 104 pulse addition circuit 107 switching signal input terminal 304 counter circuit 517 counter circuit 522 counter circuit
Claims (5)
とパルス付加信号を出力するパルス制御回路と、前記パ
ルス除去信号で制御されてパルス除去を行なうパルス除
去回路と、前記パルス付加信号で制御されてパルス付加
を行なうパルス付加回路とを具備する分周器。1. A pulse control circuit which counts an input signal and outputs a pulse removal signal and a pulse addition signal, a pulse removal circuit which is controlled by the pulse removal signal to perform pulse removal, and a pulse addition signal which is controlled by the pulse addition signal. And a pulse adding circuit for adding pulses.
加動作を切り替える信号を入力する切替信号入力端子
と、前記切替信号入力端子の入力で前記カウンタの出力
を制御するゲート回路とでパルス制御回路が構成され、
前記カウンタの出力をパルス除去信号として用い、前記
ゲート回路の出力をパルス付加信号として用いることを
特徴とする請求項１記載の分周器。2. A pulse control circuit comprising a counter, a switching signal input terminal for inputting a signal for switching a pulse removing operation and a pulse adding operation, and a gate circuit for controlling the output of the counter by the input of the switching signal input terminal. Composed,
The frequency divider according to claim 1, wherein the output of the counter is used as a pulse removal signal and the output of the gate circuit is used as a pulse addition signal.
と、前記第１のカウンタ出力を入力とするプリセット端
子を備え前記入力信号をカウントする第２のカウンタ
と、前記第１、第２のカウンタの出力を合成する加算器
と、パルス除去動作とパルス付加動作を切り替える信号
を入力する切替信号入力端子と、前記切替信号入力端子
の入力に従い前記加算器の出力を制御するゲート回路で
パルス制御回路が構成され、複数のパルスを除去または
付加することを特徴とする請求項１記載の分周器。3. A first counter that counts an input signal, a second counter that includes a preset terminal that receives the output of the first counter, and a second counter that counts the input signal, and the first and second counters. Pulse synthesizer, a switching signal input terminal for inputting a signal for switching between pulse removal operation and pulse addition operation, and a gate circuit for controlling the output of the adder according to the input of the switching signal input terminal. 2. The frequency divider according to claim 1, wherein the frequency divider is configured to remove or add a plurality of pulses.
御回路のパルス除去信号出力を合成する加算器と、前記
パルス制御回路のパルス付加信号出力を合成する加算器
を備えたことを特徴とする請求項１記載の分周器。4. A plurality of pulse control circuits, an adder for synthesizing pulse removal signal outputs of the pulse control circuit, and an adder for synthesizing pulse addition signal outputs of the pulse control circuit. The frequency divider according to claim 1.
ンタでパルス制御回路が構成され、前段のパルス制御回
路のパルス除去信号出力を合成した信号を前記カウント
・イネーブル端子に入力することを特徴とする請求項４
記載の分周器。5. A pulse control circuit is configured by a counter having a count enable terminal, and a signal obtained by combining the pulse removal signal outputs of the preceding pulse control circuit is input to the count enable terminal. Item 4
The described divider.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24784793A JP3435751B2 (en) | 1993-10-04 | 1993-10-04 | Divider |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24784793A JP3435751B2 (en) | 1993-10-04 | 1993-10-04 | Divider |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07106953A true JPH07106953A (en) | 1995-04-21 |
| JP3435751B2 JP3435751B2 (en) | 2003-08-11 |
Family
ID=17169551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24784793A Expired - Fee Related JP3435751B2 (en) | 1993-10-04 | 1993-10-04 | Divider |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3435751B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7936996B2 (en) | 2005-08-24 | 2011-05-03 | National Institute Of Information And Communications Technology | Automatic adjusting system of frequency shift keying modulator |
| US7957653B2 (en) | 2005-09-20 | 2011-06-07 | National Institute Of Information And Communications Technology | Phase control optical FSK modulator |
-
1993
- 1993-10-04 JP JP24784793A patent/JP3435751B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7936996B2 (en) | 2005-08-24 | 2011-05-03 | National Institute Of Information And Communications Technology | Automatic adjusting system of frequency shift keying modulator |
| US7957653B2 (en) | 2005-09-20 | 2011-06-07 | National Institute Of Information And Communications Technology | Phase control optical FSK modulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3435751B2 (en) | 2003-08-11 |
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