JPH0695534B2 - Heterostructure semiconductor device and manufacturing method thereof - Google Patents
Heterostructure semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0695534B2 JPH0695534B2 JP1263208A JP26320889A JPH0695534B2 JP H0695534 B2 JPH0695534 B2 JP H0695534B2 JP 1263208 A JP1263208 A JP 1263208A JP 26320889 A JP26320889 A JP 26320889A JP H0695534 B2 JPH0695534 B2 JP H0695534B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- buffer layer
- inx
- doped
- ingaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 産業上の利用分野 本発明はヘテロ構造半導体装置およびその製造方法に関
するものである。The present invention relates to a heterostructure semiconductor device and a method for manufacturing the same.
従来の技術 ノンドープのGaAs層上にＮ型のAlGaAs層を形成したヘテ
ロ構造のヘテロ接合界面には高い移動度の２次元電子ガ
スが形成される。この２次元電子ガスの濃度をゲート電
極により制御してトランジスタ動作をさせる電子移動度
トランジスタ（HEMT）は、高速スイッチング素子、マイ
クロ波・ミリ波素子として有望であり、その特性を一層
向上させるための材料面、構造面からの多くの研究が盛
んに行われている。材料面からは、GaAsのかわりにInP
を基板として用い、InPに格子整合したIn0.53Ga0.47As
とＮ型のIn0.52Al0.48Asよりなるヘテロ構造が、GaAs/A
lGaAs系のHEMTよりも高い電子移動度、高い電子飽和速
度および高い２次元電子ガス濃度を示すため、AlGaAs/G
aAs系HEMTにかわる高性能HEMTを実現できるものとして
注目されている。しかしながら、基板として用いるInP
は現在のところGaAsに比較して高価であること、基板の
品質がGaAsに比べて劣ること、不要な不純物がInP基板
上に形成された結晶層に取り込まれること、またGaAsよ
り割れ易いなどの不利な点を有している。このことか
ら、より結晶品質に優れたGaAs基板を用いてInGaAsやIn
AlAsを良好な結晶品質で結晶成長できるような新しい技
術が望まれている。このような技術は受光・発光デバイ
スと高速電子デバイスの集積回路を作製する上でも重要
である。InGaAsやInAlAs基板上に形成する場合に問題と
なるのは、InGaAsやInAlAsとGaAsとの格子定数の差異で
あり、InAs組成比が0.53の場合3.8％と非常に大きい。
このため、通常の手段でInGaAsをGaAs上に形成した場合
には、InGaAs層中に多数のディスロケーションが生じ、
その結晶性は著しく低下する。本発明者らは、InAs組成
比ＸをGaAs基板側からInGaAsを含む活性層側へ徐々に増
加させたInxGa1-xAsバッファー層を用いることにより、
活性層の結晶性を著しく向上せしめることが可能である
ことを見出した。このInxGa1-xAsバッファー層を通常の
分子線エピタキシー法で結晶成長する場合、成長温度と
して450℃以下の温度を採用することを、InxGa1-xAsバ
ッファー層の成長方向におけるInAs組成比Ｘを1.5x10-3
/nm以下とすることにより活性層の結晶性は更に良好と
なることを見出した。第２図にこのような方法を用いて
形成したHEMT構造の断面を示す。第２図において１は半
絶縁性GaAs基板、２は膜厚が200mm程度のノンドープGaA
s層であり、この上にInAs組成比が０から例えば0.5まで
変化するInxGa1-xAsバッファー層13が形成される。0.5
というInAs組成はInxGa1-xAsバッファー層13上に形成さ
れる活性層のうちのInGaAsチャンネル層５におけるInAs
組成比と等しくなるように決められるもので、特にこの
値に限定されることはない。このInxGa1-xAsバッファー
層13上にノンドープのInAlAsバリア層４が形成される。
InAlAsバリア層４のInAs組成InxGa1-xAsバッファー層13
の最表面側のInAs組成（いまの場合0.5）で決定される
れる。In0.5Ga0.5Asの格子定数とほぼ一致するように決
められる。このInAlAsバリア層４より表面側の各層5,6,
7,8,9は格子整合する条件で形成される。５はノンドー
プInGaAsチャンネル層で厚さが20nm〜100nmのものが用
いられる。６は厚さ3nm程度のノンドープInGaAs層、７
は厚さ25nm程度のＮ型InAlAs層、８は厚さ10nm程度のノ
ンドープInAlAs層、９は厚さ10nm〜50nm程度のＮ型InGa
As層である。2. Description of the Related Art A two-dimensional electron gas with high mobility is formed at a heterojunction interface of a heterostructure in which an N-type AlGaAs layer is formed on a non-doped GaAs layer. The electron mobility transistor (HEMT), which controls the concentration of the two-dimensional electron gas by a gate electrode to operate as a transistor, is promising as a high-speed switching device and a microwave / millimeter wave device. To further improve its characteristics, Much research has been done actively from the material and structural aspects. From the material side, InP instead of GaAs
In 0.53 Ga 0.47 As lattice-matched to InP using
And n-type In 0.52 Al 0.48 As heterostructure is GaAs / A
AlGaAs / G has a higher electron mobility, higher electron saturation rate and higher two-dimensional electron gas concentration than HEMTs of lGaAs system.
It is attracting attention as a material that can realize high-performance HEMTs that replace aAs HEMTs. However, InP used as a substrate
Is currently more expensive than GaAs, the substrate quality is inferior to GaAs, unnecessary impurities are incorporated into the crystal layer formed on the InP substrate, and it is more easily cracked than GaAs. Has disadvantages. From this, it is possible to use InGaAs or In
There is a demand for a new technique capable of growing AlAs with good crystal quality. Such technology is also important in manufacturing integrated circuits of light receiving / light emitting devices and high-speed electronic devices. The problem when forming on InGaAs or InAlAs substrates is the difference in lattice constant between InGaAs and InAlAs and GaAs, which is very large at 3.8% when the InAs composition ratio is 0.53.
Therefore, when InGaAs is formed on GaAs by the usual means, many dislocations occur in the InGaAs layer,
Its crystallinity is significantly reduced. The present inventors use the InxGa 1-x As buffer layer in which the InAs composition ratio X is gradually increased from the GaAs substrate side to the active layer side containing InGaAs.
It was found that it is possible to significantly improve the crystallinity of the active layer. When crystal growth of this InxGa 1-x As buffer layer is performed by a normal molecular beam epitaxy method, it is necessary to adopt a temperature of 450 ° C. or lower as the growth temperature of the InxGa 1-x As buffer layer. To 1.5x10 -3
It was found that the crystallinity of the active layer is further improved by controlling the ratio to be / nm or less. FIG. 2 shows a cross section of a HEMT structure formed using such a method. In FIG. 2, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaA having a film thickness of about 200 mm.
An InxGa 1-x As buffer layer 13 which is an s layer and on which an InAs composition ratio changes from 0 to 0.5, for example, is formed. 0.5
InAs composition is InAs in the InGaAs channel layer 5 of the active layer formed on the InxGa 1-x As buffer layer 13.
It is determined so as to be equal to the composition ratio, and is not particularly limited to this value. A non-doped InAlAs barrier layer 4 is formed on the InxGa 1-x As buffer layer 13.
InAs composition of InAlAs barrier layer 4 InxGa 1-x As buffer layer 13
Is determined by the InAs composition (0.5 in this case) on the outermost surface side of. It is determined so as to almost match the lattice constant of In 0.5 Ga 0.5 As. The layers 5, 6 on the surface side of the InAlAs barrier layer 4,
7,8,9 are formed under the condition of lattice matching. Reference numeral 5 is a non-doped InGaAs channel layer having a thickness of 20 nm to 100 nm. 6 is a non-doped InGaAs layer having a thickness of about 3 nm, 7
Is an N-type InAlAs layer with a thickness of about 25 nm, 8 is an undoped InAlAs layer with a thickness of about 10 nm, and 9 is an N-type InGa with a thickness of about 10 nm to 50 nm.
It is the As layer.
この構造においてノンドープInGaAsチャンネル層５にＮ
型InAlAs層７から電子が供給され、高移動度の２次元電
子ガスがInGaAsチャンネル層５に形成される。実際に測
定される２次元電子ガスの移動度は、InGaAsチャンネル
層５のInAs組成が0.5の場合、室温で9000〜10000cm2/v
・ｓと良好な値を示す。In this structure, N is added to the undoped InGaAs channel layer 5.
Electrons are supplied from the type InAlAs layer 7 and a two-dimensional electron gas with high mobility is formed in the InGaAs channel layer 5. The mobility of the two-dimensional electron gas actually measured is 9000 to 10000 cm 2 / v at room temperature when the InAs composition of the InGaAs channel layer 5 is 0.5.
・ S shows a good value.
発明が解決しようとする課題 従来例で示した構造における２次元電子ガスの移動度は
高く、活性層の結晶性は非常に良好であるが、実際にこ
の構造を用いて電界効果型トランジスタ（FET）を作製
すると次のような問題が生じることが明らかとなった。
すなわち、FETを作製する際に、素子形成のための島領
域を選択的に残して、他の領域は第２図のノンドープIn
AlAsバリア層４の付近までエッチング除去されるが、そ
れぞれの島領域間でリーク電流が流れ、素子分離が難し
いこと、この基板に流れるリーク電流のため、FETのピ
ンチオフ特性が良くないということが明らかとなった。Problems to be Solved by the Invention Although the mobility of the two-dimensional electron gas in the structure shown in the conventional example is high and the crystallinity of the active layer is very good, actually, this structure is used to actually produce a field effect transistor (FET). It has been revealed that the following problems occur when (1) is produced.
That is, when the FET is manufactured, the island regions for element formation are selectively left, and the other regions are left undoped In
Although it is removed by etching up to the vicinity of the AlAs barrier layer 4, it is clear that the pinch-off characteristic of the FET is not good due to the leak current flowing between the island regions, making it difficult to isolate the device and the leak current flowing through this substrate. Became.
課題を解決するための手段 このような基板リーク電流の原因として考えられる事
は、InxGa1-xAsバッファー層13のエネルギーバンドギャ
ップがGaAsに比べ小さく、InAs組成Ｘが大きくなる程小
さくなるという事である。実際に、第２図の従来例にお
いてＮ型InAlAs層７およびＮ型InGaAs層９をＮ型とせ
ず、ノンドープとし、試料を作製すると、すべての層が
ノンドープであるにもかかわらず、試料中には1x1012／
cm2の面密度でキャリア（電子）が存在していることが
判明した。この残留キャリアの原因としては、ノンドー
プ層でも1015／cm3程度のドーピングが実際には自然に
される事や、格子不整合を緩和するためのInxGa1-xAsバ
ッファー層13内に多数発生する格子欠陥に関連したキャ
リアの発生などが考えられるが、本発明者らは、InxGa
1-xAsバッファー層13のエネルギーバンドキャップが本
来小さいという事が、主原因であると推定し、InxGa1-x
Asバッファー層13のかわりに、より大きなエネルギーバ
ンドギャップを有する材料であるInx（GayAl1-y）1-xAs
四元混晶を用いることを考案した。本発明は、GaAs基板
上に結晶性の良いInGaAs層を形成する場合に、GaAsとIn
GaAsの格子不整合を緩和するために、In,Ga,Alの組成が
基板側から目的のInGaAs層まで徐々に変化するInx（Gay
Al1-y）1-xAs四元混晶のバッファー層を用いるものであ
る。Means for Solving the Problems The possible cause of such substrate leakage current is that the energy band gap of the InxGa 1-x As buffer layer 13 is smaller than that of GaAs, and becomes smaller as the InAs composition X increases. Is. Actually, in the conventional example of FIG. 2, the N-type InAlAs layer 7 and the N-type InGaAs layer 9 were not doped with N-type and were undoped. Is 1x10 12 /
It was found that carriers (electrons) exist at an areal density of cm 2 . The cause of this residual carrier is that the doping of about 10 15 / cm 3 is actually natural even in the non-doped layer, and a large number is generated in the InxGa 1-x As buffer layer 13 for relaxing the lattice mismatch. Occurrence of carriers related to the lattice defects that occur is considered.
It is estimated that the main cause is that the energy band cap of the 1-x As buffer layer 13 is originally small, and InxGa 1-x
Instead of As buffer layer 13, Inx (GayAl 1-y ) 1-x As, which is a material with a larger energy band gap
We devised to use a quaternary mixed crystal. The present invention is applicable to GaAs and In when forming an InGaAs layer with good crystallinity on a GaAs substrate.
To reduce the lattice mismatch of GaAs, the composition of In, Ga, Al gradually changes from the substrate side to the target InGaAs layer.
Al 1-y ) 1-x As Quaternary mixed crystal buffer layer is used.
作用 従来のInxGa1-xAsバッファー層に比べ、エネルギーバン
ドギャップの大きなInx（GayAl1-y）1-xAs四元混晶のバ
ッファー層を用いることにより、残留キャリア濃度を著
しく低下させることが可能となり、基板リーク電流を抑
制し素子分離が容易となるばかりでなく、FETのピンチ
オフ特性も改善できる。本発明により、GaAs基板上に形
成したInGaAs活性層を用いて、特性の良好なFETおよ
び、これを用いた集積回路を実現できる。Action The residual carrier concentration can be significantly reduced by using the Inx (GayAl 1-y ) 1-x As quaternary mixed crystal buffer layer with a larger energy band gap than the conventional InxGa 1-x As buffer layer. This not only makes it possible to suppress substrate leakage current and facilitate element isolation, but also improves the FET pinch-off characteristics. According to the present invention, an InGaAs active layer formed on a GaAs substrate can be used to realize an FET having excellent characteristics and an integrated circuit using the FET.
実施例 本発明の実施例を第１図に従って詳細に述べる。第１図
は、本発明のヘテロ構造の断面図であり、１は半絶縁性
GaAs基板、２はノンドープGaAs層で省いても良いもので
ある。３は、本発明の中心となるノンドープInx（GayAl
1-y）1-xAsバッファー層、４は層厚が200nm程度のノン
ドープInGaAsバリア層、５は層厚が200nm〜100nm程度の
ノンドープInAlAsチャンネル層（あるいは活性層）、６
は、ノンドープInAlAsスペーサ層で層厚は０〜10nm程度
のもの、７はSi不純物を1x1018〜1x1019／cm3程度ドー
プした厚さが10〜30nm程度のＮ型InAlAs層、８はショッ
トキー電極を得るための10〜30nm程度の厚さのノンドー
プInAlAs層、９はSi不純物を1x1018〜1x1019／cm3程度
ドープしたＮ型InGaAs層である。この構造において、Ｎ
型InAlAs層７より電子がノンドープのInGaAsチャンネル
層５に供給され、移動度の大きい２次元電子ガスが、ノ
ンドープInGaAsチャンネル層５内に形成される。第１図
のヘテロ構造の分子線エピタキシー（MBE）法で作製す
る場合、結晶成長時の基板温度は重要であり、Inx（Gay
Al1-y）1-xAsバッファ層３を形成する時は従来例と同様
に450℃以下、ノンドープInAlAsバリア層４より上の5,
6,7,8,9の各層を形成する時は500℃程度がよいことがわ
かった。特にバッファー層３の成長温度は重要であり、
450℃以上の温度では表面モホロジー及び電子移動度の
低下が著しいことが実験により明らかとなった。Inx（G
ayAl1-y）1-xAsバッファー層３のInAs組成Ｘは、GaAs基
板１側で０とし、ノンドープInAlAsバリア層４側でInAl
As層４とほぼ格子整合する値Ｚとし、ＯからＺまでほぼ
直線的に変化させた。Ｘの変化率も目的のノンドープの
InGaAsチャンネル層５の結晶性に大きな影響を及ぼす
が、バッファー層厚100nm当り0.15の変化率、すなわち
1.5x10-3/nm、以下とする必要がある。通常、Ｚ＝0.5の
時に800nmのバッファー層厚を用いた、つまり〜6x10-4/
nmの変化率とした。一方、Ｙの値については、GaAlAsの
格子不整合が無視できる程に小さいので０〜１までの任
意の値を設定することができる。Ｙの値をInx（GayAl
1-y）1-xAsバッファー層内で固定しても良いし、変化さ
せても良く、特にＹの値に関しては制限はない。本実施
例では、Ｙの値をGaAs基板側で１とし、ノンドープInAl
Asバリア層４側で０となるように、１から０までInx（G
ayAl1-y）1-xAsバッファー層３内でほぼ直線的に変化さ
せた。本発明によれば、ノンドープのInGaAsチャンネル
層５のInAs組成Ｚは、０から１まで任意に変化させ得る
が、実際には0.2≦Ｚ≦0.7程度の範囲が応用上重要とな
る。本発明のInx（GayAl1-y）1-xAsバッファー層３の効
果を示す実験データとしてＺ＝0.53の場合を一例として
示す。本発明の目的である基板リーク電流の抑制あるい
は残留キャリア濃度の低減を示すために、第１図および
第２図におけるＮ型InAlAs層７及びＮ型InGaAs層９のSi
不純物ドープ量を0/cm3としヘテロ構造の各層がすべて
ノンドープである構造を作製し、残留キャリア濃度を調
べた。その結果を次表に示す。Embodiment An embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a cross-sectional view of the heterostructure of the present invention, where 1 is semi-insulating.
The GaAs substrate 2 and the non-doped GaAs layer 2 may be omitted. 3 is the non-doped Inx (GayAl
1-y ) 1-x As buffer layer, 4 is a non-doped InGaAs barrier layer having a layer thickness of about 200 nm, 5 is a non-doped InAlAs channel layer (or active layer) having a layer thickness of about 200 nm to 100 nm, 6
Is a non-doped InAlAs spacer layer having a layer thickness of about 0 to 10 nm, 7 is an N-type InAlAs layer having a thickness of about 10 to 30 nm doped with Si impurities of about 1x10 18 to 1x10 19 / cm 3 , and 8 is a Schottky A non-doped InAlAs layer having a thickness of about 10 to 30 nm for obtaining an electrode, and 9 is an N-type InGaAs layer doped with Si impurities at about 1 × 10 18 to 1 × 10 19 / cm 3 . In this structure, N
Electrons are supplied from the type InAlAs layer 7 to the non-doped InGaAs channel layer 5, and a two-dimensional electron gas having high mobility is formed in the non-doped InGaAs channel layer 5. When the heterostructure molecular beam epitaxy (MBE) method shown in Fig. 1 is used, the substrate temperature during crystal growth is important.
When the Al 1-y ) 1-x As buffer layer 3 is formed, as in the conventional example, the temperature is 450 ° C. or lower, and the temperature above the undoped InAlAs barrier layer 4 is 5,
It was found that about 500 ℃ is good for forming each layer of 6,7,8,9. Especially, the growth temperature of the buffer layer 3 is important,
Experiments have shown that the surface morphology and electron mobility decrease significantly at temperatures above 450 ℃. Inx (G
a y Al 1-y ) 1-x As The InAs composition X of the buffer layer 3 is set to 0 on the GaAs substrate 1 side and InAl on the undoped InAlAs barrier layer 4 side.
The value Z was set so as to be substantially lattice-matched with the As layer 4, and was changed substantially linearly from O to Z. The change rate of X is
The crystallinity of the InGaAs channel layer 5 is greatly affected, but the change rate of 0.15 per 100 nm of the buffer layer, that is,
It should be 1.5x10 -3 / nm or less. Usually a buffer layer thickness of 800 nm was used when Z = 0.5, ie ~ 6x10 -4 /
The rate of change was nm. On the other hand, the value of Y can be set to any value from 0 to 1 because the lattice mismatch of GaAlAs is so small that it can be ignored. The value of Y is Inx (GayAl
1-y ) 1-x As It may be fixed in the buffer layer or may be changed, and there is no particular limitation on the value of Y. In this embodiment, the value of Y is set to 1 on the GaAs substrate side, and non-doped InAl is used.
As 1 to 0, Inx (G
ayAl 1-y ) 1-x As buffer layer 3 was changed substantially linearly. According to the present invention, the InAs composition Z of the undoped InGaAs channel layer 5 can be arbitrarily changed from 0 to 1, but in practice, a range of 0.2 ≦ Z ≦ 0.7 is important for application. As an experimental data showing the effect of the Inx (GayAl 1-y ) 1-x As buffer layer 3 of the present invention, the case of Z = 0.53 is shown as an example. In order to show the suppression of the substrate leakage current or the reduction of the residual carrier concentration, which is the object of the present invention, the Si of the N-type InAlAs layer 7 and the N-type InGaAs layer 9 in FIGS.
A structure in which each layer of the heterostructure was undoped with the impurity doping amount of 0 / cm 3 was prepared, and the residual carrier concentration was investigated. The results are shown in the table below.
次表から明らかな様に、残留キャリア濃度は、従来のIn
xGa1-xAsバッファー層を用いた時に比べ本発明のInx（G
ayAl1-y）1-xAsバッファー層を用いた場合は、約1/10に
低下していることがわかる。測定された移動度の値は従
来の場合の方が高くなっているが、これは本発明の結晶
性が従来に比べ劣っているためではなく、残留キャリア
の依存する場所と濃度に移動度の値が依存するためであ
る。実際に、第１図の構造において、Ｎ型InAlAs層７と
Ｎ型InAlAs層９にSiを2x1018／cm3ドープして２次元電
子ガスをノンドープのInGaAsチャンネル層５内に形成す
ると、キャリア濃度として、〜2x1012／cm2、移動度と
して室温において10000cm2/v・ｓの良好な値が得られ
た。また本発明のヘテロ構造を用いてFET（HEMT）を作
製した時、メサエッチングにより形成した素子形成のた
めの島領域間でのリーク電流は、従来構造の場合に比べ
1/20〜1/100程度に減少することも確認できた。 As is clear from the table below, the residual carrier concentration is
Compared to the case of using the xGa 1-x As buffer layer, the Inx (G
It can be seen that when the ayAl 1-y ) 1-x As buffer layer is used, it is reduced to about 1/10. Although the measured mobility value is higher in the conventional case, this is not because the crystallinity of the present invention is inferior to the conventional one, but the mobility and the location depend on the residual carrier and the concentration. This is because the value depends on it. Actually, in the structure of FIG. 1, when the N-type InAlAs layer 7 and the N-type InAlAs layer 9 were doped with Si at 2 × 10 18 / cm 3 to form a two-dimensional electron gas in the non-doped InGaAs channel layer 5, the carrier concentration was increased. as, ~2x10 12 / cm 2, at room temperature as a mobility satisfactory value of 10000cm 2 / v · s was obtained. In addition, when a FET (HEMT) is manufactured using the heterostructure of the present invention, the leakage current between island regions for device formation formed by mesa etching is higher than that of the conventional structure.
It was also confirmed that it decreased to about 1/20 to 1/100.
発明の効果 以上述べた様に、本発明のGaAs基板側よりInAs組成が徐
々に増加するInx（GayAl1-y）1-xAsバッファー層を用い
ることによりGaAs基板上に結晶性の良好なInGaAs層を活
性層とするヘテロ構造を形成できるばかりでなく、残留
キャリア濃度の低減と基板リーク電流の抑制が著しく図
られGaAs上に形成したInGaAs/InAlAs系の電気デバイス
の特性向上とそれらの集積比が可能となるなどの効果が
ある。また、本発明の実施例では主にHEMTについて述べ
たが、本発明の適用範囲はこれに限られるものではな
く、MESFETやHBTなどの電気デバイス、受光素子などの
光デバイスへの対応も可能であることは言うまでもな
い。EFFECTS OF THE INVENTION As described above, the use of the Inx (GayAl 1-y ) 1-x As buffer layer in which the InAs composition is gradually increased from the GaAs substrate side of the present invention makes InGaAs having good crystallinity on the GaAs substrate. In addition to being able to form a heterostructure with the active layer as the active layer, it is possible to significantly reduce the residual carrier concentration and suppress the substrate leakage current, and to improve the characteristics of the InGaAs / InAlAs-based electric devices formed on GaAs and their integration ratio. There is an effect that it becomes possible. Further, although the HEMT is mainly described in the embodiments of the present invention, the applicable range of the present invention is not limited to this, and it is possible to correspond to an optical device such as an electric device such as MESFET or HBT and a light receiving element. Needless to say.
第１図は本発明の実施例を説明するためのヘテロ構造断
面図、第２図は従来例を説明するためのヘテロ構造断面
図である。 １……半絶縁性GaAs基板、２……ノンドープGaAs層、３
……Inx（GayAl1-y）1-xAsバッファー層、４……ノンド
ープInAlAsバリア層、５……ノンドープのInGaAsチャン
ネル層、６……ノンドープInAlAsスペーサ層、７……Ｎ
型InAlAs層、８……ノンドープInAlAs層、９……Ｎ型In
GaAs層。FIG. 1 is a sectional view of a hetero structure for explaining an embodiment of the present invention, and FIG. 2 is a sectional view of a hetero structure for explaining a conventional example. 1 ... Semi-insulating GaAs substrate, 2 ... Non-doped GaAs layer, 3
…… Inx (GayAl 1-y ) 1-x As buffer layer, 4 …… non-doped InAlAs barrier layer, 5 …… non-doped InGaAs channel layer, 6 …… non-doped InAlAs spacer layer, 7 …… N
Type InAlAs layer, 8 ... Non-doped InAlAs layer, 9 ... N type In
GaAs layer.
Claims (2)
ァー層を介してInzGa1-zAsを含む活性層が形成されてな
る半導体ヘテロ構造において、前記Inx（AlyGa1-y）1-x
Asバッファー層のInAs組成比ＸがGaAs基板側から前記活
性層の間でＯからＺまで厚さ方向に対してほぼ直線的に
変化し、かつＸの変化率が1.5x10-3/nm以下であること
を特徴とするヘテロ構造半導体装置。1. A semiconductor heterostructure in which an active layer containing In z Ga 1-z As is formed on a GaAs substrate via an Inx (AlyGa 1-y ) 1-x As buffer layer. 1-y ) 1-x
The InAs composition ratio X of the As buffer layer changes substantially linearly in the thickness direction from O to Z between the GaAs substrate side and the active layer, and the change rate of X is 1.5x10 -3 / nm or less. A heterostructure semiconductor device characterized by being present.
厚みと共にほぼ直線的にかつ1.5x10-3/nm以下の変化率
で変化せしめたInx（AlyGa1-y）1-xAsバッファー層を形
成する工程と、このInx（AlyGa1-y）1-xAsバッファー層
上にInzGa1-zAsを含む活性層を形成する工程とを少なく
とも含み、かつ、前記Inx（AlyGa1-y）1-xAsバッファー
層と前記活性層が分子線エピタキシー法により、450℃
以下の成長温度で形成されることを特徴とするヘテロ構
造半導体装置の製造方法。2. Inx (AlyGa 1-y ) 1-x As on a GaAs substrate in which the InAs composition ratio X is changed substantially linearly with thickness from O to Z at a rate of change of 1.5 × 10 -3 / nm or less. At least a step of forming a buffer layer and a step of forming an active layer containing InzGa 1-z As on the Inx (AlyGa 1-y ) 1-x As buffer layer, and the Inx (AlyGa 1- y ) The 1-x As buffer layer and the active layer were processed by molecular beam epitaxy at 450 ° C.
A method for manufacturing a heterostructure semiconductor device, which is formed at the following growth temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263208A JPH0695534B2 (en) | 1989-10-09 | 1989-10-09 | Heterostructure semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1263208A JPH0695534B2 (en) | 1989-10-09 | 1989-10-09 | Heterostructure semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03125436A JPH03125436A (en) | 1991-05-28 |
| JPH0695534B2 true JPH0695534B2 (en) | 1994-11-24 |
Family
ID=17386285
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1263208A Expired - Fee Related JPH0695534B2 (en) | 1989-10-09 | 1989-10-09 | Heterostructure semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0695534B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100233830B1 (en) * | 1996-08-28 | 1999-12-01 | 정선종 | E-mesfet and d-mesfet and manufacturing method thereof |
| US6489639B1 (en) * | 2000-05-24 | 2002-12-03 | Raytheon Company | High electron mobility transistor |
-
1989
- 1989-10-09 JP JP1263208A patent/JPH0695534B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03125436A (en) | 1991-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2817995B2 (en) | III-V compound semiconductor heterostructure substrate and III-V compound heterostructure semiconductor device | |
| KR19980034078A (en) | Hot Electron Device and Resonant Tunneling Hot Electronic Device | |
| US5952672A (en) | Semiconductor device and method for fabricating the same | |
| US6787826B1 (en) | Heterostructure field effect transistor | |
| US5322808A (en) | Method of fabricating inverted modulation-doped heterostructure | |
| JPH07183494A (en) | Heterojunction fet | |
| US5075744A (en) | GaAs heterostructure having a GaAsy P1-y stress-compensating layer | |
| JPH0695534B2 (en) | Heterostructure semiconductor device and manufacturing method thereof | |
| JPH09237889A (en) | Semiconductor crystal laminate and semiconductor device using the laminate | |
| JP2530496B2 (en) | Semiconductor heterostructure and manufacturing method thereof | |
| US5408111A (en) | Field-effect transistor having a double pulse-doped structure | |
| US6043143A (en) | Ohmic contact and method of manufacture | |
| JP2572484B2 (en) | Field effect transistor | |
| JP2808671B2 (en) | Field effect transistor | |
| JP3158467B2 (en) | InAlAs / InGaAs heterojunction structure field effect transistor | |
| JPH0669248A (en) | Field-effect transistor and manufacture thereof | |
| WO2000007248A1 (en) | High electron mobility transistor | |
| JP2500457B2 (en) | Heterojunction field effect transistor | |
| JPH0684959A (en) | High electron mobility field effect semiconductor device | |
| JPH088354B2 (en) | Heterojunction field effect transistor | |
| JPH028450B2 (en) | ||
| JP4150879B2 (en) | Compound semiconductor epitaxial wafer | |
| JPH04298050A (en) | Heterostructure device having strained carrier supply layer | |
| JPH0645368A (en) | Heterojunction semiconductor device | |
| KR20230090573A (en) | AlGaN/GaN hetero-junction structure of HEMT Device of having multi-strain matching structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |