JPH0691216B2 - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0691216B2 JPH0691216B2 JP61012369A JP1236986A JPH0691216B2 JP H0691216 B2 JPH0691216 B2 JP H0691216B2 JP 61012369 A JP61012369 A JP 61012369A JP 1236986 A JP1236986 A JP 1236986A JP H0691216 B2 JPH0691216 B2 JP H0691216B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- gate electrode
- capacitance
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/34—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
- H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体記憶装置に関し、特に１ビットを記憶す
るためのメモリセル面積が小さくできる一ケのトランジ
スターと一ケの容量から成るダイナミック型ランダムア
クセスメモリ（DRAM）用の新規なメモリセル構造に関す
る。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random number composed of a transistor and a capacitor capable of reducing a memory cell area for storing 1 bit. The present invention relates to a novel memory cell structure for access memory (DRAM).
従来、この種のメモリセル構造は、第５図に示すよう
に、Ｐ型シリコン基板１に形成されたn+層をソース・ド
レインとするMOSトランジスターと、基板上に形成され
た容量膜と容量電極とからなるMOS型容量とが平面上に
並んで構成されている。Conventionally, as shown in FIG. 5, this type of memory cell structure has a MOS transistor having an n + layer formed on a P-type silicon substrate 1 as a source / drain, a capacitor film and a capacitor formed on the substrate. A MOS type capacitor composed of an electrode is arranged side by side on a plane.
〔発明が解決しようとする問題点〕 従来のメモリセル構造は、第５図に示すように平面上に
容量とMOSトランジスターとを並べているので、セル面
積を小さくすることは困難である。最近、容量の面積を
縮小するために、シリコン基板に堀った溝内に容量を形
成する方法が検討されている。しかし、この場合におい
ても、容量部の面積は縮小されるが、依然として容量と
MOSトランジスターとは平面的に配置されているため、
セル面積縮小には限界がある。[Problems to be Solved by the Invention] In the conventional memory cell structure, it is difficult to reduce the cell area because the capacitors and the MOS transistors are arranged on a plane as shown in FIG. Recently, in order to reduce the area of the capacitor, a method of forming the capacitor in a groove dug in a silicon substrate has been studied. However, even in this case, although the area of the capacitance section is reduced,
Since it is arranged in a plane with the MOS transistor,
There is a limit to the reduction of cell area.
本発明の半導体記憶装置は、半導体基板上に形成された
容量膜を介して形成された容量電極と、前記容量電極上
に電気的に絶縁されて形成されたゲート電極と、前記容
量電極および前記ゲート電極上に、前記容量電極と電気
的に接続され前記ゲート電極とは電気的に分離されて形
成された半導体膜とを有し前記半導体膜と前記ゲート電
極とにより電界効果トランジスターが構成されることを
特徴とする。A semiconductor memory device of the present invention includes a capacitance electrode formed via a capacitance film formed on a semiconductor substrate, a gate electrode electrically insulated from the capacitance electrode, the capacitance electrode and the capacitance electrode. A semiconductor film formed on the gate electrode and electrically connected to the capacitance electrode and electrically separated from the gate electrode, and the semiconductor film and the gate electrode form a field effect transistor. It is characterized by
本発明の半導体記憶装置は、容量電極上にトランジスタ
ーおよびトランジスター電極が形成されている。In the semiconductor memory device of the present invention, the transistor and the transistor electrode are formed on the capacitor electrode.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１実施例のメモリセル断面図であ
る。シリコン基板10上の蓄積容量部以外の領域は素子分
離領域12となる。シリコン基板上に容量膜13を介して容
量電極15が形成されており、その上に絶縁膜としてPSG
膜20を介してゲート電極16、その上に再びPSG膜20が形
成されている。ゲート電極としては多結晶シリコン膜を
用いる。ゲート電極16の側面にはゲート膜14が形成され
ている。ゲート電極として多結晶シリコン膜を用いる
と、熱酸化によって容易にゲート酸化膜が形成できる。
半導体層18が容量電極上部のPSG膜20及びゲート電極16
以外の部分に形成されている。半導体層としては、アモ
ルファスシリコン膜、多結晶シリコン膜あるいは再結晶
化されたシリコン膜が使えここではＰ型シリコンを用い
ている。半導体層は容量電極と電気的に接触している必
要がある。ここで絶縁膜として用いたPSG膜からリン拡
散によって半導体層にn+型半導体層17,19が形成でき
る。これによりゲート電極側面にn+型半導体層17,19を
ソース・ドレインとするｎチャンネル型MOSトランジス
ターが実現できる。層間膜21にコンタクト孔が開孔され
て、n+型半導体層19上にビート線22が接続されている。FIG. 1 is a sectional view of a memory cell according to the first embodiment of the present invention. A region other than the storage capacitor portion on the silicon substrate 10 becomes an element isolation region 12. A capacitor electrode 15 is formed on a silicon substrate via a capacitor film 13, and a PSG as an insulating film is formed on the capacitor electrode 15.
The gate electrode 16 is provided via the film 20, and the PSG film 20 is formed thereon again. A polycrystalline silicon film is used as the gate electrode. A gate film 14 is formed on the side surface of the gate electrode 16. When a polycrystalline silicon film is used as the gate electrode, the gate oxide film can be easily formed by thermal oxidation.
The semiconductor layer 18 is the PSG film 20 above the capacitor electrode and the gate electrode 16
It is formed in the other part. As the semiconductor layer, an amorphous silicon film, a polycrystalline silicon film, or a recrystallized silicon film can be used, and P-type silicon is used here. The semiconductor layer needs to be in electrical contact with the capacitor electrode. Here, n + type semiconductor layers 17 and 19 can be formed in the semiconductor layer by phosphorus diffusion from the PSG film used as the insulating film. As a result, an n-channel MOS transistor having the n + type semiconductor layers 17 and 19 as the source / drain on the side surface of the gate electrode can be realized. Contact holes are opened in the interlayer film 21, and the beat line 22 is connected to the n + type semiconductor layer 19.
本発明のメモリセル構造では、信号はシリコン基板10と
容量電極15で構成される蓄積容量に記憶される。信号の
書き込みおよび読み出しは、ゲート電極（ワード線）16
にバイアス電圧を加え、MOSトランジスターをON状態に
し、ビット線22を通して行う。In the memory cell structure of the present invention, the signal is stored in the storage capacitor composed of the silicon substrate 10 and the capacitor electrode 15. Gate electrodes (word lines) 16 are used for writing and reading signals.
A bias voltage is applied to the MOS transistor to turn on the MOS transistor, and the operation is performed through the bit line 22.
本発明のメモリセルは、セル面積は容量電極の大きさで
決まる。In the memory cell of the present invention, the cell area is determined by the size of the capacitor electrode.
本発明の第２実施例を第２図に示す。ここでは、ゲート
電極として高融点金属30を用いる。半導体層はゲート電
極に接して形成される。このとき、半導体層とゲート電
極の境界にはショットキー接合が形成される。従ってこ
の場合は半導体層とゲート電極とによりショットキー接
合型電界効果トランジスターができる。A second embodiment of the present invention is shown in FIG. Here, the refractory metal 30 is used as the gate electrode. The semiconductor layer is formed in contact with the gate electrode. At this time, a Schottky junction is formed at the boundary between the semiconductor layer and the gate electrode. Therefore, in this case, a Schottky junction type field effect transistor can be formed by the semiconductor layer and the gate electrode.
本発明の第３実施例を第３図に示す。この場合は、平面
容量の代りに溝容量を用いている。シリコン基板10に溝
を堀り、溝側面に容量膜13を形成し、容量電極15は溝内
に埋め込まれる。溝容量を用いることにより、蓄積容量
の占有面積をリソグラフィーの限界まで小さくできる。
従って、溝容量を用いた本発明のメモリセルは、１トラ
ンジスター１容量型のDRAMセルとしては最小のセル面積
を実施できる。A third embodiment of the present invention is shown in FIG. In this case, the groove capacitance is used instead of the planar capacitance. A groove is formed in the silicon substrate 10, a capacitance film 13 is formed on the side surface of the groove, and the capacitance electrode 15 is embedded in the groove. By using the groove capacitance, the area occupied by the storage capacitance can be reduced to the limit of lithography.
Therefore, the memory cell of the present invention using the groove capacitance can realize the smallest cell area as a one-transistor / one-capacity DRAM cell.
第４図に、本発明を用いた場合のメモリセルアレイの一
例を示す。容量電極40にワード線41が設けられ、半導体
層42は容量電極上にパターニングされる。ビット線44は
容量電極42にコンタコト43を設け、ワード線41と直交し
て設けられている。FIG. 4 shows an example of a memory cell array when the present invention is used. A word line 41 is provided on the capacitance electrode 40, and the semiconductor layer 42 is patterned on the capacitance electrode. The bit line 44 is provided orthogonally to the word line 41 by providing the capacitor electrode 42 with the contact point 43.
以上説明したように本発明は、蓄積容量電極上にワード
線と、ワード線側面を用いた縦型トランジスターとを設
けることにより、蓄積容量の電極面積だけでメモリセル
が実現できる。さらに、本発明のメモリセルはソフトエ
ラー発生率が小さいため、蓄積容量を小さくでき、その
ため一層セル面積を縮小することが可能である。本発明
によれば、従来と同一のセル面積を実現するには、約３
倍もの大きな設計ルールが使え製造歩留が向上する。As described above, according to the present invention, by providing the word line on the storage capacitor electrode and the vertical transistor using the side surface of the word line, the memory cell can be realized only by the electrode area of the storage capacitor. Further, since the memory cell of the present invention has a low soft error occurrence rate, it is possible to reduce the storage capacity, and thus it is possible to further reduce the cell area. According to the present invention, in order to realize the same cell area as the conventional one, about 3
Doubled design rules can be used to improve manufacturing yield.
第１図は本発明の第１実施例のメモリセル断面図、第２
図は本発明の第２実施例のメモリセル断面図、第３図は
本発明の第３実施例のメモリセル断面図、第４図は本発
明の実施例のメモリセルアレイを説明するための平面
図、第５図は従来のメモリセル断面図である。 １……Ｐ型シリコン基板、２……素子分離領域、３……
容量膜、４……ゲート膜、５……容量電極、６……ワー
ド線、７……n+層、８……層間膜、９……ビット線、10
……シリコン基板、12……素子分離領域、13……容量
膜、14……ゲート膜、15……容量電極、16……ゲート電
極（ワード線）、17……n+型半導体層、18……Ｐ型半導
体層、19……n+型半導体層、20……PSG膜、21……層間
膜、22……ビット線、30……高融点金属、31……ショッ
トキー接合、40……容量電極、41……ワード線、42……
半導体層、43……コンタクト、44……ビット線。FIG. 1 is a sectional view of a memory cell according to the first embodiment of the present invention, and FIG.
FIG. 4 is a sectional view of a memory cell according to the second embodiment of the present invention, FIG. 3 is a sectional view of a memory cell according to the third embodiment of the present invention, and FIG. 4 is a plan view for explaining a memory cell array according to the embodiment of the present invention. 5 and 5 are cross-sectional views of conventional memory cells. 1 ... P-type silicon substrate, 2 ... Element isolation region, 3 ...
Capacitance film, 4 ... Gate film, 5 ... Capacitance electrode, 6 ... Word line, 7 ... N + layer, 8 ... Interlayer film, 9 ... Bit line, 10
...... Silicon substrate, 12 …… Element isolation region, 13 …… Capacitive film, 14 …… Gate film, 15 …… Capacitive electrode, 16 …… Gate electrode (word line), 17 …… n + type semiconductor layer, 18 ...... P type semiconductor layer, 19 …… n + type semiconductor layer, 20 …… PSG film, 21 …… interlayer film, 22 …… bit line, 30 …… high melting point metal, 31 …… Schottky junction, 40 ・ ・ ・… Capacitance electrode, 41 …… Word line, 42 ……
Semiconductor layer, 43 ... Contact, 44 ... Bit line.
Claims (1)
において、前記複数のメモリセルの夫々は、半導体基板
を一方の電極とし前記基板の表面を覆う誘電体膜上に形
成された導電層を他方の電極とする容量と、この容量の
前記導電層上に形成されたトランジスタとを有し、前記
トランジスタは、前記導電層上に形成された第１絶縁
膜、この第１絶縁膜の上表面上に形成されたゲート電
極、このゲート電極の上表面上に形成された第２絶縁
膜、ならびに、前記第２絶縁膜の上表面から前記第１お
よび第２絶縁膜の側面を介して前記導電層に達する半導
体層であって前記ゲート電極の側面とゲート絶縁膜を介
して対向するか又はショットキー接合を形成する半導体
層でなり、さらに、前記半導体層の前記第２絶縁膜の上
表面上に位置する部分にビット線とのコンタクトが設け
られていることを特徴とする半導体記憶装置。1. A semiconductor memory device having a plurality of memory cells, wherein each of the plurality of memory cells has a semiconductor substrate as one electrode and a conductive layer formed on a dielectric film covering a surface of the substrate as the other electrode. And a transistor formed on the conductive layer having this capacitance, the transistor comprising a first insulating film formed on the conductive layer, and an upper surface of the first insulating film. Formed on the gate electrode, a second insulating film formed on the upper surface of the gate electrode, and the conductive layer from the upper surface of the second insulating film through the side surfaces of the first and second insulating films. Reaching a side surface of the gate electrode via a gate insulating film or forming a Schottky junction, and further on the upper surface of the second insulating film of the semiconductor layer. In the part where it is located The semiconductor memory device characterized by contact between Tsu bets lines are provided.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012369A JPH0691216B2 (en) | 1986-01-22 | 1986-01-22 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012369A JPH0691216B2 (en) | 1986-01-22 | 1986-01-22 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62169475A JPS62169475A (en) | 1987-07-25 |
| JPH0691216B2 true JPH0691216B2 (en) | 1994-11-14 |
Family
ID=11803350
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61012369A Expired - Lifetime JPH0691216B2 (en) | 1986-01-22 | 1986-01-22 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691216B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0151197B1 (en) * | 1994-11-21 | 1998-10-01 | 문정환 | Semconductor device & its manufacturing method |
| KR0151385B1 (en) * | 1994-11-21 | 1999-03-30 | 문정환 | Semiconductor memory device and its manufacturing method |
| JP2803717B2 (en) * | 1996-03-21 | 1998-09-24 | 日本電気株式会社 | Chip-shaped breaking part and its circuit repairing device |
| US9276134B2 (en) * | 2014-01-10 | 2016-03-01 | Micron Technology, Inc. | Field effect transistor constructions and memory arrays |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4326332A (en) * | 1980-07-28 | 1982-04-27 | International Business Machines Corp. | Method of making a high density V-MOS memory array |
| JPS5779661A (en) * | 1980-11-05 | 1982-05-18 | Mitsubishi Electric Corp | Semiconductor device |
| JPH07105474B2 (en) * | 1983-09-28 | 1995-11-13 | 株式会社日立製作所 | Semiconductor memory |
-
1986
- 1986-01-22 JP JP61012369A patent/JPH0691216B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62169475A (en) | 1987-07-25 |
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