JPH0690032A - Superconductive thin film interlayer wiring - Google Patents
Superconductive thin film interlayer wiringInfo
- Publication number
- JPH0690032A JPH0690032A JP4240501A JP24050192A JPH0690032A JP H0690032 A JPH0690032 A JP H0690032A JP 4240501 A JP4240501 A JP 4240501A JP 24050192 A JP24050192 A JP 24050192A JP H0690032 A JPH0690032 A JP H0690032A
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- JP
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- Prior art keywords
- thin film
- axis
- interlayer wiring
- integrated circuit
- orientation
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＬｎＢａ2Ｃｕ3Ｏx超伝
導薄膜を用いた三次元集積回路の層間配線に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer wiring of a three-dimensional integrated circuit using a LnBa 2 Cu 3 O x superconducting thin film.
【０００２】[0002]
【従来の技術】１９８６年に発見されたＬａ1-xＭxＣｕ
Ｏ4-y（Ｍ：Ｓｒ，Ｂａ，０＜ｘ＜１）は、超伝導転移
温度（Ｔｃ）が３０〜４０Ｋと従来の金属超伝導体のＴ
C と比較して著しく高いことから、酸化物超伝導体の探
索が進められ、ＴC 〜９０Ｋを有するＬｎＢａ2Ｃｕ3Ｏ
X酸化物超伝導体（Ｌｎ：Ｙ及びランタニド元素）、ＴC
〜１１０Ｋを有するＢｉＳｒＣａＣｕＯX系酸化物超伝
導体、ＴC 〜１２０Ｋを有するＴｌＢａＣａＣｕＯX 系
酸化物超伝導体の発見が相次いだ。ところが、これらの
超伝導薄膜は異方性が強く、たとえば、コヒーレンス長
の短いｃ−軸方向においてはコヒーレンス長の長いａ−
軸方向に比べて、超伝導の臨界電流密度が数桁以上小さ
い。そのため、ｃ−軸配向膜で構成された積層構造の三
次元高集積回路内では下部回路層から上部回路層への信
号の受渡し時にコヒーレンス長の短いａ−軸配向部分を
通過せざるを得ない。この層間配線領域では信号の電流
が臨界電流密度を越えないために、断面積を大きくする
必要が生ずる。そのため、高集積化ができないという重
大な問題点に遭遇する。La 1-x M x Cu discovered in 1986
O 4-y (M: Sr, Ba, 0 <x <1) has a superconducting transition temperature (Tc) of 30 to 40 K, which is T of a conventional metal superconductor.
Since it is remarkably higher than that of C , the search for an oxide superconductor is promoted, and LnBa 2 Cu 3 O having T C ˜90 K is advanced.
X oxide superconductor (Ln: Y and lanthanide element), T C
BiSrCaCuO X-based oxide superconductor having a ～110K, there were numerous discoveries TlBaCaCuO X-based oxide superconductor having a T C ~120K. However, these superconducting thin films have strong anisotropy, and for example, a- having a long coherence length in the c-axis direction having a short coherence length.
The critical current density of superconductivity is several orders of magnitude smaller than that in the axial direction. Therefore, in a three-dimensional highly integrated circuit having a laminated structure composed of a c-axis oriented film, the signal must be passed from the lower circuit layer to the upper circuit layer through an a-axis oriented portion having a short coherence length. . In this interlayer wiring region, the signal current does not exceed the critical current density, so that it becomes necessary to increase the cross-sectional area. Therefore, there is a serious problem that high integration cannot be achieved.
【０００３】[0003]
【発明が解決しようとする課題】本発明は、下地材料に
より超伝導薄膜の結晶学的配向軸を制御し、コヒーレン
ス長の長い方向を平面内に持つ超伝導薄膜において、層
間配線となる領域のみ、コヒーレンス長の長い方向を超
伝導配線層に垂直にし、層間配線の面積を減少させ、高
集積酸化物超伝導体回路を実現するものである。SUMMARY OF THE INVENTION The present invention controls the crystallographic orientation axis of a superconducting thin film by means of a base material, and in the superconducting thin film having a direction of a long coherence length in a plane, only a region to be an interlayer wiring is formed. , The direction of the long coherence length is made perpendicular to the superconducting wiring layer, and the area of the interlayer wiring is reduced to realize a highly integrated oxide superconductor circuit.
【０００４】[0004]
【課題を解決するための手段】本発明は、酸化物超伝導
体を用いた三次元集積回路において、ＬｎＢａ２Ｃｕ ３
Ｏｘ（Ｌｎ：Ｙまたはびランタニド元素の中で超伝導と
なる元素）との格子不整合率が異なる二種以上の材料を
それぞれ一箇所以上堆積した部分上に堆積したＬｎＢａ
２Ｃｕ３Ｏｘ超伝導薄膜の結晶学的配向軸を変化させ、
コヒーレンス長の長い軸方向を配向軸（縦方向）とする
部分を下部集積回路と上部集積回路をつなぐ層間配線と
することを特徴とする。The present invention is directed to oxide superconductivity.
In a three-dimensional integrated circuit using a body, LnBaTwoCu Three
Ox(In Ln: Y or lanthanide element, superconductivity
Two or more materials with different lattice mismatches with
LnBa deposited on each one or more places
TwoCuThreeOxChange the crystallographic orientation axis of the superconducting thin film,
The axis with the long coherence length is the orientation axis (vertical direction)
Interlayer wiring connecting the lower integrated circuit and the upper integrated circuit
It is characterized by doing.
【０００５】[0005]
【作用】本発明ではＬｎＢａ2Ｃｕ3ＯX超伝導薄膜内の
所望の層間配線となる箇所におい て、配向軸１方向を
コヒーレンス長の長い方向を軸方向に持つａ−軸配向薄
膜を成長させることができる所に特徴がある。According to the present invention, an a-axis oriented thin film having the orientation axis 1 direction as the axial direction of the long coherence length is grown at a desired interlayer wiring in the LnBa 2 Cu 3 O x superconducting thin film. The feature is that you can do it.
【０００６】従来技術では層内の回路部分がｃ−軸配向
膜すなわち、電流の流れ易い（臨界電流密度の高い）ａ
／ｂ面を薄膜面内に持っているとすれば、層間配線膜は
電流の流れ難い（臨界電流密度の低い）ｃ軸方向を電流
が流れる方向に持っていることになる。そのため、信号
電流が超伝導を破壊する臨界電流密度を越えないために
は層間配線膜を太くする必要が生じ、集積回路の微細化
ができないという問題点が生ずる。一方、本発明を用い
れば、集積回路内では電流の流れ易い（臨界電流密度の
高い）ａ／ｂ面を薄膜表面内に持ちながら、層間配線膜
では電流の流れ易い（臨界電流密度の高い）ａ−軸方向
を電流の流れる向きに成長できるため、今までできなか
った高集積化が実現できる。In the prior art, the circuit portion in the layer is a c-axis oriented film, that is, a current easily flows (high critical current density) a.
If the / b plane is provided in the thin film plane, the interlayer wiring film has the c-axis direction in which current does not easily flow (low critical current density) in the direction of current flow. Therefore, in order to prevent the signal current from exceeding the critical current density that destroys superconductivity, it is necessary to thicken the interlayer wiring film, which causes a problem that the integrated circuit cannot be miniaturized. On the other hand, according to the present invention, the current easily flows in the interlayer wiring film (high critical current density) while the current flows easily in the integrated circuit (high critical current density) in the thin film surface. Since the a-axis direction can grow in the direction in which the current flows, a high degree of integration, which has been impossible up to now, can be realized.
【０００７】[0007]
【実施例】実施例１を説明する前に、本発明に密接に関
連する実験事実を説明する。図１は基板材料ＭｇＯ，Ｓ
ｒＴｉＯ3，ＬａＳｒＧａＯ4，ＰｒＧａＯ3，ＮｄＧａ
Ｏ3，ＬａＡｌＯ3，ＹＡｌＯ3 などのＹＢａ2ＣｕＯX超
伝導体との格子不整合率が異なる基板上にＹＢａ2Ｃｕ3
ＯX超伝導薄膜を作製した時の薄膜の結晶学的配向軸の
基板温度依存性を求めたものであり、図中、ａはａ−軸
配向、ｃはｃ−軸配向、ａ＋ｃはａ−軸配向とｃ−軸配
向が混在する薄膜の成長する領域である。図から基板温
度が同じであっても異なる基板上ではＹＢａ2 Ｃｕ3 Ｏ
X超伝導薄膜の結晶方位（配向）は基板格子の不整合率
で決まり、不整合率が大きいときはＹＢａ2Ｃｕ3ＯX超
伝導薄膜はｃ−軸配向となり、不整合率が小さいときは
ＹＢａ2Ｃｕ3Ｏx超伝導薄膜はａ−軸配向となることを
示している。すなわち、例えば、ＮｄＧａＯ3（ＹＢａ2
Ｃｕ3Ｏxとの格子不整合率が０．３％）とＳｒＴｉＯ3
（同１．１％）が表面に存在する下地上にヽ図１に示し
た点線の堆積温度でＹＢａ 2Ｃｕ3ＯX薄膜を堆積すれ
ば、ＮｄＧａＯ3上に蒸着されたＹＢａ2Ｃｕ3Ｏx薄膜は
ａ−軸配向となり、一方ＳｒＴｉＯ3 上に蒸着されたＹ
Ｂａ2Ｃｕ3ＯX薄膜はｃ−軸配向となることを示してい
る。EXAMPLES Before describing Example 1, the present invention is closely related.
Explain a series of experimental facts. Figure 1 shows the substrate material MgO, S
rTiO3, LaSrGaOFour, PrGaO3, NdGa
O3, LaAlO3, YAlO3 YBa such as2CuOXSuper
YBa on a substrate with a different lattice mismatch with the conductor2Cu3
OXOf the crystallographic orientation axis of the superconducting thin film
The temperature dependence of the substrate was obtained, where a is the a-axis.
Orientation, c is c-axis orientation, a + c is a-axis orientation and c-axis orientation
This is a region where a thin film having mixed orientations grows. Substrate temperature from figure
YBa on different substrates even if the degree is the same2 Cu3 O
XThe crystal orientation (orientation) of the superconducting thin film is the mismatch rate of the substrate lattice.
And YBa when the mismatch rate is large2Cu3OXSuper
The conductive thin film has c-axis orientation, and when the mismatch rate is small,
YBa2Cu3OxThe superconducting thin film should be a-axis oriented.
Shows. That is, for example, NdGaO3(YBa2
Cu3OxLattice mismatch with 0.3%) and SrTiO 33
(1.1% of the same) is shown on Fig. 1 on the substrate with the surface present.
YBa at the deposition temperature indicated by the dotted line 2Cu3OXDeposit a thin film
For example, NdGaO3YBa deposited on top2Cu3OxThin film
a-axis orientation, while SrTiO 33 Y deposited on top
Ba2Cu3OXIt shows that the thin film is c-axis oriented.
It
【０００８】（実施例１）この実験事実を基に、図２を
もって、本発明の実施例１を説明する。この図は本発明
による層間配線を説明する断面図であって、図中１はＳ
ｒＴｉＯ3 基板、２はＮｄＧａＯ3 薄膜、３は下部集積
回路のｃ−軸配向ＹＢａ2 Ｃｕ3ＯX薄膜、４は層間配線
となるａ−軸配向ＹＢａ2Ｃｕ3Ｏx薄膜、５はＳｒＴｉ
Ｏ3 層 間絶縁膜、６は上部電極のｃ−軸配向ＹＢａ2
Ｃｕ3ＯX薄膜である。ここで、集積回路内の薄膜はｃ−
軸配向膜（コヒーレンス長の短い方向が基板面に垂
直）、層間配線部分４はａ−軸配向膜（コヒーレンス長
の短い方向が平面内）である。この層間配線を通る電流
は、例えば下部の集積回路の薄膜３から層間配線４、そ
の後上部の集積回路の薄膜６に流れる。この時、薄膜３
中は電流は面内に流れやすく（ｃ−軸配向膜）、層間配
線４では基板面と垂直方向に流れ易く（ａ−軸配向
膜）、さらに上部の集積回路である薄膜６中では電流は
面内に流れやすく（ｃ−軸配向膜）なっていることに特
徴がある。(Embodiment 1) Based on this experimental fact, Embodiment 1 of the present invention will be described with reference to FIG. This drawing is a cross-sectional view for explaining an interlayer wiring according to the present invention, in which 1 is an S
RTiO 3 substrate, 2 is NdGaO 3 thin film, the c- axis oriented YBa 2 Cu 3 O X thin film of the lower integrated circuit 3, it is as an interlayer wiring a- axis oriented YBa 2 Cu 3 O x thin film 4, the 5 SrTi
O 3 inter-layer insulating film, 6 is the upper electrode c-axis orientation YBa 2
It is a Cu 3 O x thin film. Here, the thin film in the integrated circuit is c-
The axial alignment film (the direction of the short coherence length is perpendicular to the substrate surface), and the interlayer wiring part 4 is the a-axis alignment film (the direction of the short coherence length is in the plane). The current passing through the interlayer wiring flows from the thin film 3 of the lower integrated circuit to the interlayer wiring 4 and then to the thin film 6 of the upper integrated circuit, for example. At this time, the thin film 3
The current easily flows in the plane (c-axis alignment film), the interlayer wiring 4 easily flows in the direction perpendicular to the substrate surface (a-axis alignment film), and the current flows in the thin film 6 which is the integrated circuit above. It is characterized in that it easily flows in the plane (c-axis alignment film).
【０００９】次に図３から図６をもって実施例１の層間
配線の作製例を説明する。これらの図中１から６は図２
で説明したものと同じであり、７はマスク材である。図
３は例えば、ＹＢａ2Ｃｕ3Ｏxとの格子不整合率が１．
１％のＳｒＴｉＯ3基板上にマスク材７を乗せた状態を
示している。次にマスクしたところ以外の部分に例え
ば、ＹＢａ2Ｃｕ3ＯXとの格子不整合率が０．３％のＮ
ｄＧａＯ3２を堆積する。この状態からマスク材７を取
り去ったものが図４である。次に図４の基板上全面にＹ
Ｂａ2Ｃｕ3Ｏx薄膜を図１の点線で示した基板温度例え
ば７５０℃で堆積する。すると、図５に示したようにＳ
ｒＴｉＯ3 基板上にはａ−軸配向ＹＢａ2Ｃｕ3ＯX薄膜
３が堆積され、ＮｄＧａＯ3 薄膜２上にはａ−軸配向し
たＹＢａ2Ｃｕ3Ｏx薄膜４が堆積される。次にマスク材
７を層間配線となるａ−軸配向ＹＢａＣｕ3Ｏx薄膜４上
に配置する。これが図６である。次にＳｒＴｉＯ3 層間
絶縁膜５を堆積し、マスク材７を取り去り、上部集積回
路のＹＢａ2Ｃｕ3ＯX薄膜６を堆積する。するとＳｒＴ
ｉＯ3 層間絶縁膜５上にはｃ−軸配向ＹＢａ2ＣｕＯX薄
膜６が、層間配線４上にはそのままａ−軸配向膜が成長
する。これが図２である。以上により層間配線部のみに
ａ−軸配向薄膜を持つｃ−軸配向膜の下部薄膜３及び上
部薄膜６が実現できる。Next, an example of manufacturing the interlayer wiring of the first embodiment will be described with reference to FIGS. 1 to 6 in these figures are shown in FIG.
The mask material is the same as that described in 1. FIG. 3 shows that the lattice mismatch rate with YBa 2 Cu 3 O x is 1.
It shows a state in which the mask material 7 is placed on a 1% SrTiO 3 substrate. Next, in a portion other than the masked portion, for example, N having a lattice mismatch with YBa 2 Cu 3 O x of 0.3%
depositing a dGaO 3 2. FIG. 4 shows the mask material 7 removed from this state. Next, Y is formed on the entire surface of the substrate of FIG.
A Ba 2 Cu 3 O x thin film is deposited at the substrate temperature shown by the dotted line in FIG. 1, for example, 750 ° C. Then, as shown in FIG.
RTiO 3 on the substrate are deposited a- axis oriented YBa 2 Cu 3 O X thin film 3, on the NdGaO 3 thin film 2 YBa 2 Cu 3 O x thin film 4 oriented a- axes is deposited. Next, the mask material 7 is arranged on the a-axis oriented YBaCu 3 O x thin film 4 which will be the interlayer wiring. This is FIG. Next, the SrTiO 3 interlayer insulating film 5 is deposited, the mask material 7 is removed, and the YBa 2 Cu 3 O x thin film 6 of the upper integrated circuit is deposited. Then SrT
The c-axis oriented YBa 2 CuO x thin film 6 grows on the iO 3 interlayer insulating film 5, and the a-axis oriented film grows on the interlayer wiring 4 as it is. This is FIG. As described above, the lower thin film 3 and the upper thin film 6 of the c-axis oriented film having the a-axis oriented thin film only in the interlayer wiring portion can be realized.
【００１０】（実施例２）図７は実施例２を説明する断
面図であって、図中１はＳｒＴｉＯ3 基板、２はＮｄＧ
ａＯ3 薄膜、３は下部集積回路のｃ−軸配向ＹＢａ2 Ｃ
ｕ3ＯX薄膜、４は層間配線となるａ−軸配向ＹＢａＣｕ
3 Ｏx薄膜、５はＳｒＴｉＯ3 層間絶縁 膜、６は上部電
極のｃ−軸配向ＹＢａ2 Ｃｕ3ＯX薄膜である。実施例１
における基板上のＮｄＧａＯ3 薄膜２を堆積する前にマ
スクを用いて次に堆積するＳｒＴｉＯ3 薄膜２の膜厚分
だけエッチングにより掘り下げた点のみ異なる。これに
より層間配線となるａ−軸配向部分と集積回路となるｃ
−軸配向部分との境界領域の接触面積を増大すなわち、
電流密度を向上させ、かつプロセスマージンを増大させ
る平坦化を実現する付加的効果がある。ここでは下部集
積回路の薄膜の埋め込みを例として説明したが、上部集
積回路直下の層間絶縁膜を埋め込めば、層間配線となる
ａ−軸配向部分と上部集積回路のｃ−軸配向部分との境
界領域の接触面積を増大できることは言うまでもない。(Embodiment 2) FIG. 7 is a sectional view for explaining Embodiment 2. In the drawing, 1 is a SrTiO 3 substrate and 2 is NdG.
aO 3 thin film, 3 are c-axis oriented YBa 2 C of the lower integrated circuit
u 3 O x thin film, 4 is an a-axis oriented YBaCu which becomes an interlayer wiring
3 O x thin film, 5 is a SrTiO 3 interlayer insulating film, and 6 is a c-axis oriented YBa 2 Cu 3 O x thin film of the upper electrode. Example 1
Before the NdGaO 3 thin film 2 on the substrate in FIG. 2 is deposited, a mask is used to etch the SrTiO 3 thin film 2 to be deposited next by a film thickness. As a result, the a-axis oriented portion that becomes the interlayer wiring and the c that becomes the integrated circuit
-Increasing the contact area of the boundary region with the axially oriented portion, i.e.
There is the additional effect of improving the current density and achieving planarization that increases the process margin. Although the thin film of the lower integrated circuit has been described as an example here, if the interlayer insulating film directly below the upper integrated circuit is buried, the boundary between the a-axis oriented portion of the upper integrated circuit and the a-axis oriented portion of the upper integrated circuit. It goes without saying that the contact area of the region can be increased.
【００１１】本実施例では、例として、ＳｒＴｉＯ
3（格子不整合率１．１％）、ＮｄＧａＯ3（同０．３
％）、超伝導材料としてＹＢａ2Ｃｕ3Ｏxを用いて説明
したが、格子不整合率の異なる２種の材料上に堆積した
超伝導薄膜が不整合率の小きい方の材料上ではａ−軸配
向、不整合率が大きい方の材料上ではｃ−軸配向となる
堆積温度が設定できれば全く同じ効果が得られることは
あきらかである。また本実施例では下部薄膜堆積前の異
なる２種の基板表面材料として、基板と薄膜を用いたが
２種類以上の格子不整合率の異なる薄膜材料を堆積した
上でも同じ効果が得られることは言うまでもない。In this embodiment, as an example, SrTiO 3
3 (lattice mismatch rate 1.1%), NdGaO 3 (0.3
%), YBa 2 Cu 3 O x was used as the superconducting material. However, a superconducting thin film deposited on two kinds of materials having different lattice mismatches has a It is clear that the same effect can be obtained if the deposition temperature for c-axis orientation can be set on the material having the larger −axis orientation and mismatch rate. Further, in this embodiment, the substrate and the thin film were used as the two different types of substrate surface materials before the deposition of the lower thin film, but the same effect can be obtained by depositing two or more types of thin film materials having different lattice mismatch rates. Needless to say.
【００１２】[0012]
【発明の効果】以上説明したように、本発明による、層
間配線の構造によれば、層間配線部においてはコヒーレ
ンス長の長い軸（電流の流れ易いａ−ｂ面）を配向軸
に、集積回路の薄膜部ではコヒーレンス長の短い軸（電
流の流れ難いｃ軸）を配向軸に持つ薄膜（薄膜表面内に
電流の流れ易いａ−ｂ面を持つ薄膜）を用いられるた
め、層間配線の細線化と上下集積回路内の細線化を同時
に実現できる効果がある。As described above, according to the structure of the interlayer wiring according to the present invention, in the interlayer wiring portion, the axis of the long coherence length (the ab plane where the current easily flows) is used as the orientation axis for the integrated circuit. In the thin film part, a thin film having a short coherence length axis (c axis where current does not easily flow) as an orientation axis (thin film having ab plane in which current easily flows) is used. And, it is possible to realize the thinning of the upper and lower integrated circuits at the same time.
【図１】格子不整合率とａ−軸配向／ｃ−軸配向となる
基板温度との関係を示したものであって、縦軸は基板温
度、横軸はＹＢａ2 Ｃｕ3ＯX薄膜との格子不整合率であ
る。FIG. 1 is a graph showing the relationship between the lattice mismatch rate and the substrate temperature at which a-axis orientation / c-axis orientation is achieved, where the vertical axis represents the substrate temperature and the horizontal axis represents the YBa 2 Cu 3 O x thin film. Is the lattice mismatch rate of.
【図２】実施例１の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 2 is a schematic view of a structure and manufacturing example of a vertical superconducting junction element of Example 1.
【図３】実施例１の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 3 is a schematic view of a structure and a manufacturing example of the vertical superconducting junction element of Example 1.
【図４】実施例１の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 4 is a schematic view of a structure and manufacturing example of a vertical superconducting junction element of Example 1.
【図５】実施例１の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 5 is a schematic view of a structure and a manufacturing example of the vertical superconducting junction element of Example 1.
【図６】実施例１の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 6 is a schematic view of a structure and a manufacturing example of the vertical superconducting junction element of Example 1.
【図７】実施例２の縦型超伝導接合素子の構造及び製造
例の概略図である。FIG. 7 is a schematic view of a structure and a manufacturing example of a vertical superconducting junction element of Example 2.
１ ＳｒＴｉＯ3 基板、 ２ ＮｄＧａＯ3 薄膜、 ３ 下部のｃ−軸配向ＹＢａ2ＣｕＯX薄膜、 ４ 層間配線ａ−軸配向ＹＢａ2Ｃｕ3Ｏx薄膜、 ５ 層間絶縁膜のＳｒＴｉＯ3 薄膜、 ６ 上部のｃ−軸配向ＹＢａ2Ｃｕ3ＯX薄膜、 ７ マスク、 ｃ ｃ−軸配向となる領域、 ａ ａ−軸配向となる領域、 ａ＋ｃ ａ−軸配向とｃ−軸配向とが混在する領域。1 SrTiO 3 substrate, 2 NdGaO 3 thin film, 3 lower c-axis oriented YBa 2 CuO x thin film, 4 interlayer wiring a-axis oriented YBa 2 Cu 3 O x thin film, 5 SrTiO 3 thin film of interlayer insulating film, 6 upper part c- axis oriented YBa 2 Cu 3 O X film, 7 mask region to be c c- axis orientation, the area to be a a- axis orientation, a + c a- axis oriented and c- region axis orientation are mixed.
Claims (1)
において、ＬｎＢａ 2Ｃｕ3Ｏx（Ｌｎ：Ｙまたはびラン
タニド元素の中で超伝導となる元素）との格子不整合率
が異なる二種以上の材料をそれぞれ一箇所以上堆積した
部分上に堆積したＬｎＢａ2Ｃｕ3Ｏx 超伝導薄膜の結晶
学的配向軸を変化させ、コヒーレンス長の長い軸方向を
配向軸（縦方向）とする部分を下部集積回路と上部集積
回路をつなぐ層間配線とすることを特徴とする超伝導薄
膜層間配線。1. A three-dimensional integrated circuit using an oxide superconductor.
At LnBa 2Cu3Ox(Ln: Y or big run
Lattice mismatch rate with the superconducting element among the tannide elements)
Deposited two or more materials with different
LnBa deposited on the part2Cu3Ox Crystal of superconducting thin film
The orientation axis to change the direction of the long coherence length.
Lower integrated circuit and upper integrated part with the orientation axis (vertical direction)
Superconducting thin film characterized by being an interlayer wiring connecting circuits
Interlayer wiring.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240501A JP2708675B2 (en) | 1992-09-09 | 1992-09-09 | Method of manufacturing superconducting thin film interlayer wiring |
| EP99118017A EP0973208B1 (en) | 1992-07-28 | 1993-07-27 | Lattice matching device and method for fabricating the same |
| US08/097,235 US5593950A (en) | 1992-07-28 | 1993-07-27 | Lattice matching super conducting device with a- and c- axes |
| DE69328278T DE69328278T2 (en) | 1992-07-28 | 1993-07-27 | Transition device with lattice adjustment and method for its production |
| EP93111981A EP0582889B1 (en) | 1992-07-28 | 1993-07-27 | Junction device with lattice matching and method for fabricating the same |
| DE69333799T DE69333799T2 (en) | 1992-07-28 | 1993-07-27 | Lattice-matched device and method for its manufacture |
| EP05005034A EP1544926A3 (en) | 1992-07-28 | 1993-07-27 | Superconducting thin film device comprising superconducting oxide multilayer interconnections and method for fabricating the same |
| US08/479,751 US5821200A (en) | 1992-07-28 | 1995-06-07 | Lattice matching device and method for fabricating the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4240501A JP2708675B2 (en) | 1992-09-09 | 1992-09-09 | Method of manufacturing superconducting thin film interlayer wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0690032A true JPH0690032A (en) | 1994-03-29 |
| JP2708675B2 JP2708675B2 (en) | 1998-02-04 |
Family
ID=17060458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4240501A Expired - Fee Related JP2708675B2 (en) | 1992-07-28 | 1992-09-09 | Method of manufacturing superconducting thin film interlayer wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2708675B2 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0446098A (en) * | 1990-06-13 | 1992-02-17 | Toshiba Corp | Superconducting member |
| JPH04144994A (en) * | 1990-10-05 | 1992-05-19 | Mitsubishi Heavy Ind Ltd | Production of oxide superconductor thin film |
| JPH04167578A (en) * | 1990-10-31 | 1992-06-15 | Sumitomo Electric Ind Ltd | Superconductive circuit and manufacture thereof |
| JPH05251772A (en) * | 1991-12-02 | 1993-09-28 | Sumitomo Electric Ind Ltd | Superconducting multilayer interconnection and manufacture thereof |
-
1992
- 1992-09-09 JP JP4240501A patent/JP2708675B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0446098A (en) * | 1990-06-13 | 1992-02-17 | Toshiba Corp | Superconducting member |
| JPH04144994A (en) * | 1990-10-05 | 1992-05-19 | Mitsubishi Heavy Ind Ltd | Production of oxide superconductor thin film |
| JPH04167578A (en) * | 1990-10-31 | 1992-06-15 | Sumitomo Electric Ind Ltd | Superconductive circuit and manufacture thereof |
| JPH05251772A (en) * | 1991-12-02 | 1993-09-28 | Sumitomo Electric Ind Ltd | Superconducting multilayer interconnection and manufacture thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2708675B2 (en) | 1998-02-04 |
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