JPH0687491B2 - Thin film capacitors - Google Patents

Thin film capacitors

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Publication number
JPH0687491B2
JPH0687491B2 JP23848489A JP23848489A JPH0687491B2 JP H0687491 B2 JPH0687491 B2 JP H0687491B2 JP 23848489 A JP23848489 A JP 23848489A JP 23848489 A JP23848489 A JP 23848489A JP H0687491 B2 JPH0687491 B2 JP H0687491B2
Authority
JP
Japan
Prior art keywords
film
layer
silicon
thin film
platinum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP23848489A
Other languages
Japanese (ja)
Other versions
JPH03101260A (en
Inventor
正吾 松原
洋一 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP23848489A priority Critical patent/JPH0687491B2/en
Priority to EP90309478A priority patent/EP0415751B1/en
Priority to US07/574,778 priority patent/US5053917A/en
Priority to DE69017802T priority patent/DE69017802T2/en
Publication of JPH03101260A publication Critical patent/JPH03101260A/en
Publication of JPH0687491B2 publication Critical patent/JPH0687491B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、小型電子回路に用いる薄膜コンデンサに関す
る。
Description: TECHNICAL FIELD The present invention relates to a thin film capacitor used in a small electronic circuit.

(従来の技術) 集積回路技術の発達によって電子回路がますます小型化
しており、各種電子回路に必須の回路素子であるコンデ
ンサの小型化も一段と重要になっている。誘電体薄膜を
用いた薄膜コンデンサが、トランジスタ等の能動素子と
同一の基板上に形成されて利用されているが、能動素子
の小型化が急速に進む中で薄膜コンデンサの小型化は遅
れており、より一層の高集積化を阻む大きな要因となっ
てきている。これは、従来用いられている誘電体薄膜材
料がSiO2、Si3N4等のような誘電率がたかだか10以下の
材料に限られているためであり、薄膜コンデンサを小型
化する手段として誘電率の大きな誘電体薄膜を開発する
ことが必要となっている。化学式ABO3で表されるペロブ
スカイト型酸化物であるBaTiO3、SrTiO3,PbZrO3および
イルメナイト型酸化物LiNbO3あるいはBi4Ti3O12等の強
誘電体に属する酸化物は、上記の単一組成並びに相互の
固溶体組成で、単結晶あるいはセラミックにおいて100
以上10000にも及ぶ誘電率を有することが知られてお
り、セラミック・コンデンサに広く用いられている。こ
れら材料の薄膜化は上述の薄膜コンデンサの小型化に極
めて有効であり、かなり以前から研究が行われている。
それらの中で比較的良好な特性が得られている例として
は、プロシーディング・オブ・アイ・イー・イー・イー
(Proceedings of the IEEE)第59巻10号1440−1447頁
に所載の論文があり、スパッタリングによる成膜および
熱処理を行ったBaTiO3薄膜で16(室温で作成)から1900
(1200℃で熱処理)の誘電率が得られている。
(Prior Art) With the development of integrated circuit technology, electronic circuits are becoming smaller and smaller, and miniaturization of capacitors, which are circuit elements essential for various electronic circuits, is becoming more important. Thin film capacitors using dielectric thin films are used by being formed on the same substrate as active elements such as transistors, but miniaturization of thin film capacitors has been delayed due to rapid miniaturization of active elements. , Has become a major factor preventing further high integration. This is because the conventionally used dielectric thin film materials are limited to materials with a dielectric constant of at most 10 such as SiO 2 , Si 3 N 4, etc. It is necessary to develop a dielectric thin film with a high rate. The oxides belonging to the ferroelectric such as BaTiO 3 , SrTiO 3 , PbZrO 3 and ilmenite type oxides LiNbO 3 and Bi 4 Ti 3 O 12 which are perovskite type oxides represented by the chemical formula ABO 3 are Composition and mutual solid solution composition, 100 in single crystal or ceramic
It is known to have a dielectric constant as high as 10,000, and is widely used in ceramic capacitors. Thinning of these materials is extremely effective for miniaturization of the above-mentioned thin film capacitor, and research has been conducted for quite some time.
Among these, examples in which relatively good characteristics have been obtained are the papers published in Proceedings of the IEEE Vol. 59, No. 10, pp. 1404-1447. There is a sputtered and heat-treated BaTiO 3 thin film from 16 (created at room temperature) to 1900
A dielectric constant of (heat treated at 1200 ° C) is obtained.

現在の高集積回路に広く用いられている電極材料は多結
晶シリコンあるいはシリコン基板自体の一部に不純物を
高濃度にドーピングした低抵抗シリコン層である。以下
これらを総してシリコン電極と呼ぶ。シリコン電極は微
細加工技術が確立されており、すでに広く用いられてい
るため、シリコン電極上に良好な高誘電率薄膜が作製で
きれば、集積回路用コンデンサへの利用が可能となる。
しかしながら、従来技術では例えばIBM・ジャーナル・
オブ・リサーチ・アンド・デイベロップメント(IBM Jo
urnal of Research and Development)1969年11月号686
−695頁に所載のSrTiO3膜に関する論文が、ジャーナル
・オブ・バキューム・サイエンス・アンド・テクノロジ
ー(Journal of Vacuum Science and Technology)第16
巻2号315−318頁に所載のBaTiO3に関する論文が報告さ
れている。
The electrode material widely used in the present highly integrated circuits is polycrystalline silicon or a low resistance silicon layer in which a part of the silicon substrate itself is highly doped with impurities. Hereinafter, these are collectively called a silicon electrode. Since a fine processing technology has been established for silicon electrodes and is already widely used, if a good high-dielectric-constant thin film can be formed on silicon electrodes, it can be used for capacitors for integrated circuits.
However, in the prior art, for example, IBM
Of Research and Development (IBM Jo
urnal of Research and Development) November 1969 686
A paper on SrTiO 3 film on page −695 was published in Journal of Vacuum Science and Technology 16th
Article has been reported about the BaTiO 3 of Shosai No. 2, pp 315-318 winding.

(発明が解決しようとする課題) 上記のように高誘電率を得るためには高い成膜温度を必
要とするが、従来シリコン電極上に作成されているBaTi
O3等の誘電体薄膜は約100Åの二酸化シリコン(SiO2
に等価な層が界面に形成されてしまうと報告されてい
る。この界面層は誘電率が低い層であるため、結果とし
てシリコン上に形成した高誘電率薄膜の実効的な誘電率
は大きく低下してしまい、高誘電率材料を用いる利点が
ほとんど損なわれていた。
(Problems to be Solved by the Invention) As described above, a high film formation temperature is required to obtain a high dielectric constant, but BaTi that is conventionally formed on a silicon electrode is required.
Dielectric thin film such as O 3 is about 100 Å silicon dioxide (SiO 2 )
It is reported that a layer equivalent to is formed at the interface. Since this interface layer has a low dielectric constant, the effective dielectric constant of the high-dielectric-constant thin film formed on silicon was greatly reduced as a result, and the advantage of using a high-dielectric constant material was almost lost. .

(課題を解決するための手段) 本発明はシリコン電極上に導電層、誘電体、上部電極が
順次形成された構造の薄膜コンデンサにおいて、導電層
がシリコン上に形成される第1層とその上に形成される
第2層とから構成され、第1層がチタン、タンタル、モ
リブデン、タングステンの高融点金属あるいはそれらの
シリサイド化合物から選ばれる少なくとも1種以上の材
料であり、第2層が白金、パラヂウム、ロヂウムの高融
点貴金属から選ばれる少なくとも1種以上の材料である
ことを特徴する集積回路用薄膜コンデンサである。
(Means for Solving the Problems) The present invention relates to a thin film capacitor having a structure in which a conductive layer, a dielectric, and an upper electrode are sequentially formed on a silicon electrode, and a conductive layer is formed on the first layer and the first layer. A second layer formed on the first layer, the first layer is at least one material selected from refractory metals such as titanium, tantalum, molybdenum, and tungsten, or a silicide compound thereof, and the second layer is platinum. A thin film capacitor for an integrated circuit, comprising at least one material selected from high melting point precious metals such as palladium and rhodium.

(実施例1) 以下、本発明の実施例について図面を参照して説明す
る。
Example 1 Hereinafter, an example of the present invention will be described with reference to the drawings.

第1図は本実施例の薄膜コンデンサの構造図である。単
結晶シリコン1の表面の一部にリンを高濃度にドーピン
グして低抵抗層2が形成され、その上に層間絶縁膜とし
て酸化シリコン膜3が形成されている。酸化シリコン膜
の一部は、低抵抗層を通じて下部電極を引き出すための
コンタクトホールが2箇所形成されており、一方のコン
タクトホールは多結晶シリコン膜4で埋められ、もう一
方のコンタクトホールはAl膜5で埋められている。従っ
て、Al膜5は下部電極の端子となる。多結晶シリコン膜
4はコンタクトホールを埋めると共にその一部が酸化シ
リコン膜3上へ形成されていてもよい。多結晶シリコン
膜4上には第1層のチタン、第2層の白金からなる積層
の導電層8が形成され、導電層8の上にはBaTiO3膜6
が、さらにその上に上部電極としてA17が形成されてい
る。
FIG. 1 is a structural diagram of the thin film capacitor of this embodiment. A low resistance layer 2 is formed by heavily doping phosphorus on a part of the surface of the single crystal silicon 1, and a silicon oxide film 3 is formed thereon as an interlayer insulating film. In a part of the silicon oxide film, two contact holes for drawing out the lower electrode through the low resistance layer are formed, one contact hole is filled with the polycrystalline silicon film 4, and the other contact hole is an Al film. Filled with 5. Therefore, the Al film 5 becomes a terminal of the lower electrode. The polycrystalline silicon film 4 may fill the contact hole and a part thereof may be formed on the silicon oxide film 3. On the polycrystalline silicon film 4, a laminated conductive layer 8 made of a first layer of titanium and a second layer of platinum is formed, and a BaTiO 3 film 6 is formed on the conductive layer 8.
However, A17 is formed thereon as an upper electrode.

導電層は直流マグネトロンスパッタ法で作製した。Arガ
ス雰囲気、4×10-3Torr、基板温度100℃で行い、白
金、チタンの膜厚は、それぞれ、3000Å、500Åとし
た。BaTiO3膜は化学量論組成の粉末ターゲットを用い、
高周波マグネトロンスパッタ法で5000Åの膜厚のものを
作製した。Ar−O2混合ガス中、1×10-2Torr、基板温度
600℃でスパッタ成膜した。上部電極には5000ÅのAlを
直流スパッタ法により成膜した。本コンデンサの有効面
積は250μmである。つぎに導電層として本方法の白
金、チタンの多層膜を用いた場合、高融点貴金属である
白金膜だけを用いた場合、更に導電層を形成しない場合
のBaTiO3膜の特性の違いについて述べる。第2図(a)
は本方法の白金とチタンの多層膜を用いた場合のBaTiO3
膜の、(b)は膜厚3000Åの白金膜を用いた場合の、
(c)は膜厚3000Åでシート抵抗100Ω/cm2の多結晶シ
リコン膜を用いた場合のBaTiO3膜の膜厚による誘電率の
変化を調べたものである。本方法の多層膜を用いた場合
のBaTiO3膜の誘電率はその膜厚に依存せず一定であるの
に対し、白金膜あるいは多結晶シリコン膜を用いた場合
には誘電体膜の膜厚が小さくなるにつれて誘電率が著し
く減少してしまう。
The conductive layer was formed by the DC magnetron sputtering method. Ar gas atmosphere, 4 × 10 −3 Torr, substrate temperature 100 ° C., and platinum and titanium film thicknesses of 3000Å and 500Å, respectively. For the BaTiO 3 film, a stoichiometric powder target was used.
A film with a film thickness of 5000 Å was produced by the high frequency magnetron sputtering method. Substrate temperature 1 × 10 -2 Torr in Ar-O 2 mixed gas
The film was formed by sputtering at 600 ° C. 5000 Å Al was deposited on the upper electrode by DC sputtering. The effective area of this capacitor is 250 μm 2 . Next, the difference in the characteristics of the BaTiO 3 film when the platinum / titanium multilayer film of the present method is used as the conductive layer, when only the platinum film which is a high melting point noble metal is used, and when the conductive layer is not formed will be described. Fig. 2 (a)
Is BaTiO 3 when using the platinum-titanium multilayer film of this method.
(B) of the film, when using a platinum film with a film thickness of 3000 Å,
(C) shows the change in the dielectric constant depending on the film thickness of the BaTiO 3 film when a polycrystalline silicon film having a film thickness of 3000 Å and a sheet resistance of 100 Ω / cm 2 is used. When the multilayer film of this method is used, the dielectric constant of the BaTiO 3 film is constant irrespective of its film thickness, whereas when the platinum film or polycrystalline silicon film is used, the film thickness of the dielectric film is As becomes smaller, the permittivity decreases significantly.

多結晶シリコン膜での誘電率の低下は従来報告されてい
る通り、誘電体と電極の界面におけるシリコンの酸化に
よる低誘電率層の形成が原因である。白金膜での誘電率
の低下は白金のシリサイド化合物の形成に起因してい
る。即ち、600℃での誘電体の成膜時にシリコンは白金
と反応し、シリサイド化合物を形成しながら最表面に達
する。最表面に達したシリコンは多結晶シリコン膜の場
合と同様に酸化されて低誘電率層を形成してしまうと考
えられる。X線回折により、白金が誘電体の成膜後にシ
リサイド化していることを確認した。これに対して、同
じくX線回折によれば、白金とチタンの多層膜では誘電
体の成膜後も白金がシリサイド化せず元の状態で依存し
ている。即ち、シリコンはチタン層でその拡散が抑えら
れて白金層に達しておらず、前述のようなシリコンの酸
化による低誘電率層の形成が起こらない。
As previously reported, the decrease in the dielectric constant of the polycrystalline silicon film is due to the formation of the low dielectric constant layer due to the oxidation of silicon at the interface between the dielectric and the electrode. The decrease in the dielectric constant of the platinum film is due to the formation of a platinum silicide compound. That is, silicon reacts with platinum at the time of forming a dielectric film at 600 ° C., and reaches the outermost surface while forming a silicide compound. It is considered that the silicon reaching the outermost surface is oxidized to form a low dielectric constant layer as in the case of the polycrystalline silicon film. It was confirmed by X-ray diffraction that platinum was silicified after the dielectric film was formed. On the other hand, similarly, according to X-ray diffraction, in the platinum-titanium multilayer film, platinum is not silicified even after the dielectric film is formed and depends on the original state. That is, since the diffusion of silicon is suppressed by the titanium layer and does not reach the platinum layer, the formation of the low dielectric constant layer due to the oxidation of silicon as described above does not occur.

本実施例の導電層のチタンの代わりにタンタル、モリブ
デン、タングステンの高融点金属、あるいはそれらのシ
リサイドを用いても同様の効果が得られる。また、白金
の代わりにパラヂウム、あるいはロヂウムの高融点貴金
属を用いてもよい。
Similar effects can be obtained by using a refractory metal such as tantalum, molybdenum, or tungsten, or a silicide thereof instead of titanium in the conductive layer of this embodiment. Further, instead of platinum, a high melting point noble metal such as palladium or rhodium may be used.

(実施例2) 実施例1と同じ構造の薄膜コンデンサにおいて、導電層
の第1層に高融点金属とそれらのシリサイドで構成され
る合金膜、あるいは多層膜を用いた。表1に本実施例で
用いた材料をまとめた。
(Example 2) In the thin film capacitor having the same structure as in Example 1, an alloy film or a multilayer film composed of refractory metals and their silicides was used for the first layer of the conductive layer. Table 1 summarizes the materials used in this example.

本実施例においても実施例1と同様に、BaTiO3膜の誘電
率はその膜厚に依存せず本来の値が得られ、界面での低
誘電率層の形成を防止できた。また、X線回折によっ
て、第2層の白金がシリサイド化していないことを確認
した。
Also in this example, as in Example 1, the dielectric constant of the BaTiO 3 film did not depend on the film thickness, and the original value was obtained, and formation of the low dielectric constant layer at the interface could be prevented. Moreover, it was confirmed by X-ray diffraction that the platinum in the second layer was not silicified.

(実施例3) 実施例1と同じ構造の薄膜コンデンサにおいて、導電層
の第2層に白金、パラヂウム、ロヂウムの高融点貴金属
からなる合金膜、あるいは多層膜を用いた。表2に本実
施例で用いた材料をまとめた。
(Example 3) In the thin film capacitor having the same structure as in Example 1, an alloy film or a multilayer film made of a high melting point noble metal such as platinum, palladium, or rhodium was used for the second layer of the conductive layer. Table 2 summarizes the materials used in this example.

本実施例においても実施例1と同様に、BaTiO3膜の誘電
率はその膜厚に依存せず本来の値が得られ、界面での低
誘電率層の形成を防止できた。また、X線回折によっ
て、第2層の高融点貴金属の合金あるいは多層膜金がシ
リサイド化していないことを確認した。
Also in this example, as in Example 1, the dielectric constant of the BaTiO 3 film did not depend on the film thickness, and the original value was obtained, and formation of the low dielectric constant layer at the interface could be prevented. It was also confirmed by X-ray diffraction that the alloy of the high melting point noble metal or the multilayer film gold of the second layer was not silicided.

以上はBaTiO3膜について説明したが、この他にSrTiO3
PbTiO3、PbZrO3、LiNbO3,Bi3Ti4O12及び固溶体(Ba、S
r)TiO3、(Ba、Pb)TiO3、Pb(Zr、Ti)O3について同様の
作製、評価を行った結果、BaTiO3の場合と同様の作製方
法において膜厚によらず誘電体膜本来の誘電率が得られ
た。
The above is the description of the BaTiO 3 film, but in addition to this, SrTiO 3 ,
PbTiO 3 , PbZrO 3 , LiNbO 3 , Bi 3 Ti 4 O 12 and solid solution (Ba, S
r) TiO 3, (Ba, Pb) TiO 3, Pb (Zr, Ti) O 3 same manufacturing the result of the evaluation, the dielectric film regardless of the film thickness in the same manufacturing method as in the case of BaTiO 3 The original dielectric constant was obtained.

(発明の効果) 本発明は以上説明したように、シリコン電極上に形成さ
れた薄膜コンデンサにおいてシリコン電極と誘電体膜の
間に高融点金属膜もしくはそれらのシリサイド膜と高融
点貴金属膜からなる導電層を形成することにより、シリ
コンの酸化を防ぎ、高誘電率の薄膜コンデンサを提供す
ることができる。
(Effect of the Invention) As described above, according to the present invention, in a thin film capacitor formed on a silicon electrode, a conductive film composed of a refractory metal film or a silicide film thereof and a refractory noble metal film between the silicon electrode and the dielectric film. By forming the layer, it is possible to prevent the oxidation of silicon and provide a high dielectric constant thin film capacitor.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明における実施例1の薄膜コンデンサの断
側面図、第2図はBaTiO3膜の膜厚と誘電率の関係を示す
図。 1は単結晶シリコン基板、2は単結晶シリコンの低抵抗
層、3は酸化シリコン、4は多結晶シリコン膜、5、7
はAl、6はBaTiO3膜、8は第1層のチタンと第2層の白
金からなる導電層である。
FIG. 1 is a sectional side view of a thin film capacitor of Example 1 of the present invention, and FIG. 2 is a diagram showing a relationship between a film thickness of a BaTiO 3 film and a dielectric constant. 1 is a single crystal silicon substrate, 2 is a low resistance layer of single crystal silicon, 3 is silicon oxide, 4 is a polycrystalline silicon film,
Is Al, 6 is a BaTiO 3 film, and 8 is a conductive layer made of titanium of the first layer and platinum of the second layer.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】シリコン電極上に導電層、誘電体、上部電
極が順次形成された構造の薄膜コンデンサにおいて、導
電層がシリコン上に形成される第1層とその上に形成さ
れる第2層とから構成され、第1層がチタン、タンタ
ル、モリブデン、タングステンの高融点金属あるいはそ
れらのシリサイド化合物から選ばれる少なくとも1種以
上の材料であり、第2層が白金、パラヂウム、ロヂウム
の高融点貴金属から選ばれる少なくとも1種以上の材料
であることを特徴とする薄膜コンデンサ。
1. In a thin film capacitor having a structure in which a conductive layer, a dielectric and an upper electrode are sequentially formed on a silicon electrode, the conductive layer is a first layer formed on silicon and a second layer formed on the first layer. The first layer is at least one material selected from refractory metals such as titanium, tantalum, molybdenum, and tungsten or silicide compounds thereof, and the second layer is a refractory noble metal such as platinum, palladium, and rhodium. A thin film capacitor comprising at least one material selected from the group consisting of:
JP23848489A 1989-08-30 1989-09-14 Thin film capacitors Expired - Lifetime JPH0687491B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP23848489A JPH0687491B2 (en) 1989-09-14 1989-09-14 Thin film capacitors
EP90309478A EP0415751B1 (en) 1989-08-30 1990-08-30 Thin film capacitor and manufacturing method thereof
US07/574,778 US5053917A (en) 1989-08-30 1990-08-30 Thin film capacitor and manufacturing method thereof
DE69017802T DE69017802T2 (en) 1989-08-30 1990-08-30 Thin film capacitor and its manufacturing process.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23848489A JPH0687491B2 (en) 1989-09-14 1989-09-14 Thin film capacitors

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JPH03101260A JPH03101260A (en) 1991-04-26
JPH0687491B2 true JPH0687491B2 (en) 1994-11-02

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Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0514149B1 (en) * 1991-05-16 1995-09-27 Nec Corporation Thin film capacitor
JPH0746670B2 (en) * 1991-06-07 1995-05-17 日本電気株式会社 Thin film capacitor
JP2690821B2 (en) * 1991-05-28 1997-12-17 シャープ株式会社 Semiconductor device
JPH0748448B2 (en) * 1991-08-09 1995-05-24 日本電気株式会社 Thin film capacitor and manufacturing method thereof
JP3043124B2 (en) * 1991-08-26 2000-05-22 キヤノン株式会社 Traveling wave type motor device
US5382817A (en) * 1992-02-20 1995-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a ferroelectric capacitor with a planarized lower electrode
EP0739030A3 (en) * 1995-04-19 1998-07-08 Nec Corporation Highly-integrated thin film capacitor with high dielectric constant layer
KR100326979B1 (en) * 1996-12-18 2002-05-10 포만 제프리 엘 Metal to metal capacitor and method for producing same
JP4708905B2 (en) * 2005-08-05 2011-06-22 イビデン株式会社 Thin film embedded capacitance, manufacturing method thereof, and printed wiring board
CN104916440A (en) * 2015-06-09 2015-09-16 长兴友畅电子有限公司 Improved structure of film capacitor

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