JPH0685425B2 - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0685425B2 JPH0685425B2 JP60255292A JP25529285A JPH0685425B2 JP H0685425 B2 JPH0685425 B2 JP H0685425B2 JP 60255292 A JP60255292 A JP 60255292A JP 25529285 A JP25529285 A JP 25529285A JP H0685425 B2 JPH0685425 B2 JP H0685425B2
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- memory device
- groove
- island
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、一個のMOSトランジスタと一個のキャパシタ
によりメモリセルを構成する半導体記憶装置に関する。TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor memory device in which a memory cell is composed of one MOS transistor and one capacitor.
一個のMOSトランジスタと一個のキャパシタによりメモ
リセルを構成するダイナミック型半導体記憶装置（dRA
M）が近年、ますます高集積化されている。dRAMは、高
集積化に伴ってメモリセル面積が減少し、キャパシタ面
積も減少して、情報電荷蓄積量が非常に小さいものとな
っている。この結果、メモリセルの記憶情報が誤読され
たり、α線等により半導体基板内に発生する電荷で情報
内容が消失する、といった問題が現われている。A dynamic semiconductor memory device (dRA) in which a memory cell is composed of one MOS transistor and one capacitor.
M) has become more highly integrated in recent years. In the dRAM, the memory cell area and the capacitor area are reduced as the integration degree is increased, and the information charge storage amount is very small. As a result, problems such as erroneous reading of stored information in the memory cell and loss of information content due to electric charges generated in the semiconductor substrate due to α-rays and the like appear.
この様な問題を解決する方法として、メモリセル占有面
積を増大することなるキャパシタ面積を実質的に増大す
る構造がいくつか提案されている。一つは、半導体基板
のキャパシタ形成領域内に細溝を掘り、その溝の側壁を
利用してキャパシタ面積増大を図るものである。これに
より、キャパシタ容量を溝を掘らない場合の２〜３倍に
増加することができる。しかしこの構造では、dRAMを更
に高集積化する場合、隣接するメモリセルのキャパシタ
間でパンチスルー等により電荷の漏れが生じるという問
題が生じる。この対策としては、隣接するメモリセル間
の距離を大きくすればよいが、これはメモリセルの高集
積化，高密度化を妨げる。またキャパシタ溝を浅くする
ことも考えられるが、溝側壁から空乏層が伸び易いため
に充分に浅くしなければ効果がなく、これではキャパシ
タ容量の増大が図れない。As a method for solving such a problem, some structures have been proposed in which the area of the capacitor, which increases the area occupied by the memory cell, is substantially increased. One is to dig a fine groove in a capacitor formation region of a semiconductor substrate and use the side wall of the groove to increase the capacitor area. As a result, the capacitance of the capacitor can be increased to 2 to 3 times that in the case where the trench is not dug. However, in this structure, when dRAM is further highly integrated, there arises a problem that charge leakage occurs between capacitors of adjacent memory cells due to punch-through or the like. As a countermeasure for this, the distance between adjacent memory cells may be increased, but this hinders high integration and high density of the memory cells. It is also possible to make the capacitor groove shallow, but since the depletion layer easily extends from the side wall of the groove, there is no effect unless it is made sufficiently shallow, and this cannot increase the capacitance of the capacitor.
他の方法として、素子分離領域の溝を利用してキャパシ
タ面積の増大を図る構造が、本出願人により先に提案さ
れている。その構造を第５図により説明する。ｐ型Si基
板21の素子分離領域に溝22が形成され、この溝22で囲ま
れた島状半導体領域の側壁にキャパシタ絶縁膜23を介し
てキャパシタ電極24を対向させてMOSキャパシタが形成
されている。より詳しく言えば、キャパシタ電極西は、
島状半導体領域の端部の３つの側壁と上面の一部に対向
させている。キャパシタ電極24が対向する島状半導体領
域表面には容量を増大させるためにｎ型層25が形成され
ている。溝22の底部には、素子分離用の厚い絶縁膜26が
埋め込まれ、その下の基板には反転防止用のp+型層27が
形成されている。島状半導体領域の中ほどに、ゲート絶
縁膜28を介してゲード電極29が形成され、ソース，ドレ
インとなるn+型層30,31が形成されて、MOSトランジスタ
が構成されている。As another method, the present applicant has previously proposed a structure for increasing the capacitor area by utilizing the groove of the element isolation region. The structure will be described with reference to FIG. A trench 22 is formed in the element isolation region of the p-type Si substrate 21, and a MOS capacitor is formed on the side wall of the island-shaped semiconductor region surrounded by the trench 22 with the capacitor electrode 24 opposed to the side wall of the capacitor insulating film 23. There is. More specifically, the capacitor electrode west is
The three side walls at the end of the island-shaped semiconductor region and a part of the upper surface are opposed to each other. An n-type layer 25 is formed on the surface of the island-shaped semiconductor region facing the capacitor electrode 24 in order to increase the capacitance. A thick insulating film 26 for element isolation is buried in the bottom of the groove 22, and a p + -type layer 27 for preventing inversion is formed on the underlying substrate. A gate electrode 29 is formed in the middle of the island-shaped semiconductor region via a gate insulating film 28, and n + type layers 30 and 31 serving as a source and a drain are formed to form a MOS transistor.
この構造では、素子分離領域の溝を有効利用して大きい
キャパシタ面積を実現することができる。しかしこの構
造でdRAMを高集積化する場合、技術的に可能な最小き幅
で溝を形成することになるが、これでは溝の深さに限界
が生じ、また狭く且つ深く形成された溝底部に素子分離
用絶縁膜を埋込むことも難しい。従ってある値以上のキ
ャパシタ容量を得るためには溝の幅をある程度以上広く
しなければならない。With this structure, a large capacitor area can be realized by effectively utilizing the groove of the element isolation region. However, when dRAM is highly integrated with this structure, a groove is formed with the minimum technically possible width, but this causes a limit to the groove depth, and the groove bottom that is narrow and deep is formed. It is also difficult to embed an element isolation insulating film in the. Therefore, the width of the groove must be widened to some extent in order to obtain a capacitor capacitance of a certain value or more.
本発明は上記した点に鑑みてなされたもので、より小さ
い占有面積でより大きいキャパシタ容量を実現し、信頼
性を低下させることなく高集積化を図った半導体記憶装
置を提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor memory device that realizes a larger capacitor capacitance with a smaller occupied area and achieves higher integration without lowering reliability. To do.
本発明にかかる半導体記憶装置は、第５図の構造を基本
とし、その島状半導体領域のキャパシタ電極が対向する
側壁を階段状にしたことを特徴とする。The semiconductor memory device according to the present invention is based on the structure shown in FIG. 5, and is characterized in that the side walls of the island-shaped semiconductor region facing the capacitor electrodes are stepwise shaped.
本発明によれば、キャパシタを構成する島状半導体領域
の側壁を階段状に形成することにより、大きい占有面積
を要することなく大きいキャパシタ面積を実現すること
ができる。また、階段状をなして次第に深く且つ狭くな
る素子分離溝の最深部に厚い分離用絶縁膜を設けること
により、隣接するメモリセルのキャパシタ間の分離は確
実に行なわれる。従って本発明によれば、信頼性が高く
且つ高集積化したdRAMが得られる。According to the present invention, by forming the sidewalls of the island-shaped semiconductor region forming the capacitor in a stepwise manner, a large capacitor area can be realized without requiring a large occupied area. Further, by providing a thick insulating film for isolation in the deepest part of the element isolation trench which becomes stepwise and becomes deeper and narrower, the isolation between the capacitors of the adjacent memory cells is surely performed. Therefore, according to the present invention, a highly reliable and highly integrated dRAM can be obtained.
以下本発明の実施例を説明する。 Examples of the present invention will be described below.
第１図（ａ）〜（ｄ）は一実施例のdRAMを示す。（ａ）
は平面図であり、（ｂ），（ｃ）および（ｄ）はそれぞ
れ（ａ）のＡ−Ａ′,B−Ｂ′およびＣ−Ｃ′断面図であ
る。これを製造工程に従って説明すると、ｐ型Si基板１
の素子分離領域にRIEにより溝を掘り、階段状の側壁２
を有する長方形パターンの複数の島状半導体領域を形成
する。階段状溝掘りの具体的な工程例は後述する。素子
分離溝には、反転防止のためのp+型層４を形成し、素子
分離用絶縁膜３を埋込む。p+型層４は、キャパシタ領域
以外の全ての露出している階段状溝部に（第１図
（ｃ））、またキャパシタ領域には溝の最深部にのみ
（第１図（ｄ））形成される。また素子分離用絶縁膜３
としては、MOSトランジスタのゲート電極が走る部分に
は溝が完全に平坦になるように厚い絶縁膜31が埋め込ま
れ（第１図（ｃ））、キャパシタが形成される部分では
階段状側壁２を露出させるよう最深部にのみ選択的に絶
縁膜32が埋め込まれる（第１図（ｂ）（ｄ））。これ
は、一旦素子分離溝に完全に絶縁膜を埋込み、その後キ
ャパシタ領域の絶縁膜を一部エッチングして最深部にの
み所定厚さの絶縁膜32を残すようにすればよい。そして
キャパシタ領域となる各島状半導体領域の端部の３つの
側壁と上面に例えば固相拡散を利用してｎ型層５を形成
し、その表面に熱酸化によりキャパシタ絶縁膜５を形成
して、第１層多結晶シリコン膜の堆積，パターニングに
よりキャパシタ電極７を形成する。この後、MOSトラン
ジスタを形成する。即ち、熱酸化によりゲート絶縁膜８
を形成し、この上に第２層多結晶シリコン膜の堆積，パ
ターニングによりゲート電極９を形成し、Asのイオン注
入によりソース，ドレインとなるn+型層10,11を形成す
る。この後は図では省略したが、通常の工程に従い全面
をCVD酸化膜で覆い、コンタクト孔を開けてAl配線を形
成してdRAMが完成する。ゲート電極９は一方向のメモリ
セルに共通に配設されてこれがワード線となり、またワ
ード線と直交する方向のメモリセルについてドレインが
Al配線により共通接続されて、これがビット線となる。FIGS. 1A to 1D show a dRAM according to an embodiment. (A)
Is a plan view, and (b), (c), and (d) are cross-sectional views taken along line AA ′, BB ′, and CC ′ of (a), respectively. This will be described according to the manufacturing process. The p-type Si substrate 1
A trench is dug in the element isolation region of the RIE to form a stepped sidewall 2
Forming a plurality of island-shaped semiconductor regions having a rectangular pattern. A specific process example of the stepwise trench digging will be described later. A p + -type layer 4 for preventing inversion is formed in the element isolation groove, and the element isolation insulating film 3 is embedded therein. The p + -type layer 4 is formed in all exposed stepped trenches other than the capacitor region (FIG. 1 (c)), and only in the deepest portion of the trench in the capacitor region (FIG. 1 (d)). To be done. Insulating film 3 for element isolation
The, MOS the portion running the gate electrode of the transistor trench completely insulating film 103 1 so flat is embedded (FIG. 1 (c)), stepped side wall 2 in a portion where the capacitor is formed selectively insulating film 3 2 only at the deepest portion is embedded so as to expose the (FIG. 1 (b) (d)). This once fully insulating film in the element isolation trench buried, then it is sufficient only to leave the insulating film 3 and second predetermined thickness of the insulating film of the capacitor region in a part etched and deepest. Then, the n-type layer 5 is formed on the three side walls and the upper surface of the end of each island-shaped semiconductor region to be the capacitor region by utilizing, for example, solid phase diffusion, and the capacitor insulating film 5 is formed on the surface by thermal oxidation. Then, the capacitor electrode 7 is formed by depositing and patterning the first-layer polycrystalline silicon film. After that, a MOS transistor is formed. That is, the gate insulating film 8 is formed by thermal oxidation.
Then, a gate electrode 9 is formed by depositing and patterning a second-layer polycrystalline silicon film on this, and by ion implantation of As, n + type layers 10 and 11 serving as a source and a drain are formed. After this, although not shown in the figure, the entire surface is covered with a CVD oxide film, contact holes are opened and Al wiring is formed according to a normal process, and the dRAM is completed. The gate electrode 9 is commonly provided to the memory cells in one direction, which serves as a word line, and the drain of the memory cell in the direction orthogonal to the word line
It is commonly connected by Al wiring, and this becomes a bit line.
第２図（ａ）〜（ｆ）は、階段状側壁をもつ素子分離溝
の形成工程例を、第１図（ｂ）の断面について示す。先
ず（ａ）に示すように、基板１に素子領域を覆う第１の
フォトレジスト・マスク121を形成し、RIEにより基板表
面をエッチングして浅い溝を形成する。この溝には、次
のPEP工程を容易にするために（ｂ）に示すように、CVD
による酸化膜131を埋め込んで平坦化する。そして
（ｃ）に示すように、第１のマスク121より僅かに周辺
を拡張した第２のフォトレジストマスク122を形成し、
再度RIEを行って先に形成した溝より深い溝を形成す
る。この溝は再び（ｄ）に示すようにCVDによる酸化膜1
32を埋め込んで平坦化する。そして（ｅ）に示すよう
に、第２のマスク122より更に周辺を拡張した第３のフ
ォトレジスト・マスク123を形成し、再度RIEを行って２
回目の溝より深い溝を形成する。こうして既に埋め込ん
だ酸化膜131,132を除去すると、（ｆ）に示すように階
段状側壁２をもつ素子分離溝が形成される。2 (a) to 2 (f) show an example of a process of forming an element isolation groove having a stepwise side wall with respect to the cross section of FIG. 1 (b). First, as shown in (a), a first photoresist mask 121 covering the element region is formed on the substrate 1, and the surface of the substrate is etched by RIE to form a shallow groove. In this groove, as shown in (b), to facilitate the next PEP process, CVD
The oxide film 13 1 is buried and planarized. Then, as shown in (c), a second photoresist mask 12 2 whose periphery is slightly expanded from the first mask 12 1 is formed,
RIE is performed again to form a groove deeper than the groove previously formed. This groove is again formed by the CVD oxide film 1 as shown in (d).
3 2 is embedded and flattened. Then, as shown in (e), a third photoresist mask 12 3 whose periphery is further expanded than the second mask 12 2 is formed, and RIE is performed again to perform 2
A groove deeper than the first groove is formed. By removing the oxide films 13 1 and 13 2 already buried in this way, the element isolation trench having the stepwise side wall 2 is formed as shown in (f).
なお、反転防止用p+型層４は、第２図（ａ）（ｃ）およ
び（ｆ）の段階でキャパシタ領域およびトランジスタ領
域以外には例えば斜めイオン注入を用いて形成される。
イオン注入の代わりに固相拡散を利用することもでき
る。そして第２図（ｆ）のように素子分離溝が形成され
た後、溝をCVD絶縁膜で平坦に埋め込み、キャパシタ電
極形成領域についてこの絶縁膜を選択エッチングして溝
の最深部に所定厚みの絶縁膜を残すようにする。The inversion prevention p + -type layer 4 is formed by using, for example, oblique ion implantation except the capacitor region and the transistor region in the steps of FIGS. 2 (a), (c) and (f).
Solid phase diffusion can be used instead of ion implantation. Then, after the element isolation trench is formed as shown in FIG. 2 (f), the trench is flatly filled with a CVD insulating film, and this insulating film is selectively etched in the capacitor electrode formation region to have a predetermined thickness at the deepest portion of the trench. Leave the insulating film.
この実施例によれば、島状半導体領域の端部の３つの階
段状側壁と上面の一部を利用してMOSキャパシタが形成
されるから、垂直壁のみを利用する従来の構造に比べて
小さい占有面積で大きいキャパシタ容量を実現すること
ができる。また隣接するメモリセルのキャパシタ間の分
離は、溝の最深部に埋め込まれた絶縁膜32とその下のp+
型層４により確実に行なわれ、キャパシタ領域に素子分
離領域の基板界面より深い溝を形成する構造に比べてパ
ンチスルーなどが生じ難くなっている。従って信頼性の
高い、高集積化dRAMが得られる。According to this embodiment, since the MOS capacitor is formed by utilizing the three stepwise side walls at the end of the island-shaped semiconductor region and a part of the upper surface, it is smaller than the conventional structure using only the vertical wall. A large capacitor capacity can be realized in the occupied area. The separation between adjacent memory cell capacitor, with the insulating film 3 2 embedded in the deepest portion of the groove beneath the p +
Punch-through is less likely to occur as compared with a structure in which a groove deeper than the substrate interface of the element isolation region is formed in the capacitor region more reliably by the mold layer 4. Therefore, a highly reliable and highly integrated dRAM can be obtained.
第３図は本発明の他の実施例のdRAMを第１図（ｂ）の断
面に対応させて示したものである。この実施例では、キ
ャパシタ電極７にMOSトランジスタのゲート電極９を一
部重ねるようにして、ソース領域のn+型層を省略してい
る。それ以外は先の実施例と同様である。この実施例に
よっても先の実施例と同様の効果が得られる他、電極を
重ねることでビット当りの占有面積かより小さくなり、
dRAMの一層の高密度化が図られるという効果が得られ
る。FIG. 3 shows a dRAM according to another embodiment of the present invention in correspondence with the cross section of FIG. 1 (b). In this embodiment, the gate electrode 9 of the MOS transistor is partially overlapped with the capacitor electrode 7, and the n + type layer in the source region is omitted. Other than that is the same as the previous embodiment. According to this embodiment as well, the same effect as the previous embodiment can be obtained, and by overlapping the electrodes, the occupied area per bit becomes smaller,
The effect that the density of the dRAM can be further increased is obtained.
第４図は更に他の実施例のdRAMを第１図（ｂ）の断面に
対応させて示したものである。この実施例では基板１を
高濃度のp+Si基板11とこれと同じ導電型の低濃度ｐ型層
12との積層構造としている。そして素子分離溝の最深部
がp+基板11に達するように形成されている。この実施例
の場合は、溝底部に反転防止用のp+型層を形成する工程
が不要となる。FIG. 4 shows a dRAM of another embodiment corresponding to the cross section of FIG. 1 (b). In this embodiment, the substrate 1 is a high-concentration p + Si substrate 11 and a low-concentration p-type layer of the same conductivity type.
It has a laminated structure with 1 2 . The deepest portion of the element isolation grooves are formed so as to reach the p + substrate 1 1. In the case of this embodiment, the step of forming a p + -type layer for preventing inversion at the groove bottom is unnecessary.
本発明は上記した実施例に限られるものではない。例え
ば、キャパシタ領域に形成されるｎ型層５は、若干キャ
パシタ容量が小さくなるが、省略することが可能であ
る。また各部の導電型を実施例と逆にすることも可能で
ある。更に実施例では素子分離溝を形成する工程例とし
て浅い溝部分から順次深い溝を形成していく例を挙げた
が、これと逆に先ず小さい窓のマスクを用いてRIEを行
い、順次マクスの窓を大きくして複数回のRIEを行うこ
とにより、実施例と同様に階段状側壁を形成することが
できる。この場合には、各RIE工程の後に溝を平坦化す
る工程が不要となる。その他の本発明は、その趣旨を逸
脱しない範囲で更に種々変形して実施することができ
る。The present invention is not limited to the above embodiments. For example, although the n-type layer 5 formed in the capacitor region has a slightly smaller capacitor capacitance, it can be omitted. It is also possible to reverse the conductivity type of each part to that of the embodiment. Further, in the embodiment, as an example of the process of forming the element isolation groove, an example in which the deep groove is sequentially formed from the shallow groove portion is given. On the contrary, RIE is first performed using the mask of the small window, and the sequential mask of By making the window large and performing RIE a plurality of times, it is possible to form the stepwise side wall as in the embodiment. In this case, the step of flattening the groove after each RIE step becomes unnecessary. Other aspects of the invention can be implemented with various modifications without departing from the spirit of the invention.
第１図（ａ）〜（ｄ）は本発明の一実施例のdRAMを示す
図、第２図（ａ）〜（ｆ）はその素子分離溝の形成工程
を示す図、第３図および第４図は他の実施例のdRAMを示
す図、第５図は従来のdRAMを示す図である。 １…ｐ型Si基板、２…階段状側壁、31,32…素子分離用
絶縁膜、４…反転防止用p+型層、５…ｎ型層、６…キャ
パシタ絶縁膜、７…キャパシタ電極、８…ゲート絶縁
膜、９…ゲート電極、10,11…n+型層。1 (a) to 1 (d) are diagrams showing a dRAM of one embodiment of the present invention, and FIGS. 2 (a) to 2 (f) are diagrams showing a process of forming an element isolation trench thereof, FIG. 3 and FIG. FIG. 4 is a diagram showing a dRAM of another embodiment, and FIG. 5 is a diagram showing a conventional dRAM. DESCRIPTION OF SYMBOLS 1 ... p-type Si substrate, 2 ... staircase side wall, 3 1 , 3 2 ... element isolation insulating film, 4 ... inversion prevention p + type layer, 5 ... n-type layer, 6 ... capacitor insulating film, 7 ... capacitor Electrodes, 8 ... Gate insulating film, 9 ... Gate electrodes, 10, 11 ... N + type layers.
Claims (3)
れた複数の島状半導体領域に一個のMOSトランジスタと
一個のキャパシタからなるメモリセルを集積形成して構
成され、かつ前記キャパシタは前記島状半導体領域の側
壁に絶縁膜を介してキャパシタ電極を対向させて構成さ
れた半導体記憶装置において、前記島状半導体領域の前
記キャパシタ電極が対向する側壁を階段状としたことを
特徴とする半導体記憶装置。1. A memory cell comprising a MOS transistor and a capacitor is integrally formed in a plurality of island-shaped semiconductor regions surrounded by the trench by digging a groove in an element isolation region of the substrate, and the capacitor is formed. In a semiconductor memory device having a capacitor electrode facing a sidewall of the island-shaped semiconductor region with an insulating film interposed therebetween, the sidewall of the island-shaped semiconductor region facing the capacitor electrode has a stepped shape. Semiconductor memory device.
成され、前記キャパシタはその長手方向端部の３つの側
壁と上面に絶縁膜を介してキャパシタ電極を対向させて
構成されている特許請求の範囲第１項記載の半導体記憶
装置。2. The island-shaped semiconductor region is formed in a rectangular pattern, and the capacitor is formed by facing three side walls and an upper surface of a longitudinal end of the capacitor with capacitor electrodes facing each other with an insulating film interposed therebetween. A semiconductor memory device according to claim 1.
電型の低濃度半導体層が積層されて構成され、階段状側
壁をもって形成される溝の最深部が前記高濃度半導体基
板に達する深さに形成されている特許請求の範囲第１項
記載の半導体記憶装置。3. The substrate is formed by laminating a high-concentration semiconductor substrate and a low-concentration semiconductor layer of the same conductivity type as that of the high-concentration semiconductor substrate, and the deepest portion of the groove formed with the stepwise sidewall reaches the high-concentration semiconductor substrate. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is formed in the following manner.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255292A JPH0685425B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60255292A JPH0685425B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62114263A JPS62114263A (en) | 1987-05-26 |
| JPH0685425B2 true JPH0685425B2 (en) | 1994-10-26 |
Family
ID=17276734
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60255292A Expired - Fee Related JPH0685425B2 (en) | 1985-11-14 | 1985-11-14 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0685425B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0333426B1 (en) * | 1988-03-15 | 1996-07-10 | Kabushiki Kaisha Toshiba | Dynamic RAM |
| JPH04162566A (en) * | 1990-10-25 | 1992-06-08 | Nec Corp | Semiconductor memory device |
-
1985
- 1985-11-14 JP JP60255292A patent/JPH0685425B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62114263A (en) | 1987-05-26 |
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