JPH0685081A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH0685081A JPH0685081A JP12481592A JP12481592A JPH0685081A JP H0685081 A JPH0685081 A JP H0685081A JP 12481592 A JP12481592 A JP 12481592A JP 12481592 A JP12481592 A JP 12481592A JP H0685081 A JPH0685081 A JP H0685081A
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact hole
- semiconductor device
- silicon
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置およびその製
造方法に関し、特に不純物を含むシリコン膜より成るコ
ンタクトホールの埋め込み層を有する半導体装置および
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a contact hole filling layer made of a silicon film containing impurities and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】従来、半導体基板上の所定の位置に設け
られたコンタクトホールの埋め込み層としては、例えば
タングステンシリサイド等の合金を材料とするものがあ
った。この合金を材料とする埋め込み層の形成方法とし
ては、スパッタ法を用いてコンタクトホールを埋め込む
のに充分な量の合金を半導体装置上に被着させた後、ド
ライエッチング技術を用いてこの合金の内コンタクトホ
ール内の埋め込み層を残し、それ以外を除去することに
より形成していた。2. Description of the Related Art Heretofore, as a buried layer for a contact hole provided at a predetermined position on a semiconductor substrate, there has been one made of an alloy such as tungsten silicide as a material. As a method of forming a buried layer using this alloy as a material, a sufficient amount of an alloy for filling a contact hole is deposited on a semiconductor device by using a sputtering method, and then this alloy is dried by using a dry etching technique. It was formed by leaving the buried layer in the inner contact hole and removing the rest.
【０００３】また不純物を含む１種類のシリコン膜をコ
ンタクトホールに埋め込んで埋め込み層とする半導体装
置もあった。この形成方法の一例を次に説明する。まず
減圧ＣＶＤ法により多結晶シリコン膜を成膜し、イオン
注入法を用いてリン等の不純物をこの膜に打ち込み、次
にこの多結晶シリコン膜の抵抗率を下げる目的で熱処理
を行なって不純物を拡散した後、前記合金の場合同様の
エッチングを行ない埋め込み層を残していた。In some semiconductor devices, a contact layer is filled with one type of silicon film containing impurities to form a buried layer. An example of this forming method will be described below. First, a polycrystalline silicon film is formed by a low pressure CVD method, impurities such as phosphorus are implanted into this film by an ion implantation method, and then a heat treatment is performed to reduce the resistivity of the polycrystalline silicon film to remove impurities. After the diffusion, the same etching was carried out in the case of the above alloy, and the buried layer was left.
【０００４】また不純物を含む１種類のシリコン膜より
成るコンタクトホールの埋め込み層の他の形成方法とし
ては、ドープガスとしてホスフィン，成膜ガスとしてシ
ランあるいはジシランのいずれか一方のみを用いて減圧
ＣＶＤ法により、成膜中にリンがドープされた状態のシ
リコン膜を成膜した後、熱処理，コンタクトホール内以
外のエッチングを行ない抵抗率の低い埋め込み層を形成
していた。As another method of forming a contact hole burying layer formed of one type of silicon film containing impurities, a low pressure CVD method using phosphine as a doping gas and silane or disilane as a film forming gas is used. After forming a silicon film in which phosphorus is doped during film formation, heat treatment and etching other than in the contact hole are performed to form a buried layer having a low resistivity.
【０００５】[0005]
【発明が解決しようとする課題】前述の方法を近年の高
アスペクト比（つまり開口部が小さく深い形状）のコン
タクトホールに用いると種々の不具合が生じていた。例
えば、スパッタ法ではタングステンシリサイド分子がコ
ンタクトホール側面上部に先に付着し開口部分がふさが
ってしまう問題があり、このため高アスペクト比になる
ほどコンタクトホール内部を完全に埋め込むことは困難
になってきた。またイオン注入法で不純物を打ち込んだ
後、熱拡散を行なう方法に関しては、高アスペクト比の
コンタクトホールの深さ方向の不純物の注入量制御が困
難であるため、この深いコンタクトホール内部に不純物
を拡散させるためには成膜→注入→熱拡散という工程を
複数回行なわねばならなくなり、工程手順が増大してし
まう問題があった。 次に成膜ガスにシランのみを用い
かつドープガスにホスフィンを用いたＣＶＤ技術により
形成された埋め込み層の場合、成膜する際の成長温度
は、量産に応じた成長速度を得るために５７０℃以上必
要である。しかしこの温度で成長した不純物を含みシリ
コン膜は、熱処理した後においても結晶粒が小さいため
に抵抗率が高く、特に１０００オングストローム以下の
薄い膜は、著しく抵抗率が高いという問題があった。こ
の原因のためシランを成膜ガスとして用いて形成したコ
ンタクトホールの埋め込み層は、近年の開口径の狭いコ
ンタクトホールに用いるとプラグ抵抗が高くなり過ぎ
て、半導体装置への適用が困難になっていた。When the above-mentioned method is used for a contact hole having a high aspect ratio (that is, a small opening and a deep shape) in recent years, various problems have occurred. For example, in the sputtering method, there is a problem that the tungsten silicide molecules are first attached to the upper side surface of the contact hole and the opening is blocked, so that it becomes difficult to completely fill the inside of the contact hole as the aspect ratio becomes higher. Regarding the method of performing thermal diffusion after implanting impurities by the ion implantation method, it is difficult to control the implantation amount of impurities in the depth direction of a high aspect ratio contact hole. In order to do so, the steps of film formation → implantation → thermal diffusion must be carried out multiple times, and there was a problem that the process procedure increased. Next, in the case of a buried layer formed by a CVD technique using only silane as a film forming gas and phosphine as a dope gas, the growth temperature during film formation is 570 ° C. or higher in order to obtain a growth rate according to mass production. is necessary. However, the silicon film containing impurities grown at this temperature has a high resistivity because the crystal grains are small even after the heat treatment, and there is a problem that the thin film having a thickness of 1000 angstroms or less has a remarkably high resistivity. For this reason, the contact hole burying layer formed by using silane as a film forming gas has a too high plug resistance when used for a contact hole having a small opening diameter in recent years, which makes it difficult to apply to a semiconductor device. It was
【０００６】成膜ガスとしてジシランかつドープガスと
してホスフィンを用いたＣＶＤ技術によって形成された
埋め込み層の場合、前述のシランガスを用いて成膜する
場合と異なり、４９０℃程度の比較的低い温度での成膜
が可能であり、このため熱処理後の結晶径は大きくなり
低抵抗な膜が形成できる。また薄い膜では高抵抗率にな
るという問題もほとんどない。しかしながらこの膜は、
段差被覆性が悪いという性質があるため開口径の細いコ
ンタクトホールの埋め込み層を形成する目的で、成膜が
ガスにジシラン，ドープガスにホスフィンを用いて成膜
すると、図６に示すように、層間膜１３中に形成された
コンタクトホール内のシリコン膜２３による埋め込み層
の中心部にボイド２２が発生してしまい、このボイドが
製品の段階でも残ってしまいコンタクトホール抵抗が高
くなったり、断線してしまって半導体装置の信頼性を低
下させる原因になる問題点があった。In the case of a buried layer formed by a CVD technique using disilane as a film forming gas and phosphine as a doping gas, unlike the case of forming a film using the above-mentioned silane gas, the formation at a relatively low temperature of about 490 ° C. It is possible to form a film, so that the crystal diameter after heat treatment becomes large and a low resistance film can be formed. Moreover, there is almost no problem that the thin film has a high resistivity. However, this membrane
Since disilane is used as a gas and phosphine is used as a dope gas for the purpose of forming a buried layer of a contact hole having a small opening diameter because of the poor step coverage, as shown in FIG. A void 22 is generated at the center of the buried layer formed by the silicon film 23 in the contact hole formed in the film 13, and the void remains at the product stage, resulting in a high contact hole resistance or disconnection. Therefore, there is a problem in that the reliability of the semiconductor device is deteriorated.
【０００７】[0007]
【課題を解決するための手段】本発明によれば、コンタ
トホールの埋め込み層に埋め込まれた不純物を含むシリ
コン膜が第１のシリコン膜と第２のシリコン膜の２層に
よりなる半導体装置を得る。また本発明によればコンタ
クトホールの埋め込み工程に関し、第１のガス系を用い
て不純物を有するシリコン膜を成長した後、第２のガス
系を用いて不純物を含むシリコン膜を成長してコンタク
トホールを埋め込む半導体装置の製造方法を得る。According to the present invention, there is obtained a semiconductor device in which a silicon film containing an impurity buried in a buried layer of a contact hole comprises two layers of a first silicon film and a second silicon film. Further, according to the present invention, regarding the step of filling the contact hole, a silicon film containing impurities is grown by using the first gas system, and then a silicon film containing impurities is grown by using the second gas system. A method of manufacturing a semiconductor device in which a semiconductor device is embedded is obtained.
【０００８】なお、本発明の半導体装置の製造方法で
は、コンタクトホールの埋め込み工程が、第１のガス系
を用いて不純物を含むシリコン膜を成長する工程と、第
２のガス系を用いて不純物を含むシリコン膜を成長する
工程との間に熱処理工程を有しても良い。In the method of manufacturing a semiconductor device according to the present invention, the step of filling the contact hole includes the step of growing a silicon film containing impurities using the first gas system and the step of growing impurities using the second gas system. A heat treatment step may be included between the step of growing the silicon film containing a.
【０００９】[0009]
【実施例】本発明の一実施例の半導体装置の断面図を図
１に示す。このコンタクトホールは、次の製造方法で形
成される。1 is a sectional view of a semiconductor device according to an embodiment of the present invention. This contact hole is formed by the following manufacturing method.
【００１０】まず半導体基板１１にフォトレジストをマ
スクとしてイオン注入技術により選択的に拡散層１２を
形成する。次に減圧ＣＶＤ法によりシリコン酸化膜の層
間膜１３を１μｍの厚さで形成する。この層間膜の表面
にフォトレジストを塗布し、リソグラフィー技術により
所定の位置にコンタクトのパターンを形成し、これをマ
スクとしてプラズマエッチング装置を用いて層間膜１３
内にコンタクトホール１４を形成し、フォトレジストを
除去する。この工程までの状態の断面図を図３に示す。First, the diffusion layer 12 is selectively formed on the semiconductor substrate 11 by an ion implantation technique using a photoresist as a mask. Next, an interlayer film 13 of a silicon oxide film is formed to a thickness of 1 μm by the low pressure CVD method. Photoresist is applied to the surface of the interlayer film, a contact pattern is formed at a predetermined position by a lithographic technique, and the interlayer film 13 is formed by using this as a mask and a plasma etching apparatus.
A contact hole 14 is formed inside and the photoresist is removed. A sectional view of the state up to this step is shown in FIG.
【００１１】本発明は、図２のコンタクトホールを一例
とする半導体基板上の所定の位置に設けられたコンタク
トホール内に、不純物を含む結晶性の異なった２層のシ
リコン膜がある構造とその成膜方法に特徴がある。以下
にコンタクトホール内の構造および埋込方法を説明す
る。The present invention has a structure in which there are two layers of silicon films containing impurities and having different crystallinity in contact holes provided at predetermined positions on a semiconductor substrate, the contact hole of FIG. 2 being an example. The film forming method is characterized. The structure in the contact hole and the burying method will be described below.
【００１２】図２（ａ）は本発明による成膜の一実施例
を示す成膜条件テーブルである。図２（ａ）において横
軸は成長開始からの時刻であり、縦軸は左側が成膜ガス
およびドープガスの流量、右側が炉内温度に示す。FIG. 2A is a film forming condition table showing an embodiment of film forming according to the present invention. In FIG. 2A, the horizontal axis represents the time from the start of growth, the vertical axis represents the film forming gas and doping gas flow rates on the left side, and the furnace temperature on the right side.
【００１３】成長は最初に成膜ガスとしてジシラン，ド
ープガスとしてホスフィンを用いて行なう。ホスフィン
はヘリウムにより１％に希釈したものを用いている。成
膜時の炉内温度は４９０℃程度であり、炉内圧力は約
０．２５Ｔｏｒｒである。ガスの流量はジシラン１００
ｓｃｃｍ，希釈ホスフィン８０ｓｃｃｍで時刻ｔ1 まで
の間成膜を行なう。地獄ｔ1 での半導体装置の工程別断
面図を図４（ａ）に示す。成膜開始からｔ1 までの間に
コンタクトホール２１内および層間膜１３の表面に第１
のシリコン膜４１が形成される。ｔ1 は第１のシリコン
膜４１が約１００オングストローム成長した時刻とす
る。時刻ｔ1 になったら一度反応ガスの供給を停止し、
炉内温度を５７０℃迄上昇させ安定させる。安定した時
刻ｔ2 以降は成膜ガスとしてシランを用いる。炉内圧力
は０．６０Ｔｏｒｒまで上げ、シランの流量を８００ｓ
ｃｃｍ，ホスフィンの流量を１２０ｓｃｃｍにて目標と
する膜厚となるまで成膜を行ない、ここで第２のシリコ
ン膜１２が形成される。図４（ｂ）は第２の成膜が終了
した時点の工程別断面図である。この時点ではコンタク
トホール部以外にも、第１・第２のシリコン膜が残って
いるため、次に全面をドライエッチング技術を用いてエ
ッチバックする。エッチバックの工程によりコンタクト
ホール部以外の第１・第２のシリコン膜が除去されコン
タクトの埋込層１６が形成される。この時点での工程別
断面図を図５に示す。この後窒素アニールを行なってか
らスパッタ法を用いてアルミ等の金属を被着させた後、
リソグラフィー技術及びドライエッチング技術等を用い
て配線層１７を形成し、本発明の一実施例である半導体
装置が出来上がる。出来上がった半導体装置の断面図を
図１に示す。First, the growth is performed using disilane as a film forming gas and phosphine as a doping gas. The phosphine used is diluted to 1% with helium. The temperature in the furnace during film formation is about 490 ° C., and the pressure in the furnace is about 0.25 Torr. The gas flow rate is disilane 100
Film formation is performed at a sccm of 80 sccm of diluted phosphine until time t 1 . FIG. 4A is a cross-sectional view of the semiconductor device in each process at hell t 1 . During the period from the start of film formation to t 1 , the first contact hole 21 and the surface of the interlayer film 13
The silicon film 41 is formed. Let t 1 be the time when the first silicon film 41 has grown to about 100 Å. At time t 1 , the supply of the reaction gas is stopped once,
The temperature inside the furnace is raised to 570 ° C and stabilized. After the stable time t 2 , silane is used as a film forming gas. The furnace pressure was raised to 0.60 Torr and the flow rate of silane was 800s.
The film formation is performed until the target film thickness is obtained with the flow rate of ccm and phosphine of 120 sccm, and the second silicon film 12 is formed here. FIG. 4B is a cross-sectional view for each step when the second film formation is completed. At this point, the first and second silicon films are left in addition to the contact hole portion, so that the entire surface is next etched back using the dry etching technique. By the etch back process, the first and second silicon films other than the contact hole portion are removed to form the contact buried layer 16. FIG. 5 shows cross-sectional views for each step at this point. After this, after performing nitrogen annealing, a metal such as aluminum is deposited by using a sputtering method,
The wiring layer 17 is formed by using the lithography technique and the dry etching technique, and the semiconductor device according to the embodiment of the present invention is completed. A sectional view of the completed semiconductor device is shown in FIG.
【００１４】この方法により形成されたリンを不純物と
して含むシリコンの２層膜は成長の初期のみ結晶径の大
きい低温成膜が実現できるためにシランを成膜ガスとし
て用いた膜の優れた段差被覆性とジシランを成膜ガスと
して用いた成膜による薄膜においての低抵抗性を兼ね備
えている。実際にこの方法により成膜を行なった結果、
被覆形状としては口径０．２μｍ・深さ１μｍのアスペ
クト比５のコンタクトホールに対してもボイドの発生は
なかった。Since the two-layer film of silicon containing phosphorus as an impurity formed by this method can realize low-temperature film formation with a large crystal diameter only in the initial stage of growth, excellent step coverage of a film using silane as a film-forming gas. And a low resistance in a thin film formed by using disilane as a film forming gas. As a result of actually forming a film by this method,
As a coating shape, no void was generated even in a contact hole having an aperture ratio of 0.2 μm and a depth of 1 μm and an aspect ratio of 5.
【００１５】また本実施例で製造した半導体装置のコン
タクト抵抗（プラグ抵抗を含む）は口径０．２μｍ・深
さ１μｍのコンタクトに対しても約８００Ωという低い
値が得られた。また抵抗率については５００オングスト
ロームの薄膜でも８００μｍ・ｃｍという良好な値が得
られた。Further, the contact resistance (including the plug resistance) of the semiconductor device manufactured in this example was as low as about 800Ω for a contact having a diameter of 0.2 μm and a depth of 1 μm. Regarding the resistivity, a good value of 800 μm · cm was obtained even with a thin film of 500 Å.
【００１６】図２（ｂ）は本発明による成膜法の他の実
施例を示す成膜条件テーブルである。図の横軸・縦軸は
図２（ａ）と同じである。成膜の最初は一実施例と同一
条件であるジシランを成膜ガス，１％ホスフィンをドー
プガスとして用いた成膜であるが、この実施例では膜厚
が１５０オングストローム程度になった時点ｔ3 で反応
ガスの供給を一時停止させる。ｔ3 での工程別断面図を
図４（ａ）に示す。次に炉内に窒素を送り込んで大気圧
とした後、引き続き６２０℃まで炉内温度を上げ、安定
した後約１時間窒素の流れる炉内でアニールを行なう。
アニールが終わったら自然冷却で５７０℃まで炉温を下
げ、安定させる。安定した時の時刻をｔ4 とする。ｔ4
での工程別断面図を図４（ｂ）に示す。ｔ4 以降は一実
施例と同じ条件で目標とする膜厚になるまでシランを成
膜ガス，１％ホスフィンをドープガスとして用いた成膜
を行なう。この後も一実施例と同じ様に窒素アニールを
行ない、スパッタ法によりＡｌ等を被着させ、リソグラ
フィー技術及びドライエッチング技術を用いて配線層１
７を形成する。FIG. 2B is a film forming condition table showing another embodiment of the film forming method according to the present invention. The horizontal and vertical axes in the figure are the same as those in FIG. At the beginning of film formation, disilane was used under the same conditions as in Example 1 as a film forming gas and 1% phosphine was used as a doping gas. In this example, the film thickness was about 150 angstroms at time t 3 . The supply of the reaction gas is temporarily stopped. A sectional view for each step at t 3 is shown in FIG. Next, nitrogen is fed into the furnace to bring it to atmospheric pressure, then the temperature in the furnace is raised to 620 ° C., and after stabilizing, annealing is performed in the furnace in which nitrogen flows for about 1 hour.
After the annealing is completed, the temperature of the furnace is lowered to 570 ° C by natural cooling to stabilize it. The time when it becomes stable is t 4 . t 4
4B is a cross-sectional view of each process in FIG. t 4 later performs film formation using deposition gas to silane until the film thickness of the target under the same conditions as an example, a 1% phosphine as doping gas. After that, nitrogen annealing is performed in the same manner as in the first embodiment, Al or the like is deposited by the sputtering method, and the wiring layer 1 is formed by using the lithography technique and the dry etching technique.
Form 7.
【００１７】以上の方法により得られるリンを不純物と
して含むシリコン膜はシランを成膜ガスとして用いた成
膜による優れた段差被覆性とジシランを成膜ガスとして
用いた成膜による薄膜においての低抵抗性を兼ね備えて
いる。更に一実施例に比べて、成長初期で得られる膜の
結晶性が上り安定になるため、より低抵抗な膜が得られ
る。この方法により成膜を行なった結果、被覆形状とし
ては口径０．２μｍ、深さ１μｍのアスペクト比５のコ
ンタクトホールでもボイドの発生もなく、良好な埋め込
み性が確認された。The silicon film containing phosphorus as an impurity obtained by the above method has excellent step coverage by film formation using silane as a film forming gas and low resistance in a thin film formed by film formation using disilane as a film forming gas. It has both sex. Further, as compared with the one embodiment, the crystallinity of the film obtained at the initial stage of growth increases and becomes stable, so that a film having lower resistance can be obtained. As a result of forming a film by this method, voids did not occur even in a contact hole with an aperture ratio of 0.2 μm and a depth of 1 μm and an aspect ratio of 5, and good embeddability was confirmed.
【００１８】また他の実施例の方法によって製造された
半導体装置のコンタクト抵抗（プラグ抵抗を含む）は口
径０．２μｍ，深さ１μｍのコンタクトに対しても約５
００Ωという低い値が得られた。The contact resistance (including plug resistance) of the semiconductor device manufactured by the method of the other embodiment is about 5 even for a contact having a diameter of 0.2 μm and a depth of 1 μm.
A low value of 00Ω was obtained.
【００１９】また成膜後の窒素アニールを７５０℃１時
間という条件で行なった時の膜厚（第１のシリコン膜＋
第２のシリコン膜）と比抵抗の関係を図７に示した。図
７からわかる通り一実施例に比べ更に全体的に抵抗率は
下がり、５００オングストロームの薄い膜でも６００〜
６５０μΩ・ｃｍと低い抵抗値が得られた。Further, the film thickness (first silicon film +
The relationship between the second silicon film) and the specific resistance is shown in FIG. As can be seen from FIG. 7, the overall resistivity is lower than that of one example, and even a thin film of 500 angstroms has a resistivity of 600 to 600.
A low resistance value of 650 μΩ · cm was obtained.
【００２０】[0020]
【発明の効果】以上説明した様に本発明は、所定のコン
タクトホールを有する半導体装置のコンタクトホール内
の埋め込み層に結晶性の異なる２種類の不純物を含むシ
リコン膜を用いたので、０．２μｍ径・深さ１μｍのコ
ンタクトのコンタクト抵抗が約５００Ωという低い値を
もつシリコンのプラグコンタクトを有する半導体装置が
得られるという効果を有する。As described above, according to the present invention, a silicon film containing two kinds of impurities having different crystallinities is used for a buried layer in a contact hole of a semiconductor device having a predetermined contact hole. There is an effect that a semiconductor device having a silicon plug contact having a contact resistance of a contact having a diameter and a depth of 1 μm as low as about 500Ω can be obtained.
【００２１】またこのコンタクトホールを埋め込み工程
において第１のガス系を用いて途中まで成膜した後、引
き続き第２のガス系を用いると、段差被覆性に優れ、か
つ５００オングストロームという薄膜に対し８００μΩ
・ｃｍという低い抵抗率の膜を形成できる効果もある。In addition, when the contact gas is formed halfway using the first gas system in the filling step and then the second gas system is continuously used, the step coverage is excellent and 800 μΩ for a thin film of 500 Å.
There is also an effect that a film having a low resistivity of cm can be formed.
【００２２】あるいはこの２段階の成膜のうち、第１段
階の成膜直後に熱処理を施すと、段差被覆性に優れ、か
つ５００オングストロームの薄膜に対し６００μΩ・ｃ
ｍという更に低い抵抗率の膜を形成できるという効果も
ある。Alternatively, if a heat treatment is performed immediately after the film formation in the first step of the two-step film formation, the step coverage is excellent, and 600 μΩ · c for a thin film of 500 Å.
There is also an effect that a film having a lower resistivity of m can be formed.
【図１】本発明の一実施例の半導体装置の断面図。FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.
【図２】（ａ）は本発明の一実施例の成膜条件図、
（ｂ）は本発明の一実施例の成膜条件図。FIG. 2A is a film formation condition diagram of one embodiment of the present invention,
(B) is a film-forming condition figure of one Example of this invention.
【図３】本発明の一実施例の工程別断面図（その１）FIG. 3 is a sectional view (step 1) according to steps of an embodiment of the present invention.
【図４】（ａ）は本発明の一実施例の工程別断面図（そ
の２）、（ｂ）は本発明の一実施例の工程別断面図。FIG. 4A is a sectional view of each embodiment of the present invention by step (No. 2), and FIG. 4B is a sectional view of each embodiment of the present invention by step.
【図５】本発明の一実施例の工程別断面図（その４）。FIG. 5 is a cross-sectional view (4) for each step of an embodiment of the present invention.
【図６】従来のボイドの発生したコンタクトホールの断
面図。FIG. 6 is a cross-sectional view of a conventional contact hole having a void.
【図７】本発明の実施例で成長した膜とシラン系，ジシ
ラン系のいずれか一方のみで成長した膜の比抵抗の膜厚
依存性の図。FIG. 7 is a diagram of the film thickness dependence of the specific resistance of the film grown in the example of the present invention and the film grown by only one of the silane system and the disilane system.
１１ 半導体基板 １２ 拡散層 １３ 層間膜 １４ 第１のシリコン膜 １５ 第２のシリコン膜 １６ 埋込層 １７ 配線層 ２１ コンタクトホール ２２ ボイド ２３ ジシランにより成膜されたシリコン膜 11 semiconductor substrate 12 diffusion layer 13 interlayer film 14 first silicon film 15 second silicon film 16 buried layer 17 wiring layer 21 contact hole 22 void 23 silicon film formed by disilane
Claims (3)
ンタクトホールの埋め込み層が不純物を含むシリコン膜
である半導体装置において、前記シリコン膜は結晶性の
異なる第１のシリコン膜と第２のシリコン膜の２層によ
り形成されていることを特徴とする半導体装置。1. A semiconductor device having a predetermined contact hole, wherein a buried layer of the contact hole is a silicon film containing impurities, wherein the silicon film has a first crystal film and a second silicon film having different crystallinity. A semiconductor device comprising two layers of
装置に、不純物を有するシリコン膜を成長して前記コン
タクトホールを埋め込む工程において、第１のガス系を
用いて不純物を有する第１のシリコン膜を成長した後、
第２のガス系を用いて不純物を含む第２のシリコン膜を
成長し前記コンタクトホールを埋め込むことを特徴とす
る半導体装置の製造方法。2. In a step of growing a silicon film having impurities in a semiconductor device having a predetermined contact hole and filling the contact hole, a first silicon film having impurities is grown using a first gas system. After doing
A method of manufacturing a semiconductor device, wherein a second silicon film containing an impurity is grown using a second gas system and the contact hole is filled.
第１のガス系を用いて不純物を含む前記第１のシリコン
膜を成長する工程と、第２のガス系を用いて不純物を含
む前記第２のシリコン膜を成長する工程の間に熱処理工
程が含まれることを特徴とする請求項２記載の半導体装
置の製造方法。3. The step of filling the contact hole comprises growing the first silicon film containing impurities using a first gas system, and the second step containing impurities using a second gas system. The method for manufacturing a semiconductor device according to claim 2, wherein a heat treatment step is included between the steps of growing the silicon film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12481592A JP2836371B2 (en) | 1992-05-18 | 1992-05-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12481592A JP2836371B2 (en) | 1992-05-18 | 1992-05-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0685081A true JPH0685081A (en) | 1994-03-25 |
| JP2836371B2 JP2836371B2 (en) | 1998-12-14 |
Family
ID=14894804
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12481592A Expired - Fee Related JP2836371B2 (en) | 1992-05-18 | 1992-05-18 | Method for manufacturing semiconductor device |
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| Country | Link |
|---|---|
| JP (1) | JP2836371B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012004542A (en) * | 2010-05-20 | 2012-01-05 | Tokyo Electron Ltd | Method and apparatus for forming silicon film |
| JP2013033933A (en) * | 2011-06-30 | 2013-02-14 | Tokyo Electron Ltd | Method and apparatus for forming silicon film |
| JP2013239717A (en) * | 2010-05-20 | 2013-11-28 | Tokyo Electron Ltd | Method for forming silicon film and apparatus for forming silicon film |
| US9384974B2 (en) | 2013-05-27 | 2016-07-05 | Tokyo Electron Limited | Trench filling method and processing apparatus |
-
1992
- 1992-05-18 JP JP12481592A patent/JP2836371B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012004542A (en) * | 2010-05-20 | 2012-01-05 | Tokyo Electron Ltd | Method and apparatus for forming silicon film |
| JP2013239717A (en) * | 2010-05-20 | 2013-11-28 | Tokyo Electron Ltd | Method for forming silicon film and apparatus for forming silicon film |
| KR101477159B1 (en) * | 2010-05-20 | 2014-12-29 | 도쿄엘렉트론가부시키가이샤 | Silicon film formation method and silicon film formation apparatus |
| JP2015092630A (en) * | 2010-05-20 | 2015-05-14 | 東京エレクトロン株式会社 | Method and apparatus for forming silicon film |
| JP2013033933A (en) * | 2011-06-30 | 2013-02-14 | Tokyo Electron Ltd | Method and apparatus for forming silicon film |
| TWI648771B (en) * | 2011-06-30 | 2019-01-21 | 東京威力科創股份有限公司 | Method and device for forming enamel film |
| US9384974B2 (en) | 2013-05-27 | 2016-07-05 | Tokyo Electron Limited | Trench filling method and processing apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2836371B2 (en) | 1998-12-14 |
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