JPH0682891B2 - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPH0682891B2 JPH0682891B2 JP62002686A JP268687A JPH0682891B2 JP H0682891 B2 JPH0682891 B2 JP H0682891B2 JP 62002686 A JP62002686 A JP 62002686A JP 268687 A JP268687 A JP 268687A JP H0682891 B2 JPH0682891 B2 JP H0682891B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- conductor layer
- ground side
- analog
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Structure Of Printed Boards (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明は電子機器の回路構成に係り、回路基板の表面と
裏面にアナログ回路とディジタル回路とを別けて実装、
回路構成させ、アナログ回路の高周波の接地側回路とデ
ィジタル回路の接地側回路とを絶縁させ、更に遮蔽接地
用に中間導体層を設けて回路間の影響を遮断するように
した、両面実装の混成集積回路であり、回路基板の小形
化、高密度実装化が図れ、部品の絶縁取り付けも不要と
したものである。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to a circuit configuration of an electronic device, in which an analog circuit and a digital circuit are separately mounted on a front surface and a back surface of a circuit board,
The circuit is configured so that the high frequency ground side circuit of the analog circuit and the ground side circuit of the digital circuit are insulated, and an intermediate conductor layer is further provided for shield grounding to cut off the influence between the circuits. Since it is an integrated circuit, the circuit board can be miniaturized, high-density mounting can be achieved, and insulation mounting of components is not required.
本発明は電子機器の回路構成に係り、多層回路基板の表
裏面に回路を夫々別にし、間に遮蔽導体層を設けて、ア
ナログ回路とディジタル回路を混在実装させた混成集積
回路に関す。The present invention relates to a circuit configuration of an electronic device, and relates to a hybrid integrated circuit in which circuits are separately provided on the front and back surfaces of a multilayer circuit board, a shield conductor layer is provided between them, and an analog circuit and a digital circuit are mixedly mounted.
近年、ディジタル回路の開発が進み、従来アナログ回路
で構成された回路が、小形，経済的な論理集積回路の出
現によりディジタル化されて、部分的に置換されるケー
スが多くなって来た。In recent years, the development of digital circuits has progressed, and with the advent of small-sized and economical logic integrated circuits, the number of cases in which circuits conventionally composed of analog circuits have been digitized and partially replaced have increased.
例えば、アナログの変調回路は搬送波を伴うが、この発
生をディジタルのタイミング回路と分周，倍周回路を組
合せた簡単な論理集積回路で行う等である。For example, an analog modulation circuit accompanies a carrier wave, but this generation is performed by a simple logic integrated circuit in which a digital timing circuit and a frequency dividing / frequency multiplying circuit are combined.
従って、アナログ伝送装置であっても回路構成は相当デ
ィジタル化されたものとなって来ており、同一回路基板
にアナログ回路とディジタル回路を混在実装するケース
が、小形高密度実装化のために強く要求されている。Therefore, even in analog transmission equipment, the circuit configuration has become considerably digitalized, and the case where analog circuits and digital circuits are mixedly mounted on the same circuit board is strongly recommended for compact and high-density mounting. Is required.
第４図に従来の一例の実装斜視断面図を示す。回路実装
は、プリント配線板を回路基板として片面或いは両面に
部品を取り付け接続を行う、プリント板実装方式が一般
的であり、基板材の開発、高密度配線化および多層回路
構造の開発が強力に推進されている。FIG. 4 shows a perspective sectional view of a mounting example of a conventional example. For circuit mounting, a printed circuit board mounting method is generally used in which parts are attached and connected to one or both sides using a printed wiring board as a circuit board, and development of board materials, high-density wiring, and development of multi-layer circuit structures are strongly promoted. It is being promoted.
周波数分割のアナログ回路信号は、多周波数で構成さ
れ、夫々の周波数成分が時々刻々元信号に応じて連続的
に変化しており、これを忠実に伝送する必要がある。The frequency-divided analog circuit signal is composed of multiple frequencies, and each frequency component continuously changes according to the original signal every moment, and it is necessary to faithfully transmit this.
一方時分割のディジタル回路の信号は、時間的等間隔な
位置にパルス信号の有無のみを判別し、所定間隔内の配
列を解読するもので、アナログ伝送のように周波数成分
は殆ど問題とならない。On the other hand, the signal of the time-division digital circuit determines only the presence or absence of pulse signals at positions at equal time intervals, and decodes the arrangement within a predetermined interval, and the frequency component does not pose a problem as in analog transmission.
従って、アナログ回路には他の信号の周波数成分の混入
を極めて低く抑える必要があり、また、取扱周波数が高
くなるに従い、その影響は受け易くなり、接地や遮蔽は
益々厳重となる。Therefore, it is necessary to suppress the mixing of the frequency components of other signals in the analog circuit to an extremely low level, and as the handling frequency becomes higher, the influence becomes more susceptible and grounding and shielding become more and more severe.
アナログ回路とディジタル回路を同一回路基板に混在実
装した、従来の一例の回路実装は第４図に示す如く、表
裏二面の導体層81,82を有する回路基板８の両面に、夫
々表面接続型の部品４を実装し、両面回路間をスルーホ
ール72により貫通接続して回路構成させたもので、アナ
ログ回路１とディジタル回路２とは、配線結合による悪
影響を防止するために回路基板８上の区域を区分して実
装し、接地側回路88を除き、回路配線も互いの区域に入
り混まないように行っている。As shown in FIG. 4, a conventional example of circuit mounting in which analog circuits and digital circuits are mixedly mounted on the same circuit board is, as shown in FIG. 4, on both surfaces of a circuit board 8 having conductor layers 81 and 82 on the front and back sides, respectively, a surface connection type. The components 4 are mounted and the double-sided circuits are through-connected through the through holes 72 to form a circuit. The analog circuit 1 and the digital circuit 2 are arranged on the circuit board 8 in order to prevent adverse effects due to wiring coupling. The areas are separately mounted, and the circuit wirings are arranged so as not to mix with each other except the ground side circuit 88.
接地側回路88は、抵抗を少なくするため特に高周波回路
では、出来るだけ回路配線以外の空き面積を接地側回路
88としている。In order to reduce the resistance, the ground side circuit 88, especially in a high frequency circuit, fills the open area other than the circuit wiring as much as possible with the ground side circuit.
88.
しかしながら、ディジタル回路２はアナログ回路１に比
べ信号レベルが高く、且つパルスのため高周波成分が多
く、 （１）接地側回路88が共通なため、ディジタル回路２の
帰路による影響が、アナログ回路１への特性不良や特性
劣化等の発生を来す。However, the digital circuit 2 has a higher signal level than the analog circuit 1 and has many high frequency components due to pulses. (1) Since the ground side circuit 88 is common, the analog circuit 1 is affected by the return path of the digital circuit 2. This causes the occurrence of defective characteristics and deterioration of characteristics.
（２）この影響除去には、アナログ回路１の一部分の高
周波接地側回路を、回路基板８の共通接地側回路88から
直流的に絶縁する必要がある。(2) To remove this influence, it is necessary to galvanically isolate a part of the high frequency ground side circuit of the analog circuit 1 from the common ground side circuit 88 of the circuit board 8.
（３）このため、遮蔽ケースに格納されたアナログ回路
部品はケースごと絶縁するために、回路基板８の共通接
地側回路88に対し絶縁シートや絶縁ブッシュ等による絶
縁取り付けが行われ、工数増や、絶縁不良による再特性
劣化を発生する。等の問題点がある。(3) Therefore, in order to insulate the analog circuit parts stored in the shielding case together with the case, the common ground side circuit 88 of the circuit board 8 is insulatedly attached by an insulating sheet or an insulating bushing, which increases the number of steps. , Re-characteristic deterioration due to poor insulation occurs. There are problems such as.
本発明は、上記の問題の解決を目的とし、表裏面でアナ
ログ回路とディジタル回路を分離実装し、間に遮蔽接地
導体層を設けた多層構造の回路基板を用いる新しい混成
集積回路を提案するものである。The present invention aims to solve the above problems, and proposes a new hybrid integrated circuit using a multilayer circuit board in which an analog circuit and a digital circuit are separately mounted on the front and back surfaces and a shield ground conductor layer is provided between them. Is.
第１図の本発明の原理図に示す如く、 （１）アナログ回路とディジタル回路とを同一回路基板
に構成する混成集積回路であって、表裏面の導体層51,5
2と、内部に２個の略外形全面にわたる中間導体層53,54
とを夫々絶縁して設けた回路基板５と、高周波の接地側
回路11が表面に近い第一中間導体層53に接続され、回路
電源の接地側がこの中間導体層53には接続されず絶縁し
て浮かせ、表面導体層51に構成されるアナログ回路１
と、回路の接地側回路21と回路電源の接地側とが共に第
二中間導体層54に接続され、裏面導体層52に構成される
ディジタル回路２と、から構成し、中間導体層53,54間
の絶縁層55により生じる容量を選択設定して、低周波に
おける回路間相互影響を選択的に抑制してなる。As shown in the principle diagram of the present invention in FIG. 1, (1) a hybrid integrated circuit in which an analog circuit and a digital circuit are formed on the same circuit board, and conductor layers 51, 5 on the front and back surfaces are provided.
2 and two intermediate conductor layers 53, 54 over the entire outer surface
And the high-frequency ground side circuit 11 are connected to the first intermediate conductor layer 53 close to the surface, and the ground side of the circuit power source is not connected to the intermediate conductor layer 53 and is insulated. Analog circuit 1 that is floated and formed on the surface conductor layer 51
And the digital circuit 2 in which the ground side circuit 21 of the circuit and the ground side of the circuit power source are both connected to the second intermediate conductor layer 54 and are formed in the back conductor layer 52. The intermediate conductor layers 53, 54 By selectively setting the capacitance generated by the insulating layer 55 between them, mutual influence between circuits at low frequencies is selectively suppressed.
（２）表裏面の導体層61,62と、内部に１個の略外形全
面にわたる中間導体層63とを夫々絶縁して設けた回路基
板６と、高周波の接地側回路11が中間導体層63に接続さ
れ、回路電源の接地側が中間導体層63には接続されず絶
縁して浮かせ、表面導体層61に構成されるアナログ回路
１と、回路の接地側回路21と回路電源の接地側とが共に
裏面導体層62に設けた接地パターンに接続され、裏面導
体層62に構成されるディジタル回路２と、から構成し、
中間導体層63と裏面導体層62との間の絶縁層64により生
じる容量を選択設定して、低周波における回路間相互影
響を選択的に抑圧してなる。(2) The circuit board 6 in which the conductor layers 61, 62 on the front and back surfaces are insulated from each other and the intermediate conductor layer 63 that covers the entire outer surface of the inside, and the high-frequency grounding side circuit 11 includes the intermediate conductor layer 63. , The ground side of the circuit power supply is not connected to the intermediate conductor layer 63 and is insulated and floated, and the analog circuit 1 configured on the surface conductor layer 61, the ground side circuit 21 of the circuit, and the ground side of the circuit power supply are connected to each other. And a digital circuit 2 which is connected to the ground pattern provided on the back surface conductor layer 62 and is formed on the back surface conductor layer 62.
The capacitance generated by the insulating layer 64 between the intermediate conductor layer 63 and the back conductor layer 62 is selectively set to selectively suppress the mutual influence between circuits at low frequencies.
ことを備えた、本発明の混成集積回路により解決され
る。And a hybrid integrated circuit of the present invention.
即ち、ディジタル回路の帰路がアナログ回路の高周波帰
路の接地側回路を通らず、且つ両配線回路間に同面積の
遮蔽層を設けるので、両回路間の影響の発生を防止する
ことになり、目的が達成される。That is, since the return path of the digital circuit does not pass through the ground side circuit of the high frequency return path of the analog circuit, and the shielding layer having the same area is provided between both wiring circuits, the influence between the two circuits is prevented from occurring. Is achieved.
これを図示すれば、第１図の原理図のように、アナログ
回路１は遮蔽体３で回路全体を遮蔽して、高周波帰路も
この遮蔽体３に接続して高周波接地側回路11の抵抗を下
げるようにし、更にこの遮蔽体３は、一端が接地された
供給電源B1から直流的に浮かしてある。If this is illustrated, as shown in the principle diagram of FIG. 1, the analog circuit 1 shields the entire circuit with a shield 3, and the high frequency return path is also connected to this shield 3 to reduce the resistance of the high frequency ground side circuit 11. In addition, the shield 3 is DC-floated from the power supply B1 whose one end is grounded.
ディジタル回路２は一端が接地された供給電源B2に直結
し、帰路の接地側回路21は接地してある。The digital circuit 2 is directly connected to the supply power source B2 whose one end is grounded, and the return side ground side circuit 21 is grounded.
これにより、ディジタル回路２の帰路の接地側回路21
は、アナログ回路１の接地側回路11には流入せず、電磁
誘導は遮蔽体３により防がれ、アナログ回路１はディジ
タル回路２の影響を遮断することが出来る。As a result, the return side ground side circuit 21 of the digital circuit 2
Does not flow into the ground side circuit 11 of the analog circuit 1, electromagnetic induction is prevented by the shield 3, and the analog circuit 1 can block the influence of the digital circuit 2.
また、アナログ回路１の接地は、絶縁体により直流的に
浮かせた遮蔽体３が、高周波的には抵抗が無視される容
量Ｃによってなされている。Further, the grounding of the analog circuit 1 is performed by the shield 3 floated in a direct current by an insulator by a capacitance C whose resistance is ignored in the high frequency.
更に、この容量Ｃを適切に設定することにより、ディジ
タル回路２からの低周波の誘導を抑圧することが出来
る。Furthermore, by setting the capacitance C appropriately, low frequency induction from the digital circuit 2 can be suppressed.
このことを回路基板について行えば、表面導体層と裏面
導体層とに別けて、アナログ回路１とディジタル回路２
との実装を行い、中間導体層を二層設け、第一層はアナ
ログ回路１の遮蔽体３として用い、第二層をディジタル
回路２の接地として用い、第一層と第二層との絶縁層で
主の容量Ｃを構成させた両面実装の混成集積回路とな
る。If this is done for the circuit board, the analog circuit 1 and the digital circuit 2 are separated into the front surface conductor layer and the back surface conductor layer.
And two intermediate conductor layers are provided, the first layer is used as the shield 3 of the analog circuit 1, the second layer is used as the ground of the digital circuit 2, and the insulation between the first layer and the second layer is performed. This is a double-sided mounting hybrid integrated circuit in which the main capacitance C is constituted by layers.
また、中間導体層を一層とし、アナログ回路１の遮蔽体
３として用い、ディジタル回路２の面との絶縁層が主の
容量Ｃとさせたものでも同様の効果を得ることが出来
る。Also, the same effect can be obtained by using a single intermediate conductor layer as the shield 3 of the analog circuit 1 and using the main capacitor C as the insulating layer for the surface of the digital circuit 2.
これにより、アナログ回路とディジタル回路を特性的に
影響無く混在実装させ、回路基板の小形化、高密度実装
化が図れ、部品の絶縁取り付けも必要とすることが出来
る。As a result, the analog circuit and the digital circuit can be mixedly mounted without affecting the characteristics, the circuit board can be downsized and the density can be increased, and the insulating mounting of the parts can be required.
以下図面に示す実施例によって本発明を具体的に説明す
る。The present invention will be specifically described below with reference to the embodiments shown in the drawings.
全図を通し同一符合は同一対称物を示す。Throughout the drawings, the same reference numerals indicate the same symmetrical objects.
第２図に本発明の第一実施例の断面図、第３図に本発明
の第二実施例の断面図を示す。FIG. 2 shows a sectional view of the first embodiment of the present invention, and FIG. 3 shows a sectional view of the second embodiment of the present invention.
第一実施例は、セラミック板の片面を遮蔽導体層とし、
他面に回路パターンを設けた印刷配線板の２個を、回路
パターン面を外側にして間隔を設定して接着した四層構
造の回路基板５を用いて、アナログ回路１とディジタル
回路２を混在実装させたものである。In the first embodiment, one side of the ceramic plate is a shield conductor layer,
An analog circuit 1 and a digital circuit 2 are mixed by using a circuit board 5 having a four-layer structure in which two printed wiring boards each having a circuit pattern on the other surface are adhered with the circuit pattern surface as an outer side at a set interval. It was implemented.
第２図に示す如く、回路基板５の表面導体層51の表面接
続型の部品４を実装してアナログ回路１のみを構成させ
る。この時、高周波の接地側回路11は接地抵抗を逓減さ
せるために、回路パターンを除き特性の劣化を来さない
範囲の導体を凡て接地側回路11とし、電源供給回路は接
地側極もこの接地側回路11から絶縁して設けてある。As shown in FIG. 2, the surface connection type component 4 of the surface conductor layer 51 of the circuit board 5 is mounted to configure only the analog circuit 1. At this time, in order to gradually reduce the ground resistance of the high frequency ground side circuit 11, all conductors within the range not causing the deterioration of the characteristics except the circuit pattern are the ground side circuit 11, and the power supply circuit also has the ground side pole. It is provided so as to be insulated from the ground side circuit 11.
回路基板５の裏面導体層52には、同様に表面実装してデ
ィジタル回路２を構成している。しかし、ディジタル回
路２では接地側回路21と電源供給回路の接地側極とは絶
縁することは不可能であり、同一となっている。Similarly, the back surface conductor layer 52 of the circuit board 5 is surface-mounted to form the digital circuit 2. However, in the digital circuit 2, it is impossible to insulate the ground side circuit 21 from the ground side pole of the power supply circuit, and they are the same.
二層の中間導体層53,54は、何れも周辺部を除き全面を
導体とした遮蔽体で、表面に近い第一中間導体層53はア
ナログ回路１の接地側回路11と中間接続のスルーホール
71により接続してあり、第二中間導体層54は同様にディ
ジタル回路２の接地側回路21と接続してある。Each of the two intermediate conductor layers 53, 54 is a shield having the entire surface as a conductor except the peripheral portion, and the first intermediate conductor layer 53 near the surface is a through hole for intermediate connection with the ground side circuit 11 of the analog circuit 1.
The second intermediate conductor layer 54 is similarly connected to the ground side circuit 21 of the digital circuit 2.
勿論、アナログ回路１とディジタル回路２とを回路接続
する配線は、全層を貫通させたスルーホール72により行
うが、第一中間導体層53ではこれら配線とは接続せず絶
縁しておく。Of course, the wiring for connecting the analog circuit 1 and the digital circuit 2 is formed by the through hole 72 penetrating all the layers, but the first intermediate conductor layer 53 is insulated without being connected to these wirings.
また、電源供給回路が共通の場合も、前記と同様にスル
ーホール72により接続し、ディジタル回路２側からアナ
ログ回路１に供給する。Further, even when the power supply circuit is common, the connection is made through the through hole 72 in the same manner as described above, and the analog circuit 1 is supplied from the digital circuit 2 side.
第二実施例は、セラミック板の片面を遮蔽導体層とし、
他面に回路パターンを設けた印刷配線板と、同遮蔽導体
層の無いものとを、回路パターン面を外側にして間隔を
設定して接着した三層構造の回路基板６を用いて、アナ
ログ回路１とディジタル回路２を混在実装させたもので
ある。In the second embodiment, one surface of the ceramic plate is a shield conductor layer,
An analog circuit is formed by using a circuit board 6 having a three-layer structure in which a printed wiring board provided with a circuit pattern on the other surface and one without the same shield conductor layer are bonded with the circuit pattern surface facing outward at a certain interval. 1 and the digital circuit 2 are mixedly mounted.
第３図に示す如く、第一実施例と同様に、回路基板６の
表面導体層61と裏面導体層62とに別けて、アナログ回路
１とディジタル回路２を構成させ、中間導体層63を全面
遮蔽体とし、アナログ回路１の高周波の接地側回路11と
中間接続のスルーホール71により接続してある。As shown in FIG. 3, as in the first embodiment, the front surface conductor layer 61 and the back surface conductor layer 62 of the circuit board 6 are divided into the analog circuit 1 and the digital circuit 2, and the intermediate conductor layer 63 is entirely covered. As a shield, it is connected to the high frequency ground side circuit 11 of the analog circuit 1 through a through hole 71 for intermediate connection.
更に、アナログ回路１とディジタル回路２との回路接続
や電源供給接続も前記と同じに行う。Further, the circuit connection and power supply connection between the analog circuit 1 and the digital circuit 2 are made in the same manner as described above.
かくして、アナログ回路１とディジタル回路２とは中間
導体層53,54,63により全面が遮蔽され、アナログ回路１
の高周波の接地側回路11は直流的に接地されず、ディジ
タル回路２の接地側回路21とは切り離され、ディジタル
回路２からアナログ回路１への電流による影響を遮断
し、更に、第一実施例では両中間導体層53,54間の絶縁
層55、第二実施例では中間導体層63と裏面導体層62間の
絶縁層64の容量により高周波的には接地され、この絶縁
層55,64の厚みを選択設定することにより、ディジタル
回路２からの低周波の影響も選択的に抑圧することが出
来、高周波の電磁誘導は中間導体層53,54,63の遮蔽効果
により防止出来る。Thus, the entire surfaces of the analog circuit 1 and the digital circuit 2 are shielded by the intermediate conductor layers 53, 54, 63, and the analog circuit 1
The high frequency ground side circuit 11 is not grounded in a DC manner and is separated from the ground side circuit 21 of the digital circuit 2 to cut off the influence of the current from the digital circuit 2 to the analog circuit 1. In the second embodiment, the insulation layer 55 between the intermediate conductor layers 53 and 54 is grounded in the high frequency by the capacitance of the insulation layer 64 between the intermediate conductor layer 63 and the back conductor layer 62. By selectively setting the thickness, the influence of low frequency from the digital circuit 2 can be selectively suppressed, and high frequency electromagnetic induction can be prevented by the shielding effect of the intermediate conductor layers 53, 54 and 63.
以上により、回路基板の両面にアナログ回路とディジタ
ル回路を混在実装した混成集積回路が完成されるが、回
路基板の材料、寸法、製造方法は問わない。As described above, the hybrid integrated circuit in which the analog circuit and the digital circuit are mixedly mounted on both surfaces of the circuit board is completed, but the material, size, and manufacturing method of the circuit board are not limited.
以上の如く、アナログ回路とディジタル回路を特性的に
影響悪く混在させた混成集積回路が得られ、回路基板の
小形化、高密度実装化が図れ、部品の絶縁取り付けも不
要とした効果は大なるものがある。As described above, it is possible to obtain a hybrid integrated circuit in which analog circuits and digital circuits are mixed in a characteristically unfavorable manner, a circuit board can be downsized, high-density mounting can be achieved, and the effect of eliminating the need for insulating mounting of parts is great. There is something.
第１図は本発明の原理図、 第２図は本発明の第一実施例の断面図、 第３図は本発明の第二実施例の断面図、 第４図は従来の一例の斜視断面図である。 図において、 １はアナログ回路、２はディジタル回路、 ３は遮蔽体、４は部品、 5,6,8は回路基板、11,21,88は接地側回路、 51,61,81は表面導体層、 52,62,82は裏面導体層、 53は第一中間導体層、54は第二中間導体層、 63は中間導体層、55,64は絶縁層、 71,72はスルーホールである。 1 is a principle view of the present invention, FIG. 2 is a sectional view of a first embodiment of the present invention, FIG. 3 is a sectional view of a second embodiment of the present invention, and FIG. 4 is a perspective sectional view of a conventional example. It is a figure. In the figure, 1 is an analog circuit, 2 is a digital circuit, 3 is a shield, 4 is a component, 5,6,8 are circuit boards, 11,21,88 are ground side circuits, 51,61,81 are surface conductor layers. , 52, 62 and 82 are back surface conductor layers, 53 is a first intermediate conductor layer, 54 is a second intermediate conductor layer, 63 is an intermediate conductor layer, 55 and 64 are insulating layers, and 71 and 72 are through holes.
Claims (2)
路基板に構成する混成集積回路であって、 表裏面の導体層（51,52）と、内部に２個の略外形全面
にわたる中間導体層（53,54）とを夫々絶縁して設けた
回路基板（５）と、 高周波の接地側回路（11）が表面に近い第一中間導体層
（53）に接続され、回路電源の接地側が該第一中間導体
層（53）には接続されず絶縁して浮かせ、表面導体層
（51）に構成されるアナログ回路（１）と、 回路の接地側回路（21）と回路電源の接地側とが共に第
二中間導体層（54）に接続され、裏面導体層（52）に構
成されるディジタル回路（２）と、から構成し、 該中間導体層（53,54）間の絶縁層（55）により生じる
容量を選択設定して、低周波における回路間相互影響を
選択的に抑圧してなることを特徴とする混成集積回路。1. A hybrid integrated circuit in which an analog circuit and a digital circuit are formed on the same circuit board, wherein conductor layers (51, 52) are provided on the front and back surfaces, and two intermediate conductor layers covering substantially the entire outer surface inside. 53, 54) are respectively insulated from each other, and a high frequency ground side circuit (11) is connected to the first intermediate conductor layer (53) close to the surface, and the ground side of the circuit power source is (1) The analog circuit (1) that is not connected to the intermediate conductor layer (53) and is insulated and floated to form the surface conductor layer (51), the ground side of the circuit (21), and the ground side of the circuit power supply An insulating layer (55) between the intermediate conductor layers (53, 54), the digital circuit (2) being connected to the second intermediate conductor layer (54) and being formed on the back conductor layer (52). This is characterized by selectively setting the capacitance caused by the above, and selectively suppressing the mutual influence between circuits at low frequencies. Integrated circuit.
路基板に構成する混成集積回路であって、 表裏面の導体層（61,62）と、内部に１個の略外形全面
にわたる中間導体層（63）とを夫々絶縁して設けた回路
基板（６）と、 高周波の接地側回路（11）が該中間導体層（63）に接続
され、回路電源の接地側が該中間導体層（63）には接続
されず絶縁して浮かせ、表面導体層（61）に構成される
アナログ回路（１）と、 回路の接地側回路（21）と回路電源の接地側とが共に裏
面導体層（62）に設けた接地パターンに接続され、該裏
面導体層（62）に構成されるディジタル回路（２）と、
から構成し、 該中間導体層（63）と該裏面導体層（62）との間の絶縁
層（64）により生じる容量を選択設定して、低周波にお
ける回路間相互影響を選択的に抑圧してなることを特徴
とする混成集積回路。2. A hybrid integrated circuit in which an analog circuit and a digital circuit are formed on the same circuit board, wherein conductor layers (61, 62) on the front and back surfaces and an intermediate conductor layer (a single inner conductor layer covering substantially the entire outer surface) are provided. A circuit board (6) which is insulated from each other and a high frequency ground side circuit (11) are connected to the intermediate conductor layer (63), and the ground side of the circuit power source is connected to the intermediate conductor layer (63). Are not connected to each other and are insulated and floated, and the analog circuit (1) configured on the front surface conductor layer (61) and the ground side circuit (21) of the circuit and the ground side of the circuit power supply are both on the back surface conductor layer (62). A digital circuit (2) connected to the ground pattern provided and configured on the back conductor layer (62);
And selectively setting the capacitance generated by the insulating layer (64) between the intermediate conductor layer (63) and the back conductor layer (62) to selectively suppress the mutual influence between circuits at low frequencies. A hybrid integrated circuit characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002686A JPH0682891B2 (en) | 1987-01-09 | 1987-01-09 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62002686A JPH0682891B2 (en) | 1987-01-09 | 1987-01-09 | Hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63170988A JPS63170988A (en) | 1988-07-14 |
| JPH0682891B2 true JPH0682891B2 (en) | 1994-10-19 |
Family
ID=11536171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62002686A Expired - Fee Related JPH0682891B2 (en) | 1987-01-09 | 1987-01-09 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0682891B2 (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH085581Y2 (en) * | 1990-11-27 | 1996-02-14 | 株式会社ピーエフユー | Multilayer printed wiring board |
| JP3166611B2 (en) * | 1996-04-19 | 2001-05-14 | 富士ゼロックス株式会社 | Printed wiring board and method of manufacturing the same |
| JP4372407B2 (en) * | 2002-11-12 | 2009-11-25 | イビデン株式会社 | Multilayer printed wiring board |
| JP2006319512A (en) * | 2005-05-11 | 2006-11-24 | Murata Mfg Co Ltd | Multilayer wiring board device |
| WO2009119077A1 (en) * | 2008-03-24 | 2009-10-01 | パナソニック株式会社 | Electronic circuit board and power line communication device using the same |
| JP5355940B2 (en) * | 2008-06-10 | 2013-11-27 | 株式会社東芝 | Radiation detector |
| JP6674824B2 (en) * | 2016-04-05 | 2020-04-01 | 株式会社ユーシン | Multilayer substrate circuit module, wireless communication device and radar device |
| WO2023074251A1 (en) * | 2021-10-28 | 2023-05-04 | 株式会社村田製作所 | Tracker module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0646516B2 (en) * | 1983-09-30 | 1994-06-15 | 富士通株式会社 | Decoder circuit using the Josephson device |
-
1987
- 1987-01-09 JP JP62002686A patent/JPH0682891B2/en not_active Expired - Fee Related
Non-Patent Citations (1)
| Title |
|---|
| 実願昭５８−１６７７７９号（実開昭６０−７６０９１）の願書に添付した明細書及び図面の内容を撮影したマイクロフィルム |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63170988A (en) | 1988-07-14 |
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| LAPS | Cancellation because of no payment of annual fees |