JPH0669754A - Variable attenuator - Google Patents
Variable attenuatorInfo
- Publication number
- JPH0669754A JPH0669754A JP22238392A JP22238392A JPH0669754A JP H0669754 A JPH0669754 A JP H0669754A JP 22238392 A JP22238392 A JP 22238392A JP 22238392 A JP22238392 A JP 22238392A JP H0669754 A JPH0669754 A JP H0669754A
- Authority
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- Prior art keywords
- fet
- gate
- variable attenuator
- voltage
- drain
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は可変減衰器に関し、特に
マイクロ波帯以上のモノリシック集積回路に電界効果ト
ランジスタを組み込んで使用される可変減衰器に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable attenuator, and more particularly to a variable attenuator used by incorporating a field effect transistor in a monolithic integrated circuit in the microwave band or higher.
【０００２】[0002]
【従来の技術】通常、マイクロ波回路を用いて構成され
る通信システムでは、回線構成上のレベルダイヤ調整又
は温度特性によるシステム内の信号レベル変動を吸収し
て安定化出力を得ることを目的として、多くの可変減衰
器をマイクロ波回路に使用している。このような可変減
衰器は接続される前後の機器又は素子とのインピーダン
ス整合をとり、減衰量が変化しても接続インピーダンス
が変化しない定抵抗形可変減衰器を用いることが多い。
そして可変抵抗素子としては一般的にはＰＩＮダイオー
ドがよく知られている。2. Description of the Related Art Usually, in a communication system constructed by using a microwave circuit, it is aimed at obtaining a stabilized output by absorbing a signal level fluctuation in the system due to a level diagram adjustment or a temperature characteristic on a line configuration. , Many variable attenuators are used in microwave circuits. Such a variable attenuator is often a constant resistance type variable attenuator that performs impedance matching with a device or an element before and after being connected and whose connection impedance does not change even if the attenuation amount changes.
A PIN diode is generally well known as the variable resistance element.
【０００３】近年、半導体基板上に多くの回路素子を集
積化して高周波回路を構成するモノリシック集積回路の
開発が盛んであり、マイクロ波帯以上で動作する集積回
路に適したガリウムひ素等を半導体基板上に構成する場
合も数多くある。In recent years, a monolithic integrated circuit for integrating a large number of circuit elements on a semiconductor substrate to form a high frequency circuit has been actively developed, and gallium arsenide or the like suitable for an integrated circuit operating in a microwave band or higher is used as a semiconductor substrate. There are many cases of configuring the above.
【０００４】従来、この種の集積回路に使用される可変
減衰器も装置の小形化、コストダウンのため、ガリウム
ひ素等の半導体基板上に構成したモノリシック集積回路
の可変減衰器も実現されつつある。この回路構成は図４
に示すようにブリッジＴ型回路である。すなわち、マイ
クロ波信号の入力１，出力２にそれぞれドレイン，ソー
スを接続し、ゲートを制御端子８に接続する電界効果ト
ランジスタ（ＦＥＴ）３と、ＦＥＴ３のドレインとソー
スにそれぞれ一端を接続し、他端を共通接続する抵抗
５，６と、この共通接続点にドレインを接続し、ソース
を接地し、ゲートを制御端子７に接続する電界効果トラ
ンジスタ（ＦＥＴ）４とにより、ブリッジドＴ型可変減
衰器を構成している。減衰量は制御端子７，８のバイア
ス電圧を変えて減衰量を可変としている。前述のように
この可変減衰器は定抵抗型可変減衰器なので、ＦＥＴ３
及び４のチャンネル抵抗Ｒ1 ，Ｒ2 とし、回路の特性イ
ンピーダンスをＺ0 （抵抗５，６の抵抗値）とすると、 Ｚ0 2 ＝Ｒ1 −Ｒ2 となるようにＦＥＴ３及び４のゲート電圧を制御してい
る。Conventionally, the variable attenuator used in this kind of integrated circuit is also being realized in order to downsize the device and reduce the cost, so that a variable attenuator of a monolithic integrated circuit formed on a semiconductor substrate such as gallium arsenide is being realized. . This circuit configuration is shown in FIG.
It is a bridge T-type circuit as shown in FIG. That is, a field effect transistor (FET) 3 in which a drain and a source are connected to a microwave signal input 1 and an output 2, respectively, and a gate is connected to a control terminal 8, and one end is connected to the drain and the source of the FET 3 respectively, A bridged T-type variable attenuator comprising resistors 5 and 6 having ends commonly connected and a field effect transistor (FET) 4 having a drain connected to the common connection point, a source grounded, and a gate connected to a control terminal 7. Are configured. The amount of attenuation is made variable by changing the bias voltage of the control terminals 7 and 8. As mentioned above, since this variable attenuator is a constant resistance type variable attenuator, FET3
And the channel resistances R 1 and R 2 of 4 and the characteristic impedance of the circuit is Z 0 (resistance values of the resistors 5 and 6), the gate voltage of the FETs 3 and 4 is Z 0 2 = R 1 -R 2. Are in control.
【０００５】一方、この従来のブリッジＴ型可変減衰器
は、ＦＥＴの非飽和領域でのドレイン・ソース間抵抗値
がゲート電圧により変化することを利用しているので、
高周波入力信号の電圧振幅がＦＥＴの非飽和領域内であ
れば歪特性の劣化は小さいが、ゲート電位を下げていく
とＦＥＴの非飽和領域が減少するために、歪特性が著し
く劣化する。ゲート電圧一定下で入力信号電力を増して
いった場合も、入力信号の電圧振幅がＦＥＴの飽和領域
に近づくに従い、歪特性が劣化していく。図５に、従来
のブリッジＴ型可変減衰器のゲート・ソース間電圧を変
化させた時の３次混変調歪特性のＤ／Ｕ比の実測値と減
衰量を示す。図５においてＶｇｓ1 ＝−０．１ｖ及び−
０．９ｖ付近でＤ／Ｕ比の劣化する極大点が存在する。
これら２点の極大点のうちＶｇｓ1 ＝−０．１ｖ付近で
は、ＦＥＴ４の歪が支配的であり、Ｖｇｓ1 ＝−０．９
ｖ付近ではＦＥＴ３の歪が支配的となる。可変減衰器で
は減衰量０ｄＢから数ｄＢまでの間で歪の少ない特性を
要求されるので、Ｖｇｓ1＝−０．１ｖ付近において、
ＦＥＴ４の歪を減少させる必要があった。On the other hand, this conventional bridge T type variable attenuator utilizes the fact that the resistance value between the drain and the source in the non-saturation region of the FET changes depending on the gate voltage.
If the voltage amplitude of the high-frequency input signal is within the non-saturation region of the FET, the distortion characteristic is less deteriorated. However, as the gate potential is lowered, the non-saturation region of the FET is decreased, so that the distortion characteristic is significantly deteriorated. Even when the input signal power is increased under a constant gate voltage, the distortion characteristics deteriorate as the voltage amplitude of the input signal approaches the saturation region of the FET. FIG. 5 shows the measured value of the D / U ratio of the third-order intermodulation distortion characteristic and the attenuation amount when the gate-source voltage of the conventional bridge T type variable attenuator is changed. In FIG. 5, Vgs 1 = −0.1v and −
There is a maximum point where the D / U ratio deteriorates near 0.9v.
In the vicinity of Vgs 1 = −0.1v among these two maximum points, the distortion of the FET 4 is dominant and Vgs 1 = −0.9.
The distortion of the FET 3 becomes dominant near v. Since the variable attenuator is required to have a characteristic that the amount of distortion is small between 0 dB and several dB, in the vicinity of Vgs 1 = −0.1v,
It was necessary to reduce the distortion of the FET4.
【０００６】[0006]
【発明が解決しようとする課題】この従来の可変減衰器
は所望の減衰量の可変範囲の間で３次混変調歪のＤ／Ｕ
比が所定の特性を確保できない欠点がある。特に減衰量
の少ない領域におけるＦＥＴ４による歪の劣化が生ずる
欠点があった。This conventional variable attenuator has a D / U of third-order intermodulation distortion in a variable range of desired attenuation.
There is a drawback that the ratio cannot ensure a predetermined characteristic. In particular, there is a drawback that distortion of the FET 4 is deteriorated in a region where the amount of attenuation is small.
【０００７】[0007]
【課題を解決するための手段】本発明の可変減衰器は、
モノリシック集積回路に組み込まれ特性インピーダンス
が減衰量にかかわらず一定である定抵抗形可変減衰器で
あって、ドレインを高周波信号の入力としソースを高周
波信号の出力とし、ゲートに制御電圧を印加する第１の
電界効果トランジスタと、この第１の電界効果トランジ
スタのドレイン・ソースのそれぞれに一端を接続し、他
端が共通接続されており、おのおの特性インピーダンス
が等しい抵抗値を有する２つの抵抗と、前記２つの抵抗
の共通接続点にドレインを接続し、ソースを接地電位と
し、ゲートに制御電圧を印加する第２の電界効果トラン
ジスタとを備え、前記第１の電界効果トランジスタのゲ
ート幅と前記第２の電界効果トランジスタのゲート幅と
が異なるように形成されている。The variable attenuator of the present invention comprises:
A constant resistance variable attenuator incorporated in a monolithic integrated circuit whose characteristic impedance is constant regardless of the amount of attenuation, in which the drain is a high frequency signal input, the source is a high frequency signal output, and a control voltage is applied to the gate. One field effect transistor and two resistors, one end of which is connected to each of the drain and source of the first field effect transistor, and the other end of which is commonly connected, each of which has a resistance value having an equal characteristic impedance; A second field effect transistor having a drain connected to a common connection point of the two resistors, a source having a ground potential, and a control voltage applied to a gate; and a gate width of the first field effect transistor and the second field effect transistor. Is formed so as to have a gate width different from that of the field effect transistor.
【０００８】[0008]
【実施例】本発明について図面を参照して説明する。本
発明は使用するＦＥＴの特性を変えることにより可変減
衰器の３次混変調歪特性を改良しているので、回路構成
は図４と同様である。したがって回路符号も図４の符号
をそのまま使用する。図１は本発明の一実施例のＦＥＴ
３のＩ−Ｖ特性、図２は本実施例のＦＥＴ４のＩ−Ｖ特
性、図３は本実施例を適用した歪み特性および減衰量の
特性図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings. Since the present invention improves the third-order cross-modulation distortion characteristic of the variable attenuator by changing the characteristic of the FET used, the circuit configuration is the same as in FIG. Therefore, as the circuit code, the code of FIG. 4 is used as it is. FIG. 1 shows an FET according to an embodiment of the present invention.
3 is an IV characteristic of FIG. 3, FIG. 2 is an IV characteristic of the FET 4 of the present embodiment, and FIG. 3 is a distortion characteristic and attenuation characteristic chart to which the present embodiment is applied.
【０００９】次に本実施例の動作原理を説明する。制御
端子７，８に与えるべき電圧について述べる。ＦＥＴの
チャンネル抵抗Ｒｃは（１）式で表される。Next, the operating principle of this embodiment will be described. The voltage to be applied to the control terminals 7 and 8 will be described. The channel resistance Rc of the FET is expressed by equation (1).
【００１０】 Ｒｃ＝Ｌｇ／２Ｗｇβ（Ｖｇｓ−Ｖｐ） …（１） ここでＶｇｓはゲート・ソース間電圧、Ｖｐはピンチオ
フ電圧、Ｌｇはゲート長、Ｗｇはゲート幅、βは定数で
ある。一方、図４の回路が減衰量にかかわらず特性イン
ピーダンスＺ0 が定抵抗特性を有する条件は、ＦＥＴ
３，４のチャンネル抵抗Ｒ１，Ｒ２が前述したが（２）
式となる場合である。Rc = Lg / 2Wgβ (Vgs−Vp) (1) where Vgs is a gate-source voltage, Vp is a pinch-off voltage, Lg is a gate length, Wg is a gate width, and β is a constant. On the other hand, the condition that the characteristic impedance Z 0 has a constant resistance characteristic regardless of the amount of attenuation in the circuit of FIG.
Although the channel resistances R1 and R2 of 3 and 4 are described above (2)
This is the case when it becomes an expression.
【００１１】 Ｚ0 2 ＝Ｒ1 ・Ｒ2 …（２） （２）式を（１）式を用いて表すと（３）式となる。Z 0 2 = R 1 · R 2 (2) Equation (2) can be expressed by Equation (1) as Equation (3).
【００１２】 [0012]
【００１３】ここで、ＦＥＴ３，４の各パラメータに対
してはそれぞれ添字１，２を付することにする。モノリ
シック集積回路中ではＬｇ1 ＝Ｌｇ2 ＝Ｌｇ，β1 ＝β
2 ＝β，Ｖｐ1 ＝Ｖｐ2 ＝Ｖｐなので（３）式は（４）
式となる。Here, subscripts 1 and 2 are attached to the parameters of the FETs 3 and 4, respectively. In a monolithic integrated circuit, Lg 1 = Lg 2 = Lg, β 1 = β
Since 2 = β, Vp 1 = Vp 2 = Vp, the formula (3) is (4)
It becomes an expression.
【００１４】 [0014]
【００１５】すなわち、（Ｖｇｓ1 −Ｖｐ）と（Ｖｇｓ
2 −Ｖｐ）との積が一定であるようにＶｇｓ1 ，Ｖｇｓ
2 を制御すれば、この可変減衰器の定抵抗性は保たれ
る。That is, (Vgs 1 -Vp) and (Vgs
Vgs 1 such that the product of the 2 -Vp) is constant, Vgs
By controlling 2 , the constant resistance of this variable attenuator is maintained.
【００１６】次に、この可変減衰器の３次混変調歪特性
について説明する。図１は、ＦＥＴ３の電流−電圧（Ｉ
−Ｖ）特性である。図２はＦＥＴ４のＩ−Ｖ特性で図１
のＦＥＴ３のゲート幅を２倍にした場合である。ただ
し、モノリシック集積回路中にゲート幅のみ異なるトラ
ンジスタを配置することを想定しているので、ピンチオ
フ電圧Ｖｐは図１，図２のＦＥＴとも等しく、相互コン
ダクタンスｇm は図２のＦＥＴ４が図１のＦＥＴ３の２
倍となる。すなわち本実施例の可変減衰器のＦＥＴ４の
ゲート幅を拡げることで、Ｖｐ付近のゲート電圧を与え
た時のドレイン電流の飽和電圧Ｖｓ2 （図２参照）が、
Ｖｓ1 （図１参照）に比べて増加するために、ＦＥＴ４
の歪特性が改善される。ＦＥＴ３のゲート幅を拡げた場
合には、ＦＥＴ３のゲート・ソース間容量及びゲート・
ドレイン間容量が増加し、高周波特性が著しく劣化する
ために、所要の信号周波数に対してゲート幅が制限され
る。一方、ＦＥＴ４の容量が高周波特性に及ぼす影響
は、ＦＥＴ３に比べて小さいので、ＦＥＴ４のゲート幅
の選択の自由度は大きい。Next, the third-order intermodulation distortion characteristic of this variable attenuator will be described. FIG. 1 shows the current-voltage (I
-V) characteristic. Figure 2 shows the IV characteristics of FET4.
This is the case where the gate width of the FET 3 is doubled. However, since it is assumed that transistors having different gate widths are arranged in the monolithic integrated circuit, the pinch-off voltage Vp is equal to that of the FETs of FIGS. 1 and 2, and the transconductance g m of the FET 4 of FIG. FET3 2
Doubled. That is, by expanding the gate width of the FET 4 of the variable attenuator of the present embodiment, the saturation voltage Vs 2 (see FIG. 2) of the drain current when a gate voltage near Vp is given,
In order to increase Vs 1 (see FIG. 1), FET4
The distortion characteristics of are improved. When the gate width of FET3 is expanded, the gate-source capacitance and gate
Since the drain-to-drain capacitance increases and the high-frequency characteristics are significantly deteriorated, the gate width is limited to the required signal frequency. On the other hand, since the influence of the capacitance of the FET 4 on the high frequency characteristics is smaller than that of the FET 3, the degree of freedom in selecting the gate width of the FET 4 is large.
【００１７】このようにＦＥＴ３に比較してゲート幅の
異なるＦＥＴ４を組み込むことにより、定抵抗型可変減
衰器の３次混変調歪特性は図３の特性図のように歪み特
性Ａの値が従来例より改善される。なお、歪み特性Ｂは
従来例とほぼ同じであり、減衰量の可変特性も変らない
ので、混変調歪の値が減衰量の少ない方で改善される。As described above, by incorporating the FET 4 having a gate width different from that of the FET 3, the third-order intermodulation distortion characteristic of the constant resistance type variable attenuator has a conventional value of the distortion characteristic A as shown in the characteristic diagram of FIG. Better than the example. The distortion characteristic B is almost the same as that of the conventional example, and since the variable characteristic of the attenuation amount does not change, the value of the intermodulation distortion is improved when the attenuation amount is small.
【００１８】[0018]
【発明の効果】以上説明したように本発明は、ゲート幅
の異なる２つのＦＥＴにより可変減衰器を構成している
ので、モノリシック集積回路中の可変減衰器をＦＥＴに
より構成でき、歪特性の良好な定抵抗形可変減衰器が実
現できる効果がある。As described above, according to the present invention, since the variable attenuator is composed of the two FETs having different gate widths, the variable attenuator in the monolithic integrated circuit can be composed of the FETs, and the distortion characteristic is excellent. There is an effect that a constant resistance type variable attenuator can be realized.
【図１】本発明の一実施例のＦＥＴ３の特性図である。FIG. 1 is a characteristic diagram of a FET 3 according to an embodiment of the present invention.
【図２】本実施例のＦＥＴ４の特性図である。FIG. 2 is a characteristic diagram of a FET 4 of this embodiment.
【図３】本実施例を適用した可変減衰器の特性図であ
る。FIG. 3 is a characteristic diagram of a variable attenuator to which this embodiment is applied.
【図４】本発明の一実施例および従来例に共通の回路図
である。FIG. 4 is a circuit diagram common to an embodiment of the present invention and a conventional example.
【図５】従来の可変減衰器の特性図である。FIG. 5 is a characteristic diagram of a conventional variable attenuator.
１ 入力 ２ 出力 ３，４ 電界効果トランジスタ（ＦＥＴ） ５，６ 抵抗値Ｚ0 の抵抗 ７，８ 制御端子1 input 2 output 3,4 field effect transistor (FET) 5,6 resistance of resistance value Z 0 7,8 control terminal
Claims (1)
インピーダンスが減衰量にかかわらず一定である定抵抗
形可変減衰器であって、ドレインを高周波信号の入力と
しソースを高周波信号の出力とし、ゲートに制御電圧を
印加する第１の電界効果トランジスタと、この第１の電
界効果トランジスタのドレイン・ソースのそれぞれに一
端を接続し、他端が共通接続されており、おのおの特性
インピーダンスが等しい抵抗値を有する２つの抵抗と、
前記２つの抵抗の共通接続点にドレインを接続し、ソー
スを接地電位とし、ゲートに制御電圧を印加する第２の
電界効果トランジスタとを備え、前記第１の電界効果ト
ランジスタのゲート幅と前記第２の電界効果トランジス
タのゲート幅とが異なるように形成されていることを特
徴とする可変減衰器。1. A constant resistance variable attenuator which is incorporated in a monolithic integrated circuit and whose characteristic impedance is constant irrespective of the amount of attenuation, wherein the drain is a high frequency signal input, the source is a high frequency signal output, and the gate is controlled. One end of each of the first field effect transistor for applying a voltage and the drain / source of the first field effect transistor is connected, and the other end is commonly connected, and each has a resistance value with an equal characteristic impedance. Two resistances,
A second field effect transistor that connects a drain to a common connection point of the two resistors, sets a source to a ground potential, and applies a control voltage to a gate, and includes a gate width of the first field effect transistor and the second field effect transistor. 2. A variable attenuator, which is formed so that the gate width of the field effect transistor 2 is different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22238392A JP2924483B2 (en) | 1992-08-21 | 1992-08-21 | Variable attenuator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22238392A JP2924483B2 (en) | 1992-08-21 | 1992-08-21 | Variable attenuator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0669754A true JPH0669754A (en) | 1994-03-11 |
| JP2924483B2 JP2924483B2 (en) | 1999-07-26 |
Family
ID=16781500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22238392A Expired - Lifetime JP2924483B2 (en) | 1992-08-21 | 1992-08-21 | Variable attenuator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2924483B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6542045B2 (en) | 2000-01-17 | 2003-04-01 | Nec Compound Semiconductor Devices, Ltd. | High-frequency variable attenuator having a controllable reference voltage |
| CN111988014A (en) * | 2020-09-02 | 2020-11-24 | 成都芯川电子有限公司 | Low phase shift broadband numerical control attenuator applied to microwave and millimeter waves |
-
1992
- 1992-08-21 JP JP22238392A patent/JP2924483B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6542045B2 (en) | 2000-01-17 | 2003-04-01 | Nec Compound Semiconductor Devices, Ltd. | High-frequency variable attenuator having a controllable reference voltage |
| CN111988014A (en) * | 2020-09-02 | 2020-11-24 | 成都芯川电子有限公司 | Low phase shift broadband numerical control attenuator applied to microwave and millimeter waves |
| CN111988014B (en) * | 2020-09-02 | 2024-05-03 | 成都芯川电子有限公司 | Low phase shift broadband digital control attenuator applied to microwave and millimeter wave |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2924483B2 (en) | 1999-07-26 |
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| Date | Code | Title | Description |
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| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19990406 |