JPH0669265A - Semiconductor device package - Google Patents

Semiconductor device package

Info

Publication number
JPH0669265A
JPH0669265A JP4245640A JP24564092A JPH0669265A JP H0669265 A JPH0669265 A JP H0669265A JP 4245640 A JP4245640 A JP 4245640A JP 24564092 A JP24564092 A JP 24564092A JP H0669265 A JPH0669265 A JP H0669265A
Authority
JP
Japan
Prior art keywords
semiconductor device
chip
inner leads
device chip
bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4245640A
Other languages
Japanese (ja)
Inventor
Tadashi Mimura
忠士 三村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP4245640A priority Critical patent/JPH0669265A/en
Publication of JPH0669265A publication Critical patent/JPH0669265A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance reliability of bonding by wire bonding inner leads in a fixed state. CONSTITUTION:Inner leads 4 of a lead frame are overhung from a pair of opposed sides on a circuit forming surface of an IC chip 2. A support base 6 made of hard insulation resin for a plurality of continued inner leads to a surface of the chip 2 and a soft resin film 8 which can absorb a stress are held on lower parts of bonding areas 4a. The areas 4a are connected to bonding pads 12 in a state that the base 6 and the film 8 are held by a wire bonding method, and then sealed with molding resin.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は半導体装置チップをモー
ルド樹脂で封止した半導体装置実装体とその製造方法に
関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package in which a semiconductor device chip is sealed with a molding resin and a method for manufacturing the same.

【０００２】[0002]

【従来の技術】半導体装置実装体のうち、ＬＯＣ（Lead
on Chip）構造ではリードフレームのインナーリード部
分が半導体装置チップ（以下、ＩＣチップという）の回
路形成面上に張り出している。インナーリードと半導体
装置チップのボンディングパッドとの間を電気的に接続
するワイヤボンディング工程では、インナーリードとＩ
Ｃチップ表面との間にすき間のある状態でボンディング
がなされる。インナーリードが浮いた状態でワイヤボン
ディングが施されるが、ワイヤボンディングの際にイン
ナーリードがＩＣチップの回路形成面に押しつけられて
回路形成面に応力が加わるのを防ぐために、インナーリ
ードを支持する支持リードをＩＣチップの側端面に接着
固定した実装体が提案されている（特開平３−１９２７
３５号公報参照）。2. Description of the Related Art Among semiconductor device mounting bodies, LOC (Lead
In the on-chip structure, the inner lead portion of the lead frame overhangs the circuit formation surface of the semiconductor device chip (hereinafter referred to as IC chip). In the wire bonding process for electrically connecting the inner lead and the bonding pad of the semiconductor device chip, the inner lead and the I
Bonding is performed with a gap between the C chip surface and the surface. Wire bonding is performed with the inner leads floating, but the inner leads are supported in order to prevent the inner leads from being pressed against the circuit forming surface of the IC chip and applying stress to the circuit forming surface during wire bonding. A mounting body has been proposed in which a supporting lead is adhesively fixed to a side end surface of an IC chip (JP-A-3-1927).
35 gazette).

【０００３】[0003]

【発明が解決しようとする課題】ＬＯＣ構造のリードフ
レームでは、ワイヤボンディングの際にインナーリード
がＩＣチップ表面から浮いた状態になっていると、仮り
に引例のように支持リードをＩＣチップに固定したとし
ても、インナーリードとＩＣチップ表面の間には１００
〜２００μｍ程度の隙間があるのが普通であるので、ワ
イヤボンディングの際にインナーリードが撓むことは避
けられない。ワイヤボンディングの際にインナーリード
が撓むとインナーリードにワイヤが接続されにくくな
り、ボンディングの信頼性が低くなる。インナーリード
とＩＣチップ表面との隙間が１０μｍ程度もあればボン
ディングの信頼性に影響がでる。本発明はＬＯＣ構造
で、インナーリードが固定された状態でワイヤボンディ
ングを行なうことができるようにしてボンディングの信
頼性を高めた実装体とその実装方法を提供することを目
的とするものである。In the lead frame having the LOC structure, if the inner leads are floated from the surface of the IC chip during wire bonding, the support leads are fixed to the IC chip as in the case of the reference. Even if it is done, there is 100 between the inner lead and the IC chip surface.
Since there is usually a gap of about 200 μm, it is unavoidable that the inner lead bends during wire bonding. If the inner lead bends during wire bonding, it becomes difficult for the wire to be connected to the inner lead, and the reliability of bonding decreases. If the gap between the inner leads and the surface of the IC chip is about 10 μm, the reliability of bonding will be affected. SUMMARY OF THE INVENTION It is an object of the present invention to provide a mounting body and a mounting method thereof, which have a LOC structure and can perform wire bonding in a state where inner leads are fixed, thereby improving bonding reliability.

【０００４】[0004]

【課題を解決するための手段】本発明の実装体では、半
導体装置チップの回路形成面上に複数のインナーリード
が配設され、それらのインナーリードと前記半導体チッ
プの回路形成面との間には複数のインナーリードについ
て連続した絶縁物製の支持部材が挾み込まれた状態で、
半導体装置チップとインナーリードとがボンディングワ
イヤで電気的に接続され、少なくとも半導体装置チッ
プ、ボンディングワイヤ及びインナーリードがモールド
樹脂で封止されている。好ましい態様では、支持部材の
うち半導体装置チップとの接触面は応力吸収可能な軟質
樹脂フィルムである。In the package of the present invention, a plurality of inner leads are provided on the circuit forming surface of the semiconductor device chip, and the inner leads are provided between the inner leads and the circuit forming surface of the semiconductor chip. Is a state in which a continuous insulating support member is sandwiched between a plurality of inner leads,
The semiconductor device chip and the inner lead are electrically connected with a bonding wire, and at least the semiconductor device chip, the bonding wire and the inner lead are sealed with a molding resin. In a preferred embodiment, the contact surface of the supporting member with the semiconductor device chip is a soft resin film capable of absorbing stress.

【０００５】上記の実装体を製造するために、本発明の
製造方法では半導体装置チップの回路形成面上に複数の
インナーリードを配設し、それらのインナーリードと半
導体チップの回路形成面との間に複数のインナーリード
について連続し、半導体装置チップとの接触面が応力吸
収可能な軟質樹脂フィルムとなっている絶縁物製の支持
部材を挾み込み、その状態で半導体装置チップとインナ
ーリードとをボンディングワイヤで電気的に接続し、少
なくとも半導体装置チップ、ボンディングワイヤ及びイ
ンナーリードをモールド樹脂で封止する。In order to manufacture the above-mentioned mounting body, in the manufacturing method of the present invention, a plurality of inner leads are arranged on the circuit forming surface of the semiconductor device chip, and the inner leads are connected to the circuit forming surface of the semiconductor chip. A support member made of an insulator, which is continuous between a plurality of inner leads and whose contact surface with the semiconductor device chip is a soft resin film capable of absorbing stress, is sandwiched between the semiconductor device chip and the inner leads. Are electrically connected with a bonding wire, and at least the semiconductor device chip, the bonding wire and the inner lead are sealed with a molding resin.

【０００６】本発明の他の態様では、半導体装置チップ
の回路形成面上に複数のインナーリードが配設され、各
インナーリードのボンディング部分は半導体装置チップ
側の厚みが厚くなり、かつ半導体装置チップ側の面には
応力吸収可能な軟質樹脂フィルムが貼りつけられてお
り、半導体装置チップとインナーリードとがボンディン
グワイヤで電気的に接続され、少なくとも半導体装置チ
ップ、ボンディングワイヤ及びインナーリードがモール
ド樹脂で封止されている。According to another aspect of the present invention, a plurality of inner leads are provided on the circuit forming surface of the semiconductor device chip, the bonding portion of each inner lead has a larger thickness on the semiconductor device chip side, and the semiconductor device chip has a larger thickness. A soft resin film capable of absorbing stress is attached to the side surface, and the semiconductor device chip and the inner lead are electrically connected by a bonding wire, and at least the semiconductor device chip, the bonding wire and the inner lead are made of a mold resin. It is sealed.

【０００７】[0007]

【実施例】図１は第１の実施例を表わす。ＩＣチップ２
の回路形成面上には対向する一対の側方からリードフレ
ームのインナーリード４が張り出している。各インナー
リードの先端部４ａはボンディングエリアであり、そこ
にワイヤボンディングがなされる。ボンディングエリア
４ａの下部には、ＩＣチップ２の表面との間に複数のイ
ンナーリードについて連続した絶縁物製の支持台６が挾
み込まれている。支持台６はボンディング性を向上さ
せ、かつインナーリード間を絶縁するために、硬質の絶
縁樹脂で構成されている。支持台６とＩＣチップ２の表
面との間にはワイヤボンディングの際にＩＣチップ２の
回路形成面に応力が作用してＩＣチップ２の素子が破損
するのを防ぐために、応力吸収可能な軟質の樹脂フィル
ム８が挾み込まれている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment. IC chip 2
Inner leads 4 of the lead frame project from a pair of opposite sides on the circuit forming surface. The tip portion 4a of each inner lead is a bonding area, and wire bonding is performed there. Below the bonding area 4a, a support base 6 made of an insulating material is sandwiched between the surface of the IC chip 2 and a plurality of inner leads. The support base 6 is made of a hard insulating resin in order to improve the bondability and to insulate the inner leads from each other. In order to prevent damage to the elements of the IC chip 2 due to stress acting on the circuit formation surface of the IC chip 2 during wire bonding between the support base 6 and the surface of the IC chip 2, a soft material capable of absorbing stress. The resin film 8 of is sandwiched.

【０００８】ワイヤボンディングは支持台６とフィルム
８がインナーリード４とＩＣチップ２との間に挾み込ま
れた状態でなされる。１０はインナーリードのボンディ
ングエリア４ａと対応するＩＣチップのボンディングパ
ッド１２との間を接続するボンディングワイヤである。
ワイヤボンディングがなされた後、支持台６とフィルム
８が挾み込まれた状態で、少なくともＩＣチップ２、イ
ンナーリード４及びワイヤ１０がモールド樹脂（図示
略）によって封止されている。樹脂封止の際、支持台６
とフィルム８を取り除いてもよい。The wire bonding is performed with the support base 6 and the film 8 sandwiched between the inner leads 4 and the IC chip 2. A bonding wire 10 connects the bonding area 4a of the inner lead and the bonding pad 12 of the corresponding IC chip.
After the wire bonding is performed, at least the IC chip 2, the inner leads 4 and the wires 10 are sealed with a mold resin (not shown) with the support 6 and the film 8 sandwiched therebetween. Support stand 6 for resin sealing
The film 8 may be removed.

【０００９】図１の実施例の実装体を製造するには、打
抜き又はエッチングにより製作されたリードフレームと
ＩＣチップ２とを位置決めし、インナーリード４のボン
ディングエリア４ａとＩＣチップ２との間に応力吸収可
能なフィルム８を下側にして支持台６とそのフィルム８
とを挾み込み、その状態でワイヤボンディングを施す。
その後、支持台６とフィルム８を残し、又は取り除いた
後、ＩＣチップ２が接続されたリードフレームを樹脂封
止用の金型に装着し、エポキシ樹脂などのモールド樹脂
を注入して樹脂封止を行なう。In order to manufacture the mounting body of the embodiment shown in FIG. 1, the lead frame manufactured by punching or etching and the IC chip 2 are positioned, and between the bonding area 4a of the inner lead 4 and the IC chip 2. The support 8 and its film 8 with the stress-absorbable film 8 facing down
And the wire are bonded in that state.
Then, after leaving or removing the support base 6 and the film 8, the lead frame to which the IC chip 2 is connected is mounted on a mold for resin sealing, and a mold resin such as epoxy resin is injected to seal the resin. Do.

【００１０】図２は第２の実施例を表わす。ＩＣチップ
２上に張り出して配設された各インナーリード１４の先
端のボンディングエリア１４ａのＩＣチップ側の厚さが
厚くなって支持台１６を構成している。各支持台１６の
ＩＣチップ側の面には応力吸収可能な軟質樹脂フィルム
１８が貼りつけられている。ワイヤボンディングはイン
ナーリード先端の支持台１６がフィルム１８を介してＩ
Ｃチップ２の表面に接触した状態でワイヤ１０がボンデ
ィングされる。ワイヤボンディングされた後、少なくと
もＩＣチップ２、インナーリード１４及びワイヤ１０が
モールド樹脂（図示略）によって封止される。図２の実
施例でインナーリードの先端に支持台１６を一体的に形
成するには、支持台１６を含む厚さの金属板にフィルム
１８を貼りつけてパターン化した後、金属板にエッチン
グを施してインナーリード１４を形成すればよい。FIG. 2 shows a second embodiment. The thickness of the bonding area 14a at the tip of each inner lead 14 projectingly arranged on the IC chip 2 on the IC chip side is increased to form the support base 16. A soft resin film 18 capable of absorbing stress is attached to the surface of each support 16 on the IC chip side. For wire bonding, the support base 16 at the tip of the inner lead is I
The wire 10 is bonded while being in contact with the surface of the C chip 2. After wire bonding, at least the IC chip 2, the inner leads 14 and the wires 10 are sealed with a mold resin (not shown). In order to integrally form the support base 16 on the tips of the inner leads in the embodiment of FIG. 2, a film 18 is attached to a metal plate having a thickness including the support base 16 to form a pattern, and then the metal plate is etched. The inner lead 14 may be formed by applying the heat treatment.

【００１１】[0011]

【発明の効果】本発明ではインナーリードのボンディン
グエリアとＩＣチップ表面の間に支持台が存在するの
で、ワイヤボンディングの際にインナーリードが固定さ
れており、ワイヤボンディングの信頼性が向上する。支
持台とＩＣチップ表面との間に応力吸収可能な軟質樹脂
フィルムを設けることにより、ワイヤボンディングの際
にＩＣチップの回路形成面に加わる応力が緩和され、Ｉ
Ｃチップの素子が破損するのを防ぐことができる。According to the present invention, since the support is provided between the bonding area of the inner leads and the surface of the IC chip, the inner leads are fixed during wire bonding, and the reliability of wire bonding is improved. By providing a soft resin film capable of absorbing stress between the support and the surface of the IC chip, the stress applied to the circuit forming surface of the IC chip at the time of wire bonding is relaxed.
It is possible to prevent the element of the C chip from being damaged.

【図面の簡単な説明】[Brief description of drawings]

【図１】第１の実施例の要部斜視断面図である。FIG. 1 is a perspective sectional view of an essential part of a first embodiment.

【図２】第２の実施例の要部斜視断面図である。FIG. 2 is a perspective sectional view of an essential part of a second embodiment.

【符号の説明】[Explanation of symbols]

２ ＩＣチップ ４，１４ インナーリード ４ａ，１４ａ インナーリードのボンディングエリ
ア ６ 絶縁物製支持台 ８，１８ 応力吸収可能な軟質フィルム １０ ワイヤ １２ ボンディングパッド １６ インナーリードと一体の支持台2 IC chips 4,14 Inner leads 4a, 14a Inner lead bonding area 6 Insulator support 8,18 Soft film capable of absorbing stress 10 Wires 12 Bonding pads 16 Supports integrated with inner leads

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 半導体装置チップの回路形成面上に複数
のインナーリードが配設され、それらのインナーリード
と前記半導体チップの回路形成面との間には複数のイン
ナーリードについて連続した絶縁物製の支持部材が挾み
込まれた状態で、前記半導体装置チップとインナーリー
ドとがボンディングワイヤで電気的に接続され、少なく
とも前記半導体装置チップ、ボンディングワイヤ及びイ
ンナーリードがモールド樹脂で封止されていることを特
徴とする半導体装置実装体。1. A plurality of inner leads are provided on a circuit forming surface of a semiconductor device chip, and a plurality of inner leads made of an insulating material are provided between the inner leads and the circuit forming surface of the semiconductor chip. The semiconductor device chip and the inner lead are electrically connected by a bonding wire with the support member sandwiched therebetween, and at least the semiconductor device chip, the bonding wire and the inner lead are sealed with a mold resin. A semiconductor device package characterized by the above. 【請求項２】 前記支持部材のうち前記半導体装置チッ
プとの接触面は応力吸収可能な軟質樹脂フィルムである
請求項１に記載の半導体装置実装体。2. The semiconductor device package according to claim 1, wherein a contact surface of the supporting member with the semiconductor device chip is a soft resin film capable of absorbing stress. 【請求項３】 半導体装置チップの回路形成面上に複数
のインナーリードを配設し、それらのインナーリードと
前記半導体チップの回路形成面との間に複数のインナー
リードについて連続し、前記半導体装置チップとの接触
面が応力吸収可能な軟質樹脂フィルムとなっている絶縁
物製の支持部材を挾み込み、その状態で前記半導体装置
チップとインナーリードとをボンディングワイヤで電気
的に接続し、少なくとも前記半導体装置チップ、ボンデ
ィングワイヤ及びインナーリードをモールド樹脂で封止
することを特徴とする半導体装置の実装方法。3. A plurality of inner leads are provided on a circuit forming surface of a semiconductor device chip, and the plurality of inner leads are continuous between the inner leads and the circuit forming surface of the semiconductor chip. A support member made of an insulator whose contact surface with the chip is a soft resin film capable of absorbing stress is sandwiched, and in that state, the semiconductor device chip and the inner lead are electrically connected with a bonding wire, at least A method for mounting a semiconductor device, comprising encapsulating the semiconductor device chip, the bonding wires, and the inner leads with a molding resin. 【請求項４】 半導体装置チップの回路形成面上に複数
のインナーリードが配設され、各インナーリードのボン
ディング部分は半導体装置チップ側の厚みが厚くなり、
かつ半導体装置チップ側の面には応力吸収可能な軟質樹
脂フィルムが貼りつけられており、前記半導体装置チッ
プとインナーリードとがボンディングワイヤで電気的に
接続され、少なくとも前記半導体装置チップ、ボンディ
ングワイヤ及びインナーリードがモールド樹脂で封止さ
れていることを特徴とする半導体装置実装体。4. A plurality of inner leads are provided on a circuit forming surface of a semiconductor device chip, and a bonding portion of each inner lead becomes thicker on the semiconductor device chip side,
A soft resin film capable of absorbing stress is attached to the surface of the semiconductor device chip side, the semiconductor device chip and the inner leads are electrically connected by a bonding wire, and at least the semiconductor device chip, the bonding wire, and A semiconductor device package, wherein the inner leads are sealed with a molding resin.
JP4245640A 1992-08-21 1992-08-21 Semiconductor device package Pending JPH0669265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4245640A JPH0669265A (en) 1992-08-21 1992-08-21 Semiconductor device package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4245640A JPH0669265A (en) 1992-08-21 1992-08-21 Semiconductor device package

Publications (1)

Publication Number Publication Date
JPH0669265A true JPH0669265A (en) 1994-03-11

Family

ID=17136666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4245640A Pending JPH0669265A (en) 1992-08-21 1992-08-21 Semiconductor device package

Country Status (1)

Country Link
JP (1) JPH0669265A (en)

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