JPH0666263B2 - III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure - Google Patents
III-V compound semiconductor / insulator / III-V compound semiconductor laminated structureInfo
- Publication number
- JPH0666263B2 JPH0666263B2 JP60283882A JP28388285A JPH0666263B2 JP H0666263 B2 JPH0666263 B2 JP H0666263B2 JP 60283882 A JP60283882 A JP 60283882A JP 28388285 A JP28388285 A JP 28388285A JP H0666263 B2 JPH0666263 B2 JP H0666263B2
- Authority
- JP
- Japan
- Prior art keywords
- iii
- compound semiconductor
- insulator
- laminated structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Formation Of Insulating Films (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体／絶縁体／半導体積層構造に関する。TECHNICAL FIELD The present invention relates to a semiconductor / insulator / semiconductor laminated structure.
（従来の技術） 従来、半導体・絶縁体膜積層構造は、ビームアニール技
術を用いたSOI（セミコンダクタ オンインシュレータ:
Semiconductor on Insulator）構造として、シリコン
を対象に作成されて来た。この際、絶縁体膜が単結晶で
あればSOI構造を、より容易に作成することが可能にな
る。シリコンの場合ではマグネシアスピネル（MgO・Al2
O3）や弗化カルシウム（CaF2）を基板上にエピタキシャ
ル成長させ、その上に単結晶シリコンを成長させてい
る。(Prior Art) Conventionally, the semiconductor / insulator film laminated structure has been manufactured by using an SOI (semiconductor on insulator:
Semiconductor on Insulator) structure has been created for silicon. At this time, if the insulating film is a single crystal, the SOI structure can be formed more easily. In the case of silicon, magnesia spinel (MgO ・ Al 2
O 3 ) and calcium fluoride (CaF 2 ) are epitaxially grown on the substrate, and single crystal silicon is grown thereon.
（発明が解決しようとする問題点） しかし、マグネシアスピネルのエピタキシャル成長温度
は約900℃以上であり、この温度では下地III−Ｖ化合物
半導体の表面が熱損傷を受ける。また、弗化物の熱膨張
係数は約２×10-5K-1で、III−Ｖ化合物半導体の熱膨張
係数、代表的にはガリウム砒素の６×10-6K-1という値
との差が大きく、III−Ｖ化合物半導体と弗化物の界面
には熱歪が生じやすい。さら、、従来の絶縁体とIII−
Ｖ化合物半導体では、イオン性差が大きいため界面に大
きなダイポールが生じ良好な界面が形成されにくい。本
発明の目的は熱損傷・熱歪を避けて形成することが可能
であり、かつ積層界面でのダイポールを抑制した、III
−Ｖ化合物半導体／絶縁体／III−Ｖ化合物半導体積層
構造を提供することにある。(Problems to be Solved by the Invention) However, the epitaxial growth temperature of magnesia spinel is about 900 ° C. or higher, and at this temperature, the surface of the underlying III-V compound semiconductor is thermally damaged. The coefficient of thermal expansion of fluoride is about 2 × 10 -5 K -1 , which is different from the coefficient of thermal expansion of III-V compound semiconductors, typically 6 × 10 -6 K -1 of gallium arsenide. Is large, and thermal strain easily occurs at the interface between the III-V compound semiconductor and the fluoride. Furthermore, the conventional insulator and III-
In the V compound semiconductor, a large dipole is generated at the interface because of a large ionic difference, and it is difficult to form a good interface. The object of the present invention is that it can be formed while avoiding thermal damage and thermal strain, and that the dipole at the laminated interface is suppressed, III
An object is to provide a -V compound semiconductor / insulator / III-V compound semiconductor laminated structure.
（問題点を解決するための手段） 本発明においては、III−Ｖ化合物半導体上に窒化アル
ミニウム膜、あるいは窒化アルミニウムと窒化ガリウム
の混晶膜を形成したのち、この上にIII−Ｖ化合物半導
体を積層する。窒化アルミニウム等の絶縁膜を形成する
際には、III−Ｖ化合物半導体の表面劣化を防ぐ必要が
ある。それには、例えば、トリメチルアルミニウムとア
ンモニアを原料にしかつ原子サイクロトロン共鳴プラズ
マを用いるか、あるいはトリメチルアルミニウムとヒド
ラジンを原料とする熱CVD法によって、それぞれ400℃以
上の基板温度で成長を行なえば良い。窒化アルミニウム
・窒化ガリウム混晶の作製には、ガリウム原料、例えば
トリメチルガリウムを上記原料に加えて成長を行えば良
い。(Means for Solving Problems) In the present invention, an aluminum nitride film or a mixed crystal film of aluminum nitride and gallium nitride is formed on a III-V compound semiconductor, and then a III-V compound semiconductor is formed thereon. Stack. When forming an insulating film such as aluminum nitride, it is necessary to prevent surface deterioration of the III-V compound semiconductor. For this purpose, for example, growth may be performed at a substrate temperature of 400 ° C. or higher by using trimethylaluminum and ammonia as raw materials and using atomic cyclotron resonance plasma, or by a thermal CVD method using trimethylaluminum and hydrazine as raw materials. In order to produce an aluminum nitride / gallium nitride mixed crystal, a gallium raw material, for example, trimethylgallium may be added to the above raw material and grown.
窒化アルミニウムと窒化ガリウムの混晶を用いる場合、
混晶中に窒化アルミニウムが約40％以上含まれる様にす
るのが好ましい。窒化アルミニウム膜がこれより少ない
と混晶の絶縁性は十分でない。When using a mixed crystal of aluminum nitride and gallium nitride,
It is preferable that the mixed crystal contains about 40% or more of aluminum nitride. If the aluminum nitride film is smaller than this, the insulating property of the mixed crystal is not sufficient.
（作用） 本発明の構造では、上・下の半導体部がIII−Ｖ化合物
材料で構成されるIII−Ｖ化合物半導体／絶縁体／III−
Ｖ化合物半導体積層構造において、中間の絶縁体部まで
もがIII族窒化物、すなわちIII−Ｖ化合物材料で構成さ
れる。本構造の実現には、上部III−Ｖ化合物半導体／
絶縁体間、及び絶縁体／下部III−Ｖ化合物半導体間で
イオン性の差と熱膨張係数の差が小さい必要がある。II
I族窒化物はIII−Ｖ化合物半導体と同じIII−Ｖ化合物
であるため、他の絶縁体材料にくらべ、III−Ｖ化合物
半導体とのイオン性差・熱膨張係数差がともに小さく、
良好なIII−Ｖ化合物半導体−絶縁体界面の形成に有利
である。(Operation) In the structure of the present invention, the upper and lower semiconductor portions are composed of a III-V compound semiconductor / insulator / III-
In the V compound semiconductor laminated structure, even the intermediate insulator portion is composed of a group III nitride, that is, a III-V compound material. To realize this structure, the upper III-V compound semiconductor /
The difference in ionicity and the coefficient of thermal expansion between the insulators and between the insulator / lower III-V compound semiconductor must be small. II
Since the group I nitride is the same III-V compound as the III-V compound semiconductor, both the ionic difference and the thermal expansion coefficient difference with the III-V compound semiconductor are smaller than those of other insulator materials.
It is advantageous for forming a good III-V compound semiconductor-insulator interface.
（実施例） 本実施例ではIII−Ｖ化合物半導体の一つであるガリウ
ムヒ素（GaAs）基板上に絶縁体膜を形成させた後、基板
と同じGaAsをその上に成長させた。(Example) In this example, after forming an insulator film on a gallium arsenide (GaAs) substrate which is one of III-V compound semiconductors, the same GaAs as the substrate was grown thereon.
GaAs（111）ウェハを化学的にエッチングする。トリメ
チルガリウム（TMG）とアルシン（AsH3）を原料にしてM
OCVD法によりウェハ上に約1000ÅGaAsを成長させる。こ
れを基板として続けてトリメチルアルミニウム（TM
A），ヒドラジン（N2H4）を原料にして、AlNのMOCVDを
行なう。この時TMA,N2H4温度は20℃，バブル水素流量は
それぞれ毎分5cc,200cc,基板温度は600℃，総流量は毎
分8l,圧力は80Torrに設定し、10分間で厚さ約500ÅのAl
N膜を得た。更に続けてTMG,AsH3を原料にしてMOCVD法に
よりGaAsを成長させることができた。Chemically etch a GaAs (111) wafer. Using trimethylgallium (TMG) and arsine (AsH 3 ) as raw materials, M
About 1000Å GaAs is grown on the wafer by OCVD method. Continue to use this as a substrate for trimethylaluminum (TM
A), AlN MOCVD is performed using hydrazine (N 2 H 4 ) as a raw material. At this time, TMA, N 2 H 4 temperature was 20 ° C, bubble hydrogen flow rate was 5 cc / 200 cc / min, substrate temperature was 600 ° C, total flow rate was 8 l / min, pressure was set to 80 Torr, and thickness was about 10 minutes. 500Å Al
An N film was obtained. Furthermore, it was possible to grow GaAs by MOCVD using TMG and AsH 3 as raw materials.
窒化アルミニウム，窒化ガリウムの混晶作成にはTMG,TM
A,N2H4を原料にした。TMG,TMA,N2H4温度はそれぞれ−12
℃,20℃,20℃，バブル水素流量はそれぞれ毎分１cc,4c
c,200cc，基板温度は600℃，総流量は毎分8l圧力は80To
rrに設定し、10分間で約500ÅのAl0.6Ga0.4Ｎ0.4を作成
した。TMG, TM for mixed crystal of aluminum nitride and gallium nitride
A, N 2 H 4 was used as a raw material. TMG, TMA, N 2 H 4 Temperature is −12
℃, 20 ℃, 20 ℃, bubble hydrogen flow rate is 1cc / min
c, 200cc, substrate temperature 600 ℃, total flow rate 8l / min pressure 80To
rr was set, and Al 0.6 Ga 0.4 N 0.4 of about 500 Å was prepared in 10 minutes.
（発明の効果） 本発明によれば、熱損傷・熱劣化を避け、かつ界面ダイ
ポールを抑制したIII−Ｖ化合物半導体／絶縁体／III−
Ｖ化合物半導体積層構造が実現される。本発明の構造
は、すべてがIII−Ｖ化合物材料からなる、従来にない
新規なものである。本発明により、III−Ｖ化合物半導
体を用いた半導体／絶縁体／半導体（SIS）構造デバイ
スが作製可能になる。また、本発明の積層構造をさらに
積層することにより、III−Ｖ化合物半導体基板上にIII
−Ｖ化合物半導体／絶縁体／III−Ｖ化合物半導体／絶
縁体／III−Ｖ化合物半導体／…という積層構造を構成
することができる。この積層構造により、絶縁体を障壁
層、III−Ｖ化合物半導体を井戸層とする量子井戸構造
デバイスを作製することも可能になる。(Effects of the Invention) According to the present invention, a III-V compound semiconductor / insulator / III- which avoids thermal damage / deterioration and suppresses an interface dipole.
A V compound semiconductor laminated structure is realized. The structure of the present invention is an unprecedented novel one, which is composed entirely of III-V compound materials. The present invention enables fabrication of semiconductor / insulator / semiconductor (SIS) structure devices using III-V compound semiconductors. Further, by further stacking the stacked structure of the present invention, III-V compound semiconductor substrate
A laminated structure of -V compound semiconductor / insulator / III-V compound semiconductor / insulator / III-V compound semiconductor / ... Can be formed. This laminated structure also makes it possible to fabricate a quantum well structure device in which the insulator is a barrier layer and the III-V compound semiconductor is a well layer.
Claims (1)
ウム膜または窒化アルミニウム・窒化ガリウム混晶膜、
更にその上にIII−Ｖ化合物半導体を重ねてなることを
特徴とするIII−Ｖ化合物半導体／絶縁体／III−Ｖ化合
物半導体積層構造。1. An aluminum nitride film or an aluminum nitride / gallium nitride mixed crystal film on a III-V compound semiconductor,
A III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure, characterized by further stacking a III-V compound semiconductor thereon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60283882A JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60283882A JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62141720A JPS62141720A (en) | 1987-06-25 |
| JPH0666263B2 true JPH0666263B2 (en) | 1994-08-24 |
Family
ID=17671397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60283882A Expired - Lifetime JPH0666263B2 (en) | 1985-12-16 | 1985-12-16 | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0666263B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0512565A (en) * | 1991-07-08 | 1993-01-22 | Sanyo Electric Co Ltd | Electronic cash register |
| EP0553856B1 (en) * | 1992-01-31 | 2002-04-17 | Canon Kabushiki Kaisha | Method of preparing a semiconductor substrate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6027699A (en) * | 1983-07-22 | 1985-02-12 | Agency Of Ind Science & Technol | Preparation of single crystal film of silicon carbide |
| JP2616759B2 (en) * | 1985-01-07 | 1997-06-04 | 株式会社 半導体エネルギー研究所 | Thin film formation method |
| JPS62119939A (en) * | 1985-11-19 | 1987-06-01 | Sharp Corp | Insulating substrate for semiconductor |
-
1985
- 1985-12-16 JP JP60283882A patent/JPH0666263B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62141720A (en) | 1987-06-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9691712B2 (en) | Method of controlling stress in group-III nitride films deposited on substrates | |
| US5239188A (en) | Gallium nitride base semiconductor device | |
| US6121121A (en) | Method for manufacturing gallium nitride compound semiconductor | |
| JP4935700B2 (en) | Group III nitride compound semiconductor manufacturing method, wafer, group III nitride compound semiconductor device | |
| US8679955B2 (en) | Method for forming epitaxial wafer and method for fabricating semiconductor device | |
| US6967355B2 (en) | Group III-nitride on Si using epitaxial BP buffer layer | |
| US6818926B2 (en) | Method for manufacturing gallium nitride compound semiconductor | |
| JPH033364A (en) | Semiconductor device | |
| JPH073814B2 (en) | Method for manufacturing semiconductor substrate | |
| KR100583163B1 (en) | Nitride semiconductor and fabrication method for thereof | |
| KR101171324B1 (en) | Method of forming buffer layer for a light emitting device of a nitride compound semiconductor and buffer layer formed by the method | |
| JPH0666263B2 (en) | III-V compound semiconductor / insulator / III-V compound semiconductor laminated structure | |
| JP3757339B2 (en) | Method for manufacturing compound semiconductor device | |
| JP3147821B2 (en) | Nitride compound semiconductor, crystal growth method thereof, and gallium nitride light emitting device | |
| JP2000091252A (en) | Gallium nitride based compound semiconductor and semiconductor device | |
| KR100821220B1 (en) | Light emitting device of a nitride compound semiconductor having multi buffer layers and the fabrication method thereof | |
| JPH0618174B2 (en) | Semiconductor substrate | |
| JPH10190059A (en) | Nitride compound semiconductor device and its manufacturing method | |
| WO2023002865A1 (en) | Template substrate and manufacturing method and manufacturing apparatus thereof, semiconductor substrate and manufacturing method and manufacturing apparatus thereof, semiconductor device, and electronic device | |
| JPS6066811A (en) | Manufacture of compound semiconductor device | |
| JPH05267175A (en) | Compound semiconductor substrate | |
| KR20220160890A (en) | Ⅲ-N semiconductor structure and method of manufacturing the same | |
| KR20060076675A (en) | Nitride semiconductor and method for manufacturing the same | |
| JP3255798B2 (en) | Compound semiconductor device and method of manufacturing the same | |
| JPS632391A (en) | Magnetoelectric transducer |