JPH066178A - Afc circuit - Google Patents
Afc circuitInfo
- Publication number
- JPH066178A JPH066178A JP18740892A JP18740892A JPH066178A JP H066178 A JPH066178 A JP H066178A JP 18740892 A JP18740892 A JP 18740892A JP 18740892 A JP18740892 A JP 18740892A JP H066178 A JPH066178 A JP H066178A
- Authority
- JP
- Japan
- Prior art keywords
- intermediate frequency
- circuit
- frequency
- oscillator
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Mobile Radio Communication Systems (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ディジタル通信の移動
局に用いられ基地局周波数を受信してこの周波数に追従
させ周波数を安定化させるＡＦＣ(automatic frequency
control) 回路に関する。BACKGROUND OF THE INVENTION The present invention relates to an AFC (automatic frequency) used in a mobile station for digital communication, which receives a base station frequency and tracks the frequency to stabilize the frequency.
control) Regarding the circuit.
【０００２】[0002]
【従来の技術】移動局の受信機には、一般にスーパーヘ
テロダイン方式の受信機が用いられ、受信周波数から中
間周波数への周波数変換を行う局部発振器を備えてい
る。この局部発振器は、例えば、電圧制御−温度補償水
晶発振器（以下、ＶＣ−ＴＣＸＯと略記する）等の基準
発振器と、基準発振器からの発振周波数を中間周波数に
変換する手段（逓倍回路、ＰＬＬシンセサイザ等）とか
ら構成されるが、この局部発振器の発振周波数に偏差が
含まれていると、中間周波数が所定値からずれ、正確な
復調ができなくなり、送信周波数もずれてしまう。従っ
て、受信周波数に追従して中間周波数を安定化させるべ
く、局部発振器の発振周波数から偏差を除去する必要が
ある。このため、ＡＦＣ回路を挿入して局部発振器の発
振周波数の偏差を補正している。2. Description of the Related Art As a receiver of a mobile station, a superheterodyne type receiver is generally used and is equipped with a local oscillator for performing frequency conversion from a reception frequency to an intermediate frequency. This local oscillator is, for example, a reference oscillator such as a voltage-controlled temperature-compensated crystal oscillator (hereinafter abbreviated as VC-TCXO), and means for converting an oscillation frequency from the reference oscillator into an intermediate frequency (multiplier circuit, PLL synthesizer, etc.). If the oscillation frequency of this local oscillator includes a deviation, the intermediate frequency deviates from a predetermined value, accurate demodulation cannot be performed, and the transmission frequency also deviates. Therefore, it is necessary to remove the deviation from the oscillation frequency of the local oscillator so as to follow the reception frequency and stabilize the intermediate frequency. Therefore, an AFC circuit is inserted to correct the deviation of the oscillation frequency of the local oscillator.
【０００３】図３は、上述のＡＦＣ回路を備えたダブル
スーパーヘテロダイン受信機の一構成例を示すブロック
図であり、図において、１は受信アンテナ、２，３はミ
キサ、４は増幅器、５は符号判定回路、６は第１局発と
してのＰＬＬシンセサイザ、７は第２局発としてのＮ逓
倍回路、８はＰＬＬシンセサイザ、９はミキサ、１０は
増幅器、１１は送信アンテナ、２０はＡＦＣ回路を示
す。FIG. 3 is a block diagram showing an example of the structure of a double superheterodyne receiver equipped with the above AFC circuit. In the figure, 1 is a receiving antenna, 2 and 3 are mixers, 4 is an amplifier, and 5 is A code determination circuit, 6 is a PLL synthesizer as a first station, 7 is an N multiplier circuit as a second station, 8 is a PLL synthesizer, 9 is a mixer, 10 is an amplifier, 11 is a transmitting antenna, and 20 is an AFC circuit. Show.
【０００４】ミキサ２にはＰＬＬシンセサイザ６からの
第１局部発振周波数ＦL1が入力され、ミキサ３にはＮ逓
倍回路７からの第２局部発振周波数ＦL2が入力され、受
信アンテナ１からの入力信号ＦR がミキサ２を介して第
１中間周波数ＦIF1 に変換され、ミキサ３を介して第２
中間周波数ＦIF2 に変換されて増幅器４で増幅され、符
号判定回路５に入力されて符号判定が行われて復調出力
を得る。また送信においては、ＰＬＬシンセサイザ８か
らの送信用中間周波数ＦIFT が、ミキサ９でＰＬＬシン
セサイザ６からの出力と混合されて出力信号ＦT を送信
アンテナ１１から出力する。The mixer 2 receives the first local oscillation frequency F L1 from the PLL synthesizer 6, and the mixer 3 receives the second local oscillation frequency F L2 from the N multiplication circuit 7 and inputs from the receiving antenna 1. The signal F R is converted into the first intermediate frequency F IF1 via the mixer 2 and the second intermediate frequency F IF1 via the mixer 3.
The signal is converted into the intermediate frequency F IF2 , amplified by the amplifier 4, input to the code determination circuit 5, and subjected to code determination to obtain a demodulated output. In the transmission, the intermediate frequency F IFT for transmission from the PLL synthesizer 8 is mixed with the output from the PLL synthesizer 6 in the mixer 9, and the output signal F T is output from the transmitting antenna 11.
【０００５】次にＡＦＣ回路２０について説明する。Ａ
ＦＣ回路２０は、カウンタ２１、演算部２２、ＲＯＭ２
３、Ｄ／Ａコンバータ２４、ＶＣ−ＴＣＸＯ２５で構成
されており、受信周波数ＦR に追従して中間周波数Ｆ
IF1 ，ＦIF2 ，ＦIFT を安定化させるべく、局部発振器
の発振周波数の偏差を補正する制御を行っている。以
下、これを説明する。Next, the AFC circuit 20 will be described. A
The FC circuit 20 includes a counter 21, a calculation unit 22, and a ROM 2.
3, the D / A converter 24, and the VC-TCXO 25, and follows the reception frequency F R to generate the intermediate frequency F
In order to stabilize IF1 , F IF2 , and F IFT , control is performed to correct the deviation of the oscillation frequency of the local oscillator. This will be described below.
【０００６】仮に、ＡＦＣ回路２０からの出力ｆ0 に偏
差αが重畳している場合、ＰＬＬシンセサイザ６の出力
はＦL1（１＋α），Ｎ逓倍回路７の出力はＦL2（１＋
α），ＰＬＬシンセサイザ８の出力はＦIFT （１＋α）
となる。そして、偏差を含む第１中間周波数をＦ’
IF1 、同じく第２中間周波数をＦ’IF2 で表せば、 Ｆ’IF1 ＝ＦL1（１＋α）−ＦR Ｆ’IF2 ＝ＦL2（１＋α）−Ｆ’IF1 ＝ＦL2（１＋α）−ＦL1（１＋α）＋ＦR ＝α（ＦL2−ＦL1）＋ＦL2−ＦL1＋ＦR となる。 後式に ＦIF1 ＝ＦL1−ＦR ＦIF2 ＝ＦL2−ＦIF1 ＝ＦL2−ＦL1＋ＦR を代入すると、 Ｆ’IF2 ＝α（ＦIF2 −ＦR ）＋ＦIF2 と表せる。こ
の中間周波数Ｆ’IF2 をゲートタイム ＧT ＝ｎ／ｆ0 （１＋α） の間（ｎは分周数）計数す
ると、その計数値ＤA は、 ＤA ＝Ｆ’IF2 ×ＧT ＝｛α（ＦIF2 −ＦR ）＋ＦIF2 ｝×｛ｎ／ｆ0 （１＋α）｝ ＝｛ＦIF2 （１＋α）−αＦR ｝×｛ｎ／ｆ0 （１＋α）｝ ＝ｎ／ｆ0 ・（ＦIF2 ）−αｎ／ｆ0 （１＋α） と表せる。 従って、計数値ＤA をｎ／ｆ0 ・（ＦIF2 ）に近づけれ
ば、偏差αもα→０となり、偏差α・ｆ0 がなくなるよ
うに発振周波数を制御できる。If the deviation α is superimposed on the output f 0 from the AFC circuit 20, the output of the PLL synthesizer 6 is FL 1 (1 + α), and the output of the N multiplication circuit 7 is FL 2 (1+).
α), the output of the PLL synthesizer 8 is F IFT (1 + α)
Becomes Then, the first intermediate frequency including the deviation is F ′
IF1, 'if indicated by the IF2, F' also the second intermediate frequency F IF1 = F L1 (1 + α) -F R F = 'IF2 = F L2 (1 + α) -F' IF1 F L2 (1 + α) -F L1 ( 1 + α) + F R = α a (F L2 -F L1) + F L2 -F L1 + F R. Substituting F IF1 = F L1 −F R F IF2 = F L2 −F IF1 = F L2 −F L1 + F R into the following equation, it can be expressed as F ′ IF2 = α (F IF2 −F R ) + F IF2 . 'If during the gate time the IF2 G T = n / f 0 (1 + α) (n is the frequency division number) for counting, the count value D A is, D A = F' the intermediate frequency F IF2 × G T = {α (F IF2- F R ) + F IF2 } × {n / f 0 (1 + α)} = {F IF2 (1 + α) −αF R } × {n / f 0 (1 + α)} = n / f 0 · (F IF2 ) -Αn / f 0 (1 + α). Therefore, when the count value D A is brought close to n / f 0 · (F IF2 ), the deviation α also becomes α → 0, and the oscillation frequency can be controlled so that the deviation α · f 0 disappears.
【０００７】すなわちＡＦＣ回路２０では、増幅器４か
らの出力周波数を、カウンタ２１で、ＶＣ−ＴＣＸＯ２
５の出力周波数をｎ分周したゲート時間の間計数し、演
算部２２でこの計数値ＤA を取り込み、ＲＯＭ２３の内
容に基づいて、ＤB ＝ａ・｛ｎ／ｆ0 ・（ＦIF2 ）−Ｄ
A ｝の演算を行い、補正データＤB を出力する。ちなみ
に、フィードバック制御を行わない場合には、ＤB ＝ａ
・ＤA となる。フィードバック制御により補正されたデ
ータＤB は、Ｄ／Ａコンバータ２４でアナロクの直流電
圧に変換され、ＶＣ−ＴＣＸＯ２５に入力され、ＶＣ−
ＴＣＸＯ２５の発振周波数ｆ0 を制御する。そして、Ｖ
Ｃ−ＴＣＸＯ２５の発振出力が、ＰＬＬシンセサイザ６
及び８、Ｎ逓倍回路７に供給される。That is, in the AFC circuit 20, the counter 21 measures the output frequency from the amplifier 4 by VC-TCXO2.
The output frequency of 5 is counted during the gate time divided by n, and the count value D A is fetched by the arithmetic unit 22, and D B = a · {n / f 0 · (F IF2 ) based on the contents of the ROM 23. -D
A } is calculated and the correction data D B is output. By the way, when feedback control is not performed, D B = a
・ It becomes D A. The data D B corrected by the feedback control is converted into an analog DC voltage by the D / A converter 24, input to the VC-TCXO 25, and VC-TCXO25.
The oscillation frequency f 0 of the TCXO 25 is controlled. And V
The oscillation output of the C-TCXO25 is the PLL synthesizer 6
8 and N are supplied to the N multiplication circuit 7.
【０００８】以上のようにして、ＶＣ−ＴＣＸＯ２５の
発振周波数の偏差α・ｆ0 が０となるような制御が行わ
れ、受信周波数ＦR への追従が確保され、さらに送信周
波数ＦT の受信周波数ＦR （移動無線の場合、基地局の
送信周波数）への追従が確保される。また、各局部発振
器の発振周波数を、一つの基準発振器ＶＣ−ＴＣＸＯ２
５を基準としているため、比較的その構成が簡素にでき
るという特徴がある。As described above, control is performed such that the deviation α · f 0 of the oscillation frequency of the VC-TCXO 25 becomes 0, tracking of the reception frequency F R is ensured, and reception of the transmission frequency F T is further performed. Tracking to the frequency F R (transmission frequency of the base station in the case of mobile radio) is ensured. In addition, the oscillation frequency of each local oscillator is set to one reference oscillator VC-TCXO2.
Since it is based on 5, there is a feature that the configuration can be relatively simple.
【０００９】[0009]
【発明が解決しようとする課題】上記のような従来のＡ
ＦＣ回路は以上のように構成され動作するが、受信入力
レベルが小さいときに、入力レベルが時間的に落ち込む
フェージングが発生すると、入力レベルが落ち込んでい
るときのカウンタ２１の入力が、自然界ノイズの全くラ
ンダムな周波数となってしまい、このカウンタ２１の計
数値に誤差が発生し、発振周波数の正確な制御が困難に
なる。また、増幅器４からの出力は矩形波でなくアナロ
グ信号のため、デジタル回路に直接入力される従来のＡ
ＦＣ回路の場合、カウンタ２１が誤動作する恐れがある
等の問題点があった。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The FC circuit is configured and operates as described above, but when fading occurs in which the input level drops temporally when the reception input level is small, the input of the counter 21 when the input level drops is the noise of the natural world. The frequency becomes completely random, and an error occurs in the count value of the counter 21, making it difficult to accurately control the oscillation frequency. Further, since the output from the amplifier 4 is not a rectangular wave but an analog signal, the conventional A that is directly input to the digital circuit is used.
In the case of the FC circuit, there is a problem that the counter 21 may malfunction.
【００１０】例えば米国仕様ディジタルセルラーに適用
する場合に顕著な問題が生じる。すなわちこの仕様で
は、基地局に追従した状態で移動局側に許容される周波
数偏差は、±２００Ｈｚ（ＲＦ周波数が８００ＭＨｚ帯
なので±０．２５ｐｐｍ）という小さな値であり、且
つ、ハンドオフ時には１３０ｍｓｅｃ以内でこの周波数
偏差内にＶＣ−ＴＣＸＯ２５の周波数を引き込んで送信
を開始しなければならず、カウンタ２１での計数時間も
非常に短い。従って、例えば、中間周波数の計数時間を
１００ｍｓｅｃとすると、１つの計数誤差が発振周波数
の偏差では１０Ｈｚとなり、２０個以上の誤りがあると
±２００Ｈｚの許容値を満足できなくなり、上述のよう
な従来のＡＦＣ回路は適用できなくなる。本発明は上述
のような問題点を解決するためになされたものである。A significant problem arises when applied to, for example, US specification digital cellular. In other words, in this specification, the frequency deviation allowed on the mobile station side while following the base station is a small value of ± 200 Hz (± 0.25 ppm because the RF frequency is in the 800 MHz band), and within 130 msec during handoff. It is necessary to pull in the frequency of the VC-TCXO 25 within this frequency deviation to start transmission, and the counting time in the counter 21 is also very short. Therefore, for example, if the counting time of the intermediate frequency is 100 msec, one count error is 10 Hz in the deviation of the oscillation frequency, and if there are 20 or more errors, the allowable value of ± 200 Hz cannot be satisfied, and the above-mentioned conventional The AFC circuit of No. cannot be applied. The present invention has been made to solve the above problems.
【００１１】[0011]
【課題を解決するための手段】本発明に係るＡＦＣ回路
は、コンパレータとクロック発振器と論理回路とで構成
され、入力した中間周波数信号を波形整形すると共に受
信信号の弱電界時を検出し、通常は中間周波数に同期し
たクロックを出力し、弱電界時のみ自己発振したクロッ
クを出力する中間周波数保護回路を設け、この中間周波
数保護回路の出力周波数をカウンタで計数することとし
た。An AFC circuit according to the present invention comprises a comparator, a clock oscillator and a logic circuit, which shapes the waveform of an input intermediate frequency signal and detects a weak electric field of a received signal. Has an intermediate frequency protection circuit that outputs a clock synchronized with the intermediate frequency and outputs a clock that self-oscillates only when the electric field is weak. The output frequency of this intermediate frequency protection circuit is counted by a counter.
【００１２】[0012]
【作用】本発明においては、入力信号レベルが時間的に
落ち込むフェージングが発生したときに、コンパレータ
でこれを検出し、クロック発振器で自己発振したクロッ
クを出力することとしたので、フェージングが発生した
ときでも自然界ノイズの全くランダムな周波数が計数さ
れることを防止でき、発振周波数の正確な制御が行え
る。また、入力した中間周波数信号をコンパレータで波
形整形するため、ディジタル回路の誤動作を防止でき
る。In the present invention, when fading occurs in which the input signal level drops temporally, the comparator detects it and outputs the clock self-oscillated by the clock oscillator. Therefore, when fading occurs However, it is possible to prevent the counting of completely random frequencies of natural noise, and to accurately control the oscillation frequency. Moreover, since the waveform of the input intermediate frequency signal is shaped by the comparator, malfunction of the digital circuit can be prevented.
【００１３】[0013]
【実施例】以下、本発明の実施例を図面に基づき説明す
る。図１は本発明の一実施例を示すブロック図であり、
図において、図３と同一符号は同一又は相当部分を示
し、２６は中間周波数保護回路を示す。この中間周波数
保護回路２６は、コンパレータとクロック発振器と論理
回路とで構成されており、入力した中間周波数信号をコ
ンパレータで波形整形すると共に、受信信号の弱電界時
を検出する。そして、通常は中間周波数に同期したクロ
ックを出力し、弱電界時のみ自己発振させたクロックを
出力するように動作する。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, the same reference numerals as those in FIG. 3 denote the same or corresponding portions, and 26 denotes an intermediate frequency protection circuit. The intermediate frequency protection circuit 26 includes a comparator, a clock oscillator, and a logic circuit. The intermediate frequency protection circuit 26 shapes the input intermediate frequency signal by the comparator and detects the weak electric field of the received signal. Then, it normally operates so as to output a clock synchronized with the intermediate frequency and output a self-oscillated clock only when the electric field is weak.
【００１４】図２は、上述の中間周波数保護回路２６の
動作を説明するための波形図であり、受信入力レベルが
感度付近の小さいときに、入力レベルが時間的に落ち込
むフェージングが発生すると、入力レベルが落ち込んで
いるときの増幅器４の出力は、図（Ａ）に示すようにレ
ベルが落ち、且つ、自然界ノイズの全くランダムな周波
数となる。この信号をヒステリシスを持ったコンパレー
タによって波形整形すると、その出力は図（Ｂ）の様に
なり、フェージング時の全くランダムな周波数が取り除
かれ、フェージング時はＬレベル（またはＨレベル）に
固定される。FIG. 2 is a waveform diagram for explaining the operation of the above-mentioned intermediate frequency protection circuit 26, and when fading occurs in which the input level temporally drops when the input level is small near the sensitivity, the input is input. When the level is lowered, the output of the amplifier 4 is lowered in level as shown in FIG. 5A and has a completely random frequency of natural noise. When the waveform of this signal is shaped by a comparator having hysteresis, its output becomes as shown in FIG. 7B, and completely random frequencies at the time of fading are removed and fixed at L level (or H level) at fading. .
【００１５】中間周波数保護回路２６内の論理回路は、
図（Ｃ）に示すように、通常はクロック発振器からのク
ロックパルスをコンパレータの出力の立上りに同期させ
て出力し、コンパレータの出力の立上りが一定時間内に
来ない場合、中間周波数に近い周波数で発振させている
クロック発振器のクロックパルスを出力し、フェージン
グ時のパルス抜けを防止する。この中間周波数保護回路
２６からの出力がカウンタ２１に入力され、カウンタ２
１はこの出力を計数するため、フェージング時の全くラ
ンダムな周波数が計数される様な事態を防止でき、フェ
ージングによる影響を排除し、ＶＣ−ＴＣＸＯ２５の発
振周波数をより正確に制御することができる。また、回
路構成は簡単なものであり、移動局に適した構成である
ため、移動局の小型化、簡素化を実現できる。さらに、
増幅器４の出力はコンパレータで矩形波に波形整形され
るため、この信号をデジタル回路に入力しても誤動作を
生じることがなくなる。The logic circuit in the intermediate frequency protection circuit 26 is
As shown in FIG. 7C, normally, a clock pulse from a clock oscillator is output in synchronization with the rising edge of the output of the comparator, and when the rising edge of the output of the comparator does not come within a certain time, the frequency is close to the intermediate frequency. The clock pulse of the oscillating clock oscillator is output to prevent pulse loss during fading. The output from the intermediate frequency protection circuit 26 is input to the counter 21, and the counter 2
Since 1 counts this output, it is possible to prevent a situation in which totally random frequencies are counted during fading, eliminate the influence of fading, and control the oscillation frequency of the VC-TCXO 25 more accurately. Further, the circuit configuration is simple and suitable for the mobile station, so that the mobile station can be downsized and simplified. further,
Since the output of the amplifier 4 is shaped into a rectangular wave by the comparator, malfunction does not occur even if this signal is input to the digital circuit.
【００１６】[0016]
【発明の効果】本発明は以上説明したように、入力レベ
ルが時間的に落ち込むフェージング時にコンパレータで
これを検出し、クロック発振器で自己発振させることと
したので、フェージングが発生したときでも自然界ノイ
ズの全くランダムな周波数が計数されてしまう事態を防
止でき、発振周波数の正確な制御が行える。また、入力
した中間周波数信号をコンパレータで波形整形するた
め、ディジタル回路の誤動作を防止できる等の効果があ
る。As described above, according to the present invention, the comparator detects the fading when the input level drops temporally and causes the clock oscillator to self-oscillate. Therefore, even when fading occurs, the noise of the natural world is eliminated. It is possible to prevent a situation in which completely random frequencies are counted, and it is possible to accurately control the oscillation frequency. Further, since the waveform of the input intermediate frequency signal is shaped by the comparator, it is possible to prevent malfunction of the digital circuit.
【図１】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
【図２】図１に示す保護回路の動作を示す波形図であ
る。FIG. 2 is a waveform diagram showing an operation of the protection circuit shown in FIG.
【図３】従来のＡＦＣ回路を示すブロック図である。FIG. 3 is a block diagram showing a conventional AFC circuit.
２０ ＡＦＣ回路 ２１ カウンタ ２２ 演算部 ２３ ＲＯＭ ２４ Ｄ／Ａコンバータ ２５ ＶＣ−ＴＣＸＯ ２６ 中間周波数保護回路 20 AFC circuit 21 counter 22 arithmetic unit 23 ROM 24 D / A converter 25 VC-TCXO 26 intermediate frequency protection circuit
Claims (1)
信周波数に追従させて中間周波数を安定化させるため中
間周波数を入力し局部発振器を制御するフィードバック
制御回路に組み込まれ、 カウンタと演算部と電圧制御発振器とを有し、 カウンタで中間周波数を計数し、この計数値を基に演算
部で順次演算処理を行い、演算値を更新しながら電圧制
御発振器を制御するＡＦＣ(automatic frequency contr
ol）回路において、 コンパレータとクロック発振器と論理回路とで構成さ
れ、入力した中間周波数信号を波形整形すると共に受信
信号の弱電界時を検出し、通常は中間周波数に同期した
クロックを出力し、弱電界時のみ自己発振したクロック
を出力する中間周波数保護回路、 この中間周波数保護回路の出力をカウンタで計数し、こ
の計数値を基に演算部で順次演算処理を行い演算値を更
新しながら電圧制御発振器を制御する手段、 を備えたＡＦＣ回路。1. A feedback control circuit used in a mobile station for digital communication, for inputting an intermediate frequency and controlling a local oscillator for stabilizing an intermediate frequency by following a received frequency, a counter, an arithmetic unit, and a voltage. It has a control oscillator, counts the intermediate frequency with a counter, and the arithmetic unit sequentially performs arithmetic processing based on this count value and controls the voltage controlled oscillator while updating the arithmetic value. AFC (automatic frequency contr)
ol) circuit, which is composed of a comparator, a clock oscillator and a logic circuit, shapes the input intermediate frequency signal and detects the weak electric field of the received signal, and usually outputs a clock synchronized with the intermediate frequency. An intermediate frequency protection circuit that outputs a clock that self-oscillates only when an electric field is generated.The output of this intermediate frequency protection circuit is counted by a counter, and based on this count value, the calculation unit performs sequential calculation processing and voltage control is performed while updating the calculation value. An AFC circuit including means for controlling an oscillator.
Priority Applications (10)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18740892A JP2767518B2 (en) | 1992-06-23 | 1992-06-23 | AFC circuit |
| CA002098660A CA2098660C (en) | 1992-06-23 | 1993-06-17 | Automatic frequency control circuit |
| US08/080,407 US5513388A (en) | 1992-06-23 | 1993-06-18 | Automatic frequency control circuit |
| AU41408/93A AU659018B2 (en) | 1992-06-23 | 1993-06-21 | Automatic frequency control circuit |
| EP95104801A EP0663725A1 (en) | 1992-06-23 | 1993-06-23 | Automatic frequency control circuit |
| EP93304891A EP0580294B1 (en) | 1992-06-23 | 1993-06-23 | Automatic frequency control circuit |
| EP95104800A EP0662754A1 (en) | 1992-06-23 | 1993-06-23 | Automatic frequency control circuit |
| DE69317825T DE69317825T2 (en) | 1992-06-23 | 1993-06-23 | Automatic frequency control circuit |
| AU13454/95A AU671570B2 (en) | 1992-06-23 | 1995-02-23 | Automatic frequency control circuit |
| AU13453/95A AU670896B2 (en) | 1992-06-23 | 1995-02-23 | Automatic frequency control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18740892A JP2767518B2 (en) | 1992-06-23 | 1992-06-23 | AFC circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH066178A true JPH066178A (en) | 1994-01-14 |
| JP2767518B2 JP2767518B2 (en) | 1998-06-18 |
Family
ID=16205515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18740892A Expired - Lifetime JP2767518B2 (en) | 1992-06-23 | 1992-06-23 | AFC circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2767518B2 (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6165618A (en) * | 1984-09-07 | 1986-04-04 | Nec Corp | Automatic frequency control circuit |
| JPS6326020A (en) * | 1986-07-18 | 1988-02-03 | Nippon Telegr & Teleph Corp <Ntt> | Receiving equipment having frequency measuring function |
| JPS6423467A (en) * | 1987-07-17 | 1989-01-26 | Canon Kk | Pll circuit for information reproducing device |
| JPH01128624A (en) * | 1987-11-13 | 1989-05-22 | Nippon Telegr & Teleph Corp <Ntt> | Moving radio equipment with frequency stabilizing function |
| JPH0413280A (en) * | 1990-05-02 | 1992-01-17 | Olympus Optical Co Ltd | Phased lock loop circuit for recording and reproducing information |
-
1992
- 1992-06-23 JP JP18740892A patent/JP2767518B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6165618A (en) * | 1984-09-07 | 1986-04-04 | Nec Corp | Automatic frequency control circuit |
| JPS6326020A (en) * | 1986-07-18 | 1988-02-03 | Nippon Telegr & Teleph Corp <Ntt> | Receiving equipment having frequency measuring function |
| JPS6423467A (en) * | 1987-07-17 | 1989-01-26 | Canon Kk | Pll circuit for information reproducing device |
| JPH01128624A (en) * | 1987-11-13 | 1989-05-22 | Nippon Telegr & Teleph Corp <Ntt> | Moving radio equipment with frequency stabilizing function |
| JPH0413280A (en) * | 1990-05-02 | 1992-01-17 | Olympus Optical Co Ltd | Phased lock loop circuit for recording and reproducing information |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2767518B2 (en) | 1998-06-18 |
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