JPH066177A - Electronic tuner - Google Patents
Electronic tunerInfo
- Publication number
- JPH066177A JPH066177A JP15811292A JP15811292A JPH066177A JP H066177 A JPH066177 A JP H066177A JP 15811292 A JP15811292 A JP 15811292A JP 15811292 A JP15811292 A JP 15811292A JP H066177 A JPH066177 A JP H066177A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- high frequency
- frequency amplifier
- tuning
- pll
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Noise Elimination (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、テレビジョン受像機や
VTR等に用いる電子チューナに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic tuner used for a television receiver, a VTR or the like.
【0002】[0002]
【従来の技術】図2は従来のPLL選局回路を備えた電
子チューナのブロック図である。図2において、1は入
力同調回路、2は高周波増幅回路、3は段間同調回路、
4は混合回路、5は中間周波同調回路、6は局部発振回
路、7はPLL選局回路であって、該PLL選局回路7
からの出力信号である同調電圧13は上記入力同調回路
1、段間同調回路3、及び局部発振回路6に導かれる。2. Description of the Related Art FIG. 2 is a block diagram of an electronic tuner having a conventional PLL channel selection circuit. In FIG. 2, 1 is an input tuning circuit, 2 is a high frequency amplifier circuit, 3 is an interstage tuning circuit,
Reference numeral 4 is a mixing circuit, 5 is an intermediate frequency tuning circuit, 6 is a local oscillation circuit, and 7 is a PLL tuning circuit.
A tuning voltage 13, which is an output signal from the input circuit, is guided to the input tuning circuit 1, the interstage tuning circuit 3, and the local oscillation circuit 6.
【0003】8はアンテナ入力端子、9は中間周波増幅
回路、10は出力端子、11はマイコン(図示せず)等
からの選局信号を上記PLL選局回路7に入力する入力
端子、12は上記PLL回路7が選局動作期間中ロック
信号を出力するロック信号出力端子、14は上記中間周
波増幅回路9から上記高周波増幅回路2に供給されるA
GC電圧であり、一点鎖線で囲むブロック14は電子チ
ューナ本体を示す。Reference numeral 8 is an antenna input terminal, 9 is an intermediate frequency amplifier circuit, 10 is an output terminal, 11 is an input terminal for inputting a tuning signal from a microcomputer (not shown) or the like to the PLL tuning circuit 7, and 12 is a terminal. The PLL circuit 7 outputs a lock signal output terminal for outputting a lock signal during a channel selection operation, and 14 is supplied from the intermediate frequency amplifier circuit 9 to the high frequency amplifier circuit 2.
This is a GC voltage, and a block 14 surrounded by a chain line shows an electronic tuner body.
【0004】上記の構成より成る電子チューナは、マイ
コン等からの選局信号が入力端子11に入力されると、
局部発振回路6の信号の一部がPLL選局回路7に入力
されているため入力されたマイコンからのデータに基づ
いた周波数に各段の同調周波数を合わせるように上記P
LL選局回路7から同調電圧13が導出される。In the electronic tuner having the above structure, when a tuning signal from a microcomputer or the like is input to the input terminal 11,
Since a part of the signal of the local oscillation circuit 6 is input to the PLL channel selection circuit 7, the P frequency is adjusted so that the tuning frequency of each stage is adjusted to the frequency based on the input data from the microcomputer.
The tuning voltage 13 is derived from the LL tuning circuit 7.
【0005】この同調電圧13は、入力同調回路1、段
間同調回路3及び局発同調回路6に印加され、アンテナ
入力端子8より入力される信号の中から、目的の周波数
を入力同調回路1、高周波増幅回路2、段間同調回路3
で選択増幅するように働き、混合回路4で局部発振回路
6より供給される局部発振周波数の信号と混合されて中
間周波数に変換される。This tuning voltage 13 is applied to the input tuning circuit 1, the inter-stage tuning circuit 3 and the local tuning circuit 6, and the target frequency is selected from the signals input from the antenna input terminal 8. , High-frequency amplifier circuit 2, interstage tuning circuit 3
In the mixing circuit 4, the signal is mixed with the signal of the local oscillation frequency supplied from the local oscillation circuit 6 and converted into an intermediate frequency.
【0006】中間周波数に変換された同調信号は、中間
周波同調回路5で選択された後、中間周波増幅回路9に
導かれ、増幅検波されて出力端子10より導出される。
また、上記中間周波増幅回路9より検波された水平同期
信号を取り出し、これを平滑したAGC電圧14を高周
波増幅回路2に供給し、中間周波増幅回路9への入力レ
ベルが一定になるように上記高周波増幅回路2の増幅度
を調整して、アンテナ入力端子8の入力信号レベルに対
応し、入力信号が飽和しないように制御している。The tuning signal converted to the intermediate frequency is selected by the intermediate frequency tuning circuit 5, then guided to the intermediate frequency amplifier circuit 9, amplified and detected, and then derived from the output terminal 10.
Further, the horizontal synchronizing signal detected by the intermediate frequency amplifier circuit 9 is taken out, and the smoothed AGC voltage 14 is supplied to the high frequency amplifier circuit 2 so that the input level to the intermediate frequency amplifier circuit 9 becomes constant. The amplification degree of the high frequency amplifier circuit 2 is adjusted so as to correspond to the input signal level of the antenna input terminal 8 and control is performed so that the input signal is not saturated.
【0007】[0007]
【発明が解決しようとする課題】上記従来の装置におい
ては、アンテナ入力端子に、非常に強い入力信号が到来
した場合、これをPLL選局回路で選局しようとする
と、選局期間中は、中間周波数増幅回路に信号が入力さ
れないため、入力信号レベルに応じたAGC電圧が出力
されず、高周波増幅回路は最大増幅度の状態で動作し、
この状態は選局動作が完了するまで継続する。In the above conventional apparatus, when a very strong input signal arrives at the antenna input terminal, if a PLL tuning circuit tries to tune it, during the tuning period, Since no signal is input to the intermediate frequency amplifier circuit, the AGC voltage corresponding to the input signal level is not output, and the high frequency amplifier circuit operates in the maximum amplification state,
This state continues until the tuning operation is completed.
【0008】しかし、PLL選局回路による選局動作の
終了近くになると、各同調回路の同調周波数は、目的の
周波数に近づき、同調点から少しずれたところではある
が、目的の信号は、高周波増幅回路に強入力として印加
されることになり、高周波増幅回路は最大感度状態で動
作しているので、飽和状態になって所謂AGCロック現
象が起きる。However, near the end of the tuning operation by the PLL tuning circuit, the tuning frequency of each tuning circuit approaches the target frequency and is slightly displaced from the tuning point, but the target signal is high frequency. Since the high frequency amplifier circuit is applied as a strong input and the high frequency amplifier circuit operates in the maximum sensitivity state, the saturation state occurs and a so-called AGC lock phenomenon occurs.
【0009】高周波増幅回路が飽和すると、入力信号の
スプリアスが発生し、そのレベルも非常に大きなものと
なるので、そのスプリアスが段間同調回路、混合回路、
局部発振回路等を経由してPLL選局回路に入力され
る。その結果、PLL選局回路においては正規の局部発
振信号との区別ができなくなりスプリアスの信号を正規
の局部発振信号と誤認し、PLL選局回路が誤動作をす
るという問題が発生する。When the high frequency amplifying circuit is saturated, spurious of the input signal is generated and the level thereof becomes very large. Therefore, the spurious is interstage tuning circuit, mixing circuit,
It is input to the PLL tuning circuit via a local oscillation circuit or the like. As a result, the PLL tuning circuit cannot distinguish it from the regular local oscillation signal, and the spurious signal is mistakenly recognized as the regular local oscillation signal, causing a problem that the PLL tuning circuit malfunctions.
【0010】[0010]
【課題を解決するための手段】本発明は上記の問題を解
決するため、高周波増幅回路と局部発振回路と混合回路
とPLL選局回路とを備えた電子チューナにおいて、上
記PLL選局回路の選局動作期間中、上記高周波増幅回
路の利得を下げる利得調整回路を設け、アンテナからの
強入力信号に対する上記PLL選局回路の誤動作を防止
するように構成する。In order to solve the above problems, the present invention provides an electronic tuner including a high frequency amplifier circuit, a local oscillator circuit, a mixing circuit, and a PLL tuning circuit, in which the selection of the PLL tuning circuit is performed. A gain adjusting circuit for lowering the gain of the high frequency amplifying circuit is provided during the station operation period so as to prevent malfunction of the PLL channel selecting circuit with respect to a strong input signal from the antenna.
【0011】[0011]
【作用】上記の構成によれば、PLL選局回路が選局動
作を行っている期間中、利得調整回路は、高周波増幅回
路の利得を下げた状態にするので、アンテナ入力端子よ
り強入力の信号が印加されても、上記高周波増幅回路を
飽和させないように動作せることができ、強入力による
スプリアスの発生を防止して、PLL選局回路の誤動作
を防止させることができる。According to the above configuration, the gain adjusting circuit keeps the gain of the high frequency amplifier circuit lowered during the period in which the PLL tuning circuit is performing the tuning operation. Even if a signal is applied, the high frequency amplifier circuit can be operated so as not to be saturated, spurious due to strong input can be prevented, and malfunction of the PLL channel selection circuit can be prevented.
【0012】[0012]
【実施例】図1は、本発明の一実施例の構成図である。
一点鎖線で囲む部分は図2に示す従来例と同一構成であ
り、対応する部分には同一符号を付し、説明を省略す
る。図1において、点線で囲む部分が本発明の主要部を
構成する回路である。上記PLL選局回路7のロック信
号出力端子12とアース間には、抵抗R5とコンデンサ
C1の並列回路を接続し、上記ロック信号出力端子12
とエミッタが接地されたトランジスタQ2のベース間に
は抵抗R4を接続する。1 is a block diagram of an embodiment of the present invention.
The portion surrounded by the alternate long and short dash line has the same configuration as that of the conventional example shown in FIG. 2, and the corresponding portions are designated by the same reference numerals and the description thereof is omitted. In FIG. 1, a portion surrounded by a dotted line is a circuit forming a main part of the present invention. A parallel circuit of a resistor R 5 and a capacitor C 1 is connected between the lock signal output terminal 12 of the PLL tuning circuit 7 and the ground, and the lock signal output terminal 12 is connected.
A resistor R 4 is connected between the base of a transistor Q 2 whose emitter is grounded.
【0013】また、上記トランジスタQ2のコレクタと
トランジスタQ1のベース間には抵抗R2を接続し、上記
トランジスタQ1のコレクタとアース間には抵抗R3を接
続し、上記トランジスタQ1のベース、エミッタ間には
抵抗R1を接続し、更に上記トランジスタQ1のエミッタ
は、上記AGC電圧13が供給される高周波増幅回路2
の制御端子に接続する。Further, the transistor Q is between second collector and the transistor Q 1 based connecting a resistor R 2, Between the collector and ground the transistor Q 1 is connected to resistor R 3, the transistor Q 1 A resistor R 1 is connected between the base and the emitter, and the emitter of the transistor Q 1 is supplied with the AGC voltage 13 to the high frequency amplifier circuit 2
Connect to the control terminal of.
【0014】PLL選局回路7のロック信号出力端子1
2から導出されるロック出力信号は、PLL選局回路7
が選局動作期間中”H”となり、トランジスタQ2をオ
ンにして、AGC電圧14が供給されるAGCラインか
ら抵抗R1,R2を介して、トランジスタQ2に電流が流
れる。この時、抵抗R1、R2で分圧される電圧により、
トランジスタQ1のベースにバイアス電圧が印加され、
上記AGCラインからトランジスタQ1、抵抗R3を介し
て電流が流れる。Lock signal output terminal 1 of PLL tuning circuit 7
The lock output signal derived from 2 is the PLL tuning circuit 7
There becomes "H" in channel selection period, and turns on transistor Q 2, via the AGC line resistance R 1, R 2 which AGC voltage 14 is supplied, a current flows through the transistor Q 2. At this time, due to the voltage divided by the resistors R 1 and R 2 ,
A bias voltage is applied to the base of the transistor Q 1 ,
A current flows from the AGC line through the transistor Q 1 and the resistor R 3 .
【0015】その結果、AGCラインのインピーダンス
Z0と抵抗R3によって分圧されたAGC電圧が高周波増
幅回路2に印加され、該高周波増幅回路2の増幅度(利
得)を下げるように働く。上記高周波増幅回路2の増幅
度の下げ幅は、上記AGCラインのインピーダンスZ0
と抵抗R3の比によって決めることができる。As a result, the AGC voltage divided by the impedance Z 0 of the AGC line and the resistor R 3 is applied to the high frequency amplification circuit 2 and acts to reduce the amplification degree (gain) of the high frequency amplification circuit 2. The reduction degree of the amplification factor of the high frequency amplifier circuit 2 is determined by the impedance Z 0 of the AGC line.
And the resistance R 3 can be determined.
【0016】上記PLL選局回路7のロック信号出力端
子12に接続された抵抗R5とコンデンサC1との並列回
路は、選局が終了し、ロック出力信号が”L”になった
後も一定の時間、トランジスタQ2のスイッチング動作
を継続させるためのものであり、必要に応じて付加すれ
ば良い。The parallel circuit of the resistor R 5 and the capacitor C 1 connected to the lock signal output terminal 12 of the PLL channel selection circuit 7 continues even after the channel selection is completed and the lock output signal becomes "L". This is for continuing the switching operation of the transistor Q 2 for a certain period of time, and may be added as necessary.
【0017】[0017]
【発明の効果】本発明は上記の構成であるので、アンテ
ナ入力として強入力信号を受信した場合でも高周波増幅
回路の飽和を防止し、スプリアスの発生を抑制して、P
LL選局回路の誤動作を防止することができ、信頼性の
高い電子チューナを提供することができる。Since the present invention has the above-mentioned structure, even when a strong input signal is received as an antenna input, the high frequency amplifier circuit is prevented from being saturated and spurious is suppressed from occurring.
A malfunction of the LL tuning circuit can be prevented, and a highly reliable electronic tuner can be provided.
【図1】 本発明の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.
【図2】 従来例の構成図である。FIG. 2 is a configuration diagram of a conventional example.
2・・・・・高周波増幅回路 4・・・・・混合回路 6・・・・・局部発振回路 7・・・・・PLL選局回路 12・・・・・ロック信号出力端子 14・・・・・AGC電圧 Q1,Q2・・・・・トランジスタ R3・・・・・抵抗2 ... High frequency amplifier circuit 4 ... Mixing circuit 6 ... Local oscillation circuit 7 ... PLL tuning circuit 12 ... Lock signal output terminal 14 ... ·· AGC voltage Q 1, Q 2 ····· transistor R 3 ····· resistance
─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───
【手続補正書】[Procedure amendment]
【提出日】平成4年11月9日[Submission date] November 9, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図1[Name of item to be corrected] Figure 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図1】 [Figure 1]
【手続補正2】[Procedure Amendment 2]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図2[Name of item to be corrected] Figure 2
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図2】 [Fig. 2]
Claims (1)
合回路と、PLL選局回路とを備えた電子チューナにお
いて、上記PLL選局回路の選局動作期間中、上記高周
波増幅回路の利得を下げる利得調整回路を設け、アンテ
ナからの強入力信号に対する上記PLL選局回路の誤動
作を防止するようにしたことを特徴とする電子チュー
ナ。1. An electronic tuner comprising a high frequency amplifier circuit, a local oscillator circuit, a mixing circuit, and a PLL tuning circuit, wherein the gain of the high frequency amplifier circuit is adjusted during a tuning operation of the PLL tuning circuit. An electronic tuner characterized in that a gain adjusting circuit for lowering is provided so as to prevent a malfunction of the PLL tuning circuit with respect to a strong input signal from an antenna.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15811292A JPH066177A (en) | 1992-06-17 | 1992-06-17 | Electronic tuner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15811292A JPH066177A (en) | 1992-06-17 | 1992-06-17 | Electronic tuner |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH066177A true JPH066177A (en) | 1994-01-14 |
Family
ID=15664570
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15811292A Pending JPH066177A (en) | 1992-06-17 | 1992-06-17 | Electronic tuner |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH066177A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6725850B2 (en) | 2002-01-31 | 2004-04-27 | Fuji Jukogyo Kabushiki Kaisha | Gas-liquid separation device in a vibrator engine |
KR100746976B1 (en) * | 2001-05-17 | 2007-08-07 | 엘지이노텍 주식회사 | Apparatus for receiving multimedia signal |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04150419A (en) * | 1990-10-12 | 1992-05-22 | Matsushita Electric Ind Co Ltd | Electronic tuner device |
-
1992
- 1992-06-17 JP JP15811292A patent/JPH066177A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04150419A (en) * | 1990-10-12 | 1992-05-22 | Matsushita Electric Ind Co Ltd | Electronic tuner device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100746976B1 (en) * | 2001-05-17 | 2007-08-07 | 엘지이노텍 주식회사 | Apparatus for receiving multimedia signal |
US6725850B2 (en) | 2002-01-31 | 2004-04-27 | Fuji Jukogyo Kabushiki Kaisha | Gas-liquid separation device in a vibrator engine |
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