JPH065714B2 - Semiconductor memory cell - Google Patents
Semiconductor memory cellInfo
- Publication number
- JPH065714B2 JPH065714B2 JP58136130A JP13613083A JPH065714B2 JP H065714 B2 JPH065714 B2 JP H065714B2 JP 58136130 A JP58136130 A JP 58136130A JP 13613083 A JP13613083 A JP 13613083A JP H065714 B2 JPH065714 B2 JP H065714B2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- electrode
- gate electrode
- current
- potential
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Description
【発明の詳細な説明】 本発明は、小型化してもアルファ粒子などの放射粒子に
よって引き起されるソフトエラーの発生が少ないスタテ
ィック型半導体メモリセルに関するものである。The present invention relates to a static semiconductor memory cell in which soft errors caused by radiating particles such as alpha particles are less likely to occur even when miniaturized.
アルファ粒子などの放射性粒子が半導体内に入射する
と、半導体内部には多量の電荷が生成される。これらの
電荷が半導体メモリセル内部の電極に流入すると、その
電極の電位を変化させ、その結果ソフトエラーを起す。
半導体メモリセル内の電極が取り扱う電荷量が大きい時
は、このような内部生成電荷の流入の影響は小さく、こ
のメモリセルがソフトエラーを起こすことは少ない。し
かし半導体メモリセルが小型化されると、メモリセル内
電極の取り扱う電荷量が減少するため、ソフトエラーの
問題が重大となる。When radioactive particles such as alpha particles enter a semiconductor, a large amount of charges are generated inside the semiconductor. When these charges flow into the electrode inside the semiconductor memory cell, the potential of the electrode is changed, resulting in a soft error.
When the amount of charges handled by the electrodes in the semiconductor memory cell is large, the influence of such inflow of internally generated charges is small, and this memory cell rarely causes a soft error. However, when the semiconductor memory cell is miniaturized, the amount of charge handled by the electrodes in the memory cell is reduced, and the problem of soft error becomes serious.
従来の半導体メモリセルでは、メモリセル内電極の構造
を改良し、放射性粒子によって生成される電荷のこの電
極への流入を少なくすること、この電極の取り扱う電荷
量を流入電荷量以上に保つこと、によってソフトエラー
を防いでいた。しかしメモリセル内電極へ流入する電荷
量を減らすことには限界があるため、その電極で取り扱
う電荷量をある値以上に保たなければならない。そのた
め従来の半導体メモリセルではその大きさも、その消費
電力もある値以上に保たなければならなかった。In the conventional semiconductor memory cell, the structure of the electrode in the memory cell is improved to reduce the inflow of charges generated by radioactive particles into this electrode, and the amount of charge handled by this electrode is kept above the amount of inflow charges. Was preventing a soft error. However, since there is a limit to reducing the amount of charge flowing into the electrode in the memory cell, it is necessary to keep the amount of charge handled by the electrode above a certain value. Therefore, in the conventional semiconductor memory cell, its size and its power consumption have to be kept above a certain value.
このことはこの半導体メモリセルの小型化およびこの半
導体メモリセルを使ったメモリ装置の集積化にとって大
きな障害となっていた。This has been a major obstacle to miniaturization of this semiconductor memory cell and integration of a memory device using this semiconductor memory cell.
本願発明の目的はアルファ粒子などの放射性粒子によっ
て引き起されるソフトエラーの発生が極めて少なく、ソ
フトエラー対策のために小型化、集積化が制限されるこ
との少ない半導体メモリセルを提供することである。An object of the present invention is to provide a semiconductor memory cell in which the occurrence of soft errors caused by radioactive particles such as alpha particles is extremely small, and miniaturization and integration are not limited as a countermeasure against soft errors. is there.
本発明による半導体メモリセルは、第１の電源に接続さ
れた第１通電電極、第２通電電極、ゲート電極を有する
第１導電型の第１FETと、 第１FETの第１通電電極に接続された第１通電電極、第
１FETのゲート電極に接続された第２通電電極、第１FET
の第２通電電極に接続されたゲート電極を有する第１導
電型の第２FETとを有し、しかも第１、第２FETの第２通
電電極に隣接する半導体領域を第１の電源に接続された
反対導電型領域とし、第１の電源より低電位の第２の電
源に接続された第１通電電極、第２通電電極、ゲート電
極を有する第２導電型の第３FETと、 第３FETの第１通電電極に接続された第１通電電極、第
３FETのゲート電極に接続された第２通電電極、第３FET
の第２通電電極に接続されたゲート電極を有する第２導
電型の第４FETとを有し、しかも第３、第４FETの第２通
電電極に隣接する半導体領域を第２の電源に接続された
反対導電型領域とし、 第１FETの第２通電電極と第３FETの第２通電電極の間に
接続された第１ダイオードと、 第２FETの第２通電電極と第４FETの第２通電電極の間に
接続された第２ダイオードと、第１FETのゲート電極と
第２FETのゲート電極の間に接続された ｛Ｃ０１・｜ΔＶ｜−｜Ｉ１−ＩＤ｜・Δｔα｝／Ｃ１
＞ＶＴＨ を満たす容量値Ｃ０１の第１の容量と、 第３FETのゲート電極と第４FETのゲート電極の間に接続
された、 ｛Ｃ０１・｜ΔＶ｜−｜Ｉ１−ＩＤ｜・Δｔα｝／Ｃ２
＞ＶＴＨ を満たす容量値Ｃ０２の第２の容量を備えたことを特徴
とする。ただしΔＶ：アルファ粒子等の影響による容量
の一方の端子の電位変化、Δｔα：アルファ粒子等によ
る生成電流のうちの無視できない初期の大電流流入時
間、Ｉ１，Ｉ２，ＩＤ：それぞれΔｔαの間に第１導電
型FET、第２導電型FET、ダイオードに流れる電流、
Ｃ１，Ｃ２：それぞれ第１、第２の容量の他方の端子に
接続される全容量のうち大きい方、ＶＴＨ：ダイオード
のしきい値電圧である。A semiconductor memory cell according to the present invention is connected to a first conductive type first FET having a first conducting electrode, a second conducting electrode and a gate electrode connected to a first power source, and a first conducting electrode of the first FET. First conducting electrode, second conducting electrode connected to the gate electrode of the first FET, first FET
A second FET of a first conductivity type having a gate electrode connected to the second current-carrying electrode, and a semiconductor region adjacent to the second current-carrying electrodes of the first and second FETs is connected to the first power supply. A second conductive type third FET having a first conductive electrode, a second conductive electrode, and a gate electrode, which are regions of opposite conductivity type and are connected to a second power source having a lower potential than the first power source, and a first FET of the third FET. A first conducting electrode connected to the conducting electrode, a second conducting electrode connected to the gate electrode of the third FET, a third FET
A fourth FET of a second conductivity type having a gate electrode connected to the second current-carrying electrode, and a semiconductor region adjacent to the second current-carrying electrodes of the third and fourth FETs is connected to a second power source. Between the second conducting electrode of the first FET and the second conducting electrode of the second FET, and the first diode connected between the second conducting electrode of the first FET and the second conducting electrode of the third FET in the opposite conductivity type region. Connected second diode and {C 01 · | ΔV | − | I 1 −I D | · Δt α } / C 1 connected between the gate electrode of the first FET and the gate electrode of the second FET.
> V a first capacitor of capacitance value C 01 satisfying TH, connected between the gate electrode of the gate electrode of the 3FET second 4FET, {C 01 · | ΔV | - | I 1 -I D | · Δt α } / C 2
A second capacitance having a capacitance value C 02 satisfying> V TH is provided. However, ΔV: potential change at one terminal of the capacitance due to the influence of alpha particles, etc., Δt α : initial large current inflow time that cannot be ignored among the generated currents due to alpha particles, I 1 , I 2 , I D : each Δt The current flowing through the first conductivity type FET, the second conductivity type FET, and the diode during α ,
C 1 and C 2 are the larger ones of the total capacitances connected to the other terminals of the first and second capacitances, respectively, and V TH is the threshold voltage of the diode.
次に図を参照しながら、本発明の半導体メモリセルの動
作原理および効果を説明する。第１図は本発明のメモリ
セルをMOSFETとシリコン接合ダイオード等を用いて構成
した一例を示している。この図の101，102はＰ型チャネ
ルMOSFET，103，104はＮ型チャネルMOSFET，105，106は
順方向に接続されたシリコン接合ダイオード、107，108
は選択ゲートとして使用されるＮ型チャネルMOSFET，10
9，110は電源線、111，112はワード線、113，114はビッ
ト線、115，116は容量をそれぞれを示す。この図の例で
は、Ｎ型チャネルMOSFET103，104，107，108の閥値電圧
は1V、Ｐ型チャネルMOSFET101，102の閥値電圧は−1Vと
仮定する。さらに電源線109，110にはそれぞれ5V，0Vの
一定電位が供給されており、シリコン接合ダイオード10
5，106は第２図に示されるようにしきい値電圧が約0.7V
の順方向電流−電圧特性をもつものと仮定する。Next, the operating principle and effect of the semiconductor memory cell of the present invention will be described with reference to the drawings. FIG. 1 shows an example in which the memory cell of the present invention is constructed by using a MOSFET and a silicon junction diode. In this figure, 101 and 102 are P-type channel MOSFETs, 103 and 104 are N-type channel MOSFETs, 105 and 106 are forward-connected silicon junction diodes, 107 and 108.
Is an N-type channel MOSFET used as a select gate, 10
Reference numerals 9 and 110 represent power supply lines, 111 and 112 represent word lines, 113 and 114 represent bit lines, and 115 and 116 represent capacitors. In the example of this figure, it is assumed that the N-channel MOSFETs 103, 104, 107 and 108 have a threshold voltage of 1V and the P-channel MOSFETs 101 and 102 have a threshold voltage of -1V. Further, the power supply lines 109 and 110 are supplied with constant potentials of 5 V and 0 V, respectively, and the silicon junction diode 10
5,106 has a threshold voltage of about 0.7V as shown in Fig.2.
It is assumed that the forward current-voltage characteristics of
今は、Ｎ型チャネルMOSFET107，108はオフ状態で節点N2
の電位と節点N4がそれぞれ5V，4.3Vの場合を考える。こ
のときＮ型チャネルMOSFET103はオン、Ｐ型チャネルMOS
FET103はオン、Ｐ型チャネルMOSFET101はオフ状態にあ
る。そのため節点N3の電位はすみやかに0Vとなり、節点
N1の電位はすみやかに0.7Vぐらいになる。Now, the N-type channel MOSFETs 107 and 108 are in the off state and the node N2
Let us consider the case where the potential and the node N4 are 5V and 4.3V, respectively. At this time, the N-type channel MOSFET 103 is turned on and the P-type channel MOS
The FET 103 is on and the P-type channel MOSFET 101 is off. Therefore, the potential of node N3 quickly becomes 0V,
The potential of N1 quickly becomes about 0.7V.
その結果、Ｐ型チャネルMOSFET102はオン、Ｎ型チャネ
ルMOSFET104はオフ状態になり、そのため、節点N2の電
位は5V、節点N4の電位は4.3Vに保持される。As a result, the P-type channel MOSFET 102 is turned on and the N-type channel MOSFET 104 is turned off, so that the potential of the node N2 is maintained at 5V and the potential of the node N4 is maintained at 4.3V.
このようにして節点N2，N4が高電位、節点N1，N2が低電
位の状態は安定であり、いつまでも保持される。In this way, the state in which the nodes N2 and N4 are at high potential and the nodes N1 and N2 are at low potential is stable and held forever.
また本メモリセルが対称であることから容易にわかるよ
うに、節点N1，N3が高電位で節点N2，N4が低電位という
逆の状態も同様に安定できる。本メモリセルはこの２つ
の安定状態を２進情報に対応させてメモリセルとして機
能する。Further, as can be easily understood from the fact that this memory cell is symmetrical, the reverse state in which the nodes N1 and N3 are at high potential and the nodes N2 and N4 are at low potential can be similarly stabilized. The present memory cell functions as a memory cell by relating these two stable states to binary information.
書き込み読み出し動作はワード線111，112を高電位に
し、Ｎ型チャネルMOSFET107，108をオン状態にし、ビッ
チ線113，114を通して行なわれる。Writing and reading operations are performed through the bit lines 113 and 114 with the word lines 111 and 112 set to a high potential, the N-type channel MOSFETs 107 and 108 turned on.
アルファ粒子等の放射性粒子の入射によって半導体内に
生成された電荷がこの半導体内部の電極に流入すると、
該電極の電位は、該電極とその周囲の半導体との間の電
位差を減らす方向に変化する。よってもともと半導体内
部電極とその周囲半導体とが同電位の場合には、該電極
電位はアルファ粒子の影響を受けない。When the charge generated in the semiconductor by the incidence of radioactive particles such as alpha particles flows into the electrode inside this semiconductor,
The potential of the electrode changes so as to reduce the potential difference between the electrode and the semiconductor around it. Therefore, if the semiconductor internal electrode and the surrounding semiconductor are originally at the same potential, the electrode potential is not affected by the alpha particles.
第１図のメモリセルの例では、節点N1，N2を構成する半
導体領域をＰ型半導体に限り、それに隣接する半導体領
域を5Vの電位に保たれたＮ型半導体に限ることができ
る。何故ならば、節点N1，N2はＰ型チャネルMOSFETのソ
ースドレイン領域とシリコン接合ダイオードのＰ側領域
に接続されているが、これらの領域は通常Ｐ型半導体で
あり、さらに、CMOS構造を採用しているならば、これら
の領域は5V電位の供給されたＮウェルと呼ばれるＮ型半
導体内に形成されるからである。同様に節点N3，N4を構
成する半導体領域をＮ型半導体に限り、それに隣接する
半導体領域を0Vの電位に保たれたＰ型半導体に限ること
ができる。In the example of the memory cell of FIG. 1, the semiconductor regions forming the nodes N1 and N2 can be limited to P-type semiconductors, and the semiconductor regions adjacent thereto can be limited to N-type semiconductors kept at the potential of 5V. Because the nodes N1 and N2 are connected to the source / drain region of the P-type channel MOSFET and the P-side region of the silicon junction diode, these regions are usually P-type semiconductors, and the CMOS structure is adopted. If so, these regions are formed in an N-type semiconductor called an N well supplied with a 5V potential. Similarly, the semiconductor regions forming the nodes N3 and N4 can be limited to N-type semiconductors, and the semiconductor regions adjacent thereto can be limited to P-type semiconductors maintained at the potential of 0V.
節点N2，N4が高電位、節点N1，N3が低電位である状態で
α粒子等の放射性粒子が入射した場合を考える。節点N
2，N3の電位は周囲の半導体領域と同電位であるから、
上記の理由により、ここにα粒子等が入射しても本メモ
リセルの状態が壊されることはない。尚、α粒子等の入
射が２つ以上の節点に同時に影響を及ぼす可能性は極め
て低いため、ここでは考えないことにする。Consider a case where radioactive particles such as α particles are incident with the nodes N2 and N4 at high potential and the nodes N1 and N3 at low potential. Node N
Since the potential of 2, N3 is the same as that of the surrounding semiconductor region,
For the above reason, the state of the memory cell is not destroyed even if α particles or the like are incident on it. Since it is extremely unlikely that the incidence of α particles or the like will affect two or more nodes at the same time, it will not be considered here.
次に、この状態で、α粒子等が節点N1に入射した場合を
考える。この場合、節点N1を構成するＰ型半導体領域に
はα粒子等によって生成されたホールが流入し、その電
位が上昇する。この電位上昇量ΔＶＮ１は、流入するホ
ールの電荷量をＱ、節点N1につながる全容量をＣＮとす
れば、ΔＶＮ１＝Q/CNで与えられる。ＣＮが大きく、Δ
ＶＮ１が初期の節点N1とN2の大小関係を反転させる程大
きくなければ、ソフトエラーは起きない。このことは、
本発明の半導体メモリセル固有の効果がない、従来の半
導体メモリセルに対してもいえる。ところが、ＣＮが小
さく、ΔＶＮ１が例えば節点N1とN2の初期の電位差(4.3
V)以上になる場合は、節点N1とN2の大小関係が反転し、
ソフトエラーが起こる可能性がある。各種のノイズや特
性バラツキなどの不安定要素があれば、ΔＶＮ１がもっ
と小さくてもソフトエラーが起こる可能がある。ところ
が本発明の半導体メモリセルでは以下に説明するように
ソフトエラーを回避することができる。Next, in this state, consider the case where an α particle or the like is incident on the node N1. In this case, holes generated by α particles or the like flow into the P-type semiconductor region forming the node N1, and the potential thereof rises. The potential increase amount ΔV N1 is given by ΔV N1 = Q / C N, where Q is the charge amount of the inflowing holes and C N is the total capacitance connected to the node N1. C N is large, Δ
If V N1 is not large enough to reverse the magnitude relationship between the initial nodes N1 and N2, no soft error occurs. This is
The same can be said for the conventional semiconductor memory cell which does not have the effect peculiar to the semiconductor memory cell of the present invention. However, C N is small, and ΔV N1 is, for example, the initial potential difference between the nodes N1 and N2 (4.3
V) and above, the magnitude relationship between nodes N1 and N2 is reversed,
Soft errors can occur. If there are unstable elements such as various noises and characteristic variations, a soft error may occur even if ΔV N1 is smaller. However, in the semiconductor memory cell of the present invention, soft error can be avoided as described below.
小型化した半導体メモリセルでは、ますますＣＮが小さ
くなり、その分ΔＶＮ１は大きくなる。その値は5V以上
にもなる。今、ΔＶＮ１が5V以上の場合を考えてみる。
この場合、節点N1の電位は5.7V以上になるが、節点N1を
構成するＰ型半導体の周囲には5V電位のＮ型半導体があ
るため、そのPN接合に順方向電流が流れ、その電位は5.
7V位以上には上昇しない。すなわち、α粒子等が入射し
た後の節点N1の電位としては高々5.7V，ΔＶＮ１として
は5Vを想定すればよい。In a miniaturized semiconductor memory cell, C N becomes smaller and ΔV N1 becomes larger accordingly. Its value is more than 5V. Now, consider the case where ΔV N1 is 5 V or more.
In this case, the potential of the node N1 becomes 5.7V or more, but since there is an N-type semiconductor of 5V potential around the P-type semiconductor forming the node N1, a forward current flows through the PN junction and its potential is Five.
It does not rise above 7V. That is, the potential of the node N1 after the incidence of the α particles and the like is assumed to be 5.7 V at most and ΔV N1 is 5 V.
このようにして節点N1の電位が5.7Vになると、ダイオー
ド105を通して電流が流れ、節点N3の電位はすみやかに
5.0Vぐらいまで上昇する。さらにN2，N4の電位も、N1，
N3の電位変化の影響を容量115，116を通して受け、上昇
する。簡単のため、容量115，116の値はともにＣ０、節
点N2，N4につながる全容量の値がともにＣＮの場合を想
定すると、節点N2，N4の電位変化はそれぞれ (1) (C0・ΔVN1-I106・Δtα)/CN (2) {C0・ΔVN3-(I104-I106)・Δtα}/CN となる。なお、ここでΔＶＮ１，ΔＶＮ３はそれぞれα
粒子等の入射の影響による節点N1とN3の電位変化で ΔＶＮ１ΔＶＮ３（5V） であり、Δｔαはα粒子等生成電流のうち無視できない
初期の大電流流入時間、Ｉ１０６，Ｉ１０４はそれぞれ
Δｔαの間のダイオード106およびMOSFET104を流れる電
流である。そのため、Ｃ０を適当に大きく、Ｉ１０４，
Ｉ１０６を小さくする設計（例えばMOSFETのゲート長を
長くする、ゲート幅を狭くする、ゲート酸化膜厚を厚く
する等）を行なえば、上記節点N2，N4の電位変化量を0.
7V以上に出来る。そして、α粒子等入射後Δtα経過後
には節点N4の電位は節点N3の電位5Vよりも高くできる。In this way, when the potential of the node N1 becomes 5.7V, a current flows through the diode 105, and the potential of the node N3 promptly changes.
It rises to about 5.0V. Furthermore, the potentials of N2 and N4 are
It is affected by the potential change of N3 through the capacitors 115 and 116 and rises. For the sake of simplicity, assuming that the capacitances 115 and 116 are both C 0 and the total capacitances connected to the nodes N2 and N4 are both C N , the potential changes at the nodes N2 and N4 are (1) (C 0・ ΔV N1 -I 106・ Δt α ) / C N (2) {C 0・ ΔV N3- (I 104 -I 106 ) ・ Δt α } / C N Here, ΔV N1 and ΔV N3 are α
The potential change of the nodes N1 and N3 due to the influence of the incidence of particles is ΔV N1 ΔV N3 (5V), and Δt α is the initial large current inflow time that cannot be ignored among the α particle generation currents, and I 106 and I 104 are The current flowing through the diode 106 and the MOSFET 104 during Δt α , respectively. Therefore, C 0 is appropriately increased to I 104 ,
By designing I 106 to be small (for example, increasing the gate length of the MOSFET, narrowing the gate width, increasing the thickness of the gate oxide film, etc.), the potential change amount at the nodes N2 and N4 can be reduced to 0.
Can be more than 7V. The potential at the node N4 can be higher than the potential 5V at the node N3 after a lapse of Δt α after the incidence of α particles or the like.
例えばC0/CN＝0.5，ΔVN3＝5V，(I104-I106)Δtα)/CN
＝1Vの場合を考える。この時、第(2)式の値は1.5Vであ
るから、節点N4の初期電位が4.3Vならば、その値は5.8V
まで上昇することになる。この時節点N2の電位は、節点
N1同様にPN接合の順方向バイアスにより、高々5.7Vまで
しか上昇しない。しかし、Ｎ型半導体に限られている節
点N4の電位は、PN接合が逆方向バイアスされることにな
り、5.8Vまで上昇できる。C0/CN＝0.5はC0の設計次第で
可能な値である。(I104-I106)Δtα)/CNの値は、Δtα
がナノ秒オーダと小さいことから、大きくならない。For example, C 0 / C N = 0.5, ΔV N3 = 5V, (I 104 -I 106 ) Δt α ) / C N
Consider the case of = 1V. At this time, the value of the equation (2) is 1.5V, so if the initial potential of the node N4 is 4.3V, the value is 5.8V.
Will rise to. At this time, the potential of the node N2 is
Like N1, due to the forward bias of the PN junction, the voltage rises only up to 5.7V. However, the potential at the node N4, which is limited to N-type semiconductors, can rise to 5.8V because the PN junction is reverse-biased. C 0 / C N = 0.5 is a possible value depending on the design of C 0 . The value of (I 104 -I 106 ) Δt α ) / C N is Δt α
Does not grow because it is on the order of nanoseconds.
上記の例の場合、α粒子等の入射等の節点N1，N2，N3，
N4の電位はそれぞれ5.7V，5.7V，5V，5.8Vであった。こ
こで重要なことは節点N3の電位よりもN4のそれの方が大
きくなることである。比C0/CNが小さい場合にはその大
小関係が逆転する場合がある。例えばC0/CN＝0.1の場
合、第(2)式の値は−0.5Vとなり、α粒子等の入射後の
節点N3，N4の電位はそれぞれ5V，4.5Vになってしまう。
この場合には以下に述べるような効果は得られず、ソフ
トエラーが起こる。そのため、本発明のメモリセルで
は、第(2)式の値がダイオードのしきい値電圧より大き
くなるよう比C0/CNをある程度大きくする必要がある。In the case of the above example, the nodes N1, N2, N3, such as the incidence of α particles, etc.
The potentials of N4 were 5.7V, 5.7V, 5V and 5.8V, respectively. What is important here is that the potential of N4 is larger than that of node N3. When the ratio C 0 / C N is small, the magnitude relation may be reversed. For example, when C 0 / C N = 0.1, the value of the equation (2) becomes −0.5V, and the potentials of the nodes N3 and N4 after incidence of α particles and the like become 5V and 4.5V, respectively.
In this case, the effects described below cannot be obtained, and a soft error occurs. Therefore, in the memory cell of the present invention, it is necessary to increase the ratio C 0 / C N to some extent so that the value of the equation (2) becomes larger than the threshold voltage of the diode.
α粒子等入射の影響が無視できるようになった時、各節
点の電位は5V以上であるから、Ｐ型チャネルMOSFET10
1，102はオフ、Ｎ型チャネルMOSFET103，104はオンであ
り、節点N4の電位は節点N3の電位よりも高い状態とな
る。When the influence of incident α particles becomes negligible, the potential of each node is 5V or more.
Since 1 and 102 are off and N-type channel MOSFETs 103 and 104 are on, the potential of the node N4 is higher than the potential of the node N3.
そのため、節点N3，N4の電位差はMOSFET103，104で構成
される作動増幅器によって増幅されることになる。Therefore, the potential difference between the nodes N3 and N4 is amplified by the operational amplifier composed of the MOSFETs 103 and 104.
すなわち節点N3の電位はN4よりも低いため下がり、0Vと
なり、節点N4の電位は節点N3そしてN1の電位低下によっ
てMOSFET102がオンするため、高電位に引き上げられ
る。That is, since the potential of the node N3 is lower than that of N4, it drops to 0 V, and the potential of the node N4 is pulled up to a high potential because the MOSFET 102 is turned on by the potential drop of the nodes N3 and N1.
このようにして節点N1にα粒子等の放射性粒子が入射し
ても、本メモリセルの状態が壊されることはない。この
ことは節点N4にα粒子等が入射した場合にも、本メモリ
セルがもう一方の状態、すなわち節点N1，N3が高電位で
節点N2，N4が低電位の状態、の場合にも全く同様に成立
する。In this way, even if radioactive particles such as α particles enter the node N1, the state of the memory cell is not destroyed. This is exactly the same even when an α particle or the like is incident on the node N4, when the memory cell is in the other state, that is, when the nodes N1 and N3 are at high potential and the nodes N2 and N4 are at low potential. Holds.
但し、容量115，116と各節点の容量の比と各MOSFETのチ
ャネル電流は上記第(2)式をダイオードのしきい値電圧
より大きくすることに相当する条件つまり｛C0・ΔVN4-
(I103-I105)・Δtα}/CN＞0.7を満たすように設計されな
ければならない。このように設計されれば、本メモリセ
ルはα粒子等の入射によって記憶状態が壊されることの
少ないメモリセルとなる。However, the ratio of the capacitances 115 and 116 to the capacitance at each node and the channel current of each MOSFET are the conditions equivalent to making the above expression (2) larger than the threshold voltage of the diode, that is, {C 0 · ΔV N4-
It must be designed so that (I 103 -I 105 ) Δt α } / C N > 0.7. If designed in this way, the present memory cell becomes a memory cell whose storage state is less likely to be destroyed by the incidence of α particles or the like.
以上説明したように、本発明のメモリセルでは容量比C0
/CNをある程度大きくすることが重要であり、その下限
は各MOSFETのチャネル電流などで決まる。上記実施例の
場合、第(2)式からも明らかなように、C0/CN>0.34であ
れば効果が得られた。ここで容量CNはCOも含む各節点の
全容量であり、上記実施例では簡単のため、それらは４
節点とも同じ値と仮定して議論した。しかし、実際は各
節点の容量が多少異なり、それら異なるCNi(i=1,……,
4)に対して、C0／CNが第(2)式の値をＶＴＨより大きく
することに相当する条件を満たすことが必要である。と
ころが一般に、ＣＮｉ値は各節点で異なるとしても大き
く異なることはなく、各MOSFETのチャネル電流もそうで
ある。よってＣ０をある程度大きくすれば、各節点に対
して第(2)式の値をＶＴＨより大きくすることに相当す
る条件を満たすことは可能である。また、上記の実施例
のようにC0/CN>0.34とすることは困難な要求ではない。
よって、本発明のメモリセルは実現可能である。As described above, in the memory cell of the present invention, the capacitance ratio C 0
It is important to increase / CN to some extent, and the lower limit is determined by the channel current of each MOSFET. In the case of the above embodiment, as is clear from the equation (2), the effect was obtained if C 0 / C N > 0.34. Here, the capacity C N is the total capacity of each node including C O , and since it is simple in the above embodiment, they are 4
The discussion was made on the assumption that the nodes have the same value. However, in reality, the capacity of each node is slightly different, and these different C Ni (i = 1, ...,
In contrast to 4), it is necessary that C 0 / C N satisfy the condition corresponding to making the value of the equation (2) larger than V TH . However, in general, the C Ni value does not vary greatly even if it differs at each node, and so does the channel current of each MOSFET. Therefore, if C 0 is increased to some extent, it is possible to satisfy the condition corresponding to making the value of the equation (2) larger than V TH for each node. Further, it is not a difficult requirement to set C 0 / C N > 0.34 as in the above embodiment.
Therefore, the memory cell of the present invention can be realized.
本メモリセルの動作を説明するため、第１図の実施例で
はダイオードとしてシリコン接合ダイオードを用いた
が、本発明はこれに限る必要はない。第２図にその特性
を示すように、順方向電流が顕著に流れはじめるしきい
値電圧があれば他のダイオードであっても構わない。例
えばガリウム砒素接合ダイオードでも構わないし、２つ
以上のシリコン接合ダイオードを並列または直列につな
いだものでも構わないし、第３図にその実施例を示すよ
うにMOSFETの一方の通電電極とゲート電極を併合させた
ダイオードでも構わない。例えばショットキ接合ダイオ
ードを使えば、従来のCMOSスタティックメモリセルで金
属−シリコンオーム性コンタクト部をシヨットキコンタ
クトに変えるだけで済み、面積の点でも有利である。In order to explain the operation of this memory cell, a silicon junction diode is used as the diode in the embodiment of FIG. 1, but the present invention is not limited to this. As shown in the characteristics of FIG. 2, another diode may be used as long as it has a threshold voltage at which a forward current begins to flow remarkably. For example, a gallium arsenide junction diode may be used, or two or more silicon junction diodes may be connected in parallel or in series. As shown in the embodiment of FIG. It may be a diode. For example, if a Schottky junction diode is used, it is only necessary to change the metal-silicon ohmic contact portion to a Schottky contact in the conventional CMOS static memory cell, which is also advantageous in terms of area.
第３図は本発明のメモリセルの他の実施例を示してい
る。第１図のシリコン接合ダイオード105，106の代り
に、一方の通電電極とゲート電極を併合したＮ型チャネ
ルMOSFETで構成したダイオードが使われている他は第１
図の実施例と同じである。各部を示す番号の１桁目は第
１図のそれと対応している。この実施例ではダイオード
の電流電圧特性を、MOSFETのしきい値電圧やゲイン定数
を変えることにより、自由に変えられる特徴がある。FIG. 3 shows another embodiment of the memory cell of the present invention. Instead of the silicon junction diodes 105 and 106 shown in FIG. 1, a diode composed of an N-type channel MOSFET in which one current-carrying electrode and a gate electrode are combined is used.
This is the same as the illustrated embodiment. The first digit of the number indicating each part corresponds to that of FIG. This embodiment is characterized in that the current-voltage characteristic of the diode can be freely changed by changing the threshold voltage and the gain constant of the MOSFET.
但し第３図の実施例では節点N1′，N2′をＰ型半導体に
限ることができず、α粒子等の入射によってこれらの節
点電位は低から高ばかりでなく高から低へも変化しう
る。However, in the embodiment shown in FIG. 3, the nodes N1 'and N2' cannot be limited to the P-type semiconductor, and these node potentials can change not only from low to high but also from high to low by the incidence of α particles and the like. .
しかし、節点N1′，N2′の電位の高から低への電圧変化
は、MOSFET301，302をオフにし、ダイオード305，306が
逆方向バイアスされるため節点N3′，N4′へは伝わらな
い。そのため、節点N3′，N4′の電位差はα粒子等入射
前のままに保たれ、この場合もソフトエラーは生じな
い。However, the voltage change from the high potential to the low potential of the nodes N1 'and N2' does not reach the nodes N3 'and N4' because the MOSFETs 301 and 302 are turned off and the diodes 305 and 306 are reverse biased. Therefore, the potential difference between the nodes N3 'and N4' is kept as it was before the incidence of α particles and the like, and in this case also, no soft error occurs.
以上本発明の半導体メモリセルの動作を説明するため電
源電圧として0V，5V，PN接合ダイオードの順方向しきい
値電圧0.7Vを使い、第１図の実施例で節点N1を中心に説
明したが、本発明の半導体メモリセルの効果は他の場合
も同様である。In order to explain the operation of the semiconductor memory cell of the present invention, 0V, 5V and the forward threshold voltage of 0.7V of the PN junction diode were used as the power supply voltage, and the description was given centering on the node N1 in the embodiment of FIG. The effects of the semiconductor memory cell of the present invention are the same in other cases.
第１は本発明の半導体メモリセルをMOSFETとシリコン接
合ダイオードを用いて構成した一例を示す回路図。第２
図は第１図で用いたシリコン接合ダイオードの順方向電
流−電圧特性を示す図。第３図は本発明の半導体メモリ
セルの他の実施例を示す回路図。 101，301，102，302……Ｐ型チャネルMOSFET、 103，303，104，304，107，307，108，308……Ｎ型チャ
ネルMOSFET。 105，106……シリコン接合ダイオード、 305，306……一方の通電電極とゲート電極を併合して構
成したダイオード、 109，309，110，310……電源線、 111，311，112，312……ワード線、 113，313，114，314……ビット線、 115，315，116，316……容量。The first is a circuit diagram showing an example in which a semiconductor memory cell of the present invention is configured by using a MOSFET and a silicon junction diode. Second
The figure shows the forward current-voltage characteristics of the silicon junction diode used in FIG. FIG. 3 is a circuit diagram showing another embodiment of the semiconductor memory cell of the present invention. 101, 301, 102, 302 ... P-type channel MOSFET, 103, 303, 104, 304, 107, 307, 108, 308 ... N-type channel MOSFET. 105, 106 ...... Silicon junction diode, 305, 306 ...... Diode formed by combining one current-carrying electrode and gate electrode, 109, 309, 110, 310 ...... Power supply line, 111, 311, 112, 312 …… Word line, 113,313,114,314 ... Bit line, 115,315,116,316 ... Capacity.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 27/10 ４９１ 8728−4Ｍ 6741−5Ｌ Ｇ１１Ｃ 11/34 ３４１ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification number Internal reference number FI Technical indication H01L 27/10 491 8728-4M 6741-5L G11C 11/34 341
Claims (1)
２通電電極、ゲート電極を有する第１導電型の第１FET
と、 第１FETの第１通電電極に接続された第１通電電極、第
１FETのゲート電極に接続された第２通電電極、第１FET
の第２通電電極に接続されたゲート電極を有する第１導
電型の第２FETとを有し、しかも第１、第２FETの第２通
電電極に隣接する半導体領域を第１の電源に接続された
反対導電型領域とし、第１の電源より低電位の第２の電
源に接続された第１通電電極、第２通電電極、ゲート電
極を有する第２導電型の第３FETと、 第３FETの第１通電電極に接続された第１通電電極、第
３FETのゲート電極に接続された第２通電電極、第３FET
の第２通電電極に接続されたゲート電極を有する第２導
電型の第４FETと、を有し、しかも第３、第４FETの第２
通電電極に隣接する半導体領域を第２の電源に接続され
た反対導電型領域とし、 第１FETの第２通電電極と第３FETの第２通電電極の間に
接続された第１ダイオードと、 第２FETの第２通電電極と第４FETの第２通電電極の間に
接続された第２ダイオードと、 第１FETのゲート電極と第２FETのゲート電極の間に接続
された、 ｛Ｃ０１・｜ΔＶ｜−｜Ｉ１−ＩＤ｜・Δｔα｝／Ｃ１
＞ＶＴＨ を満たす容量値Ｃ０１の第１の容量と、第３FETのゲー
ト電極と第４FETのゲート電極の間に接続された、 ｛Ｃ０１・｜ΔＶ｜−｜Ｉ２−ＩＤ｜・Δｔα｝／Ｃ２
＞ＶＴＨ を満たす容量値Ｃ０２の第２の容量を備え（ただしΔ
Ｖ：アルファ粒子等の影響による容量の一方の端子の電
位変化、Δｔα：アルファ粒子等による生成電流のうち
無視できない初期の大電流流入時間、Ｉ１，Ｉ２，
ＩＤ：それぞれΔｔαの間に第１導電型FET、第２導電
型FET、ダイオードに流れる電流、Ｃ１，Ｃ２：それぞ
れ第１、第２の容量の他方の端子に接続される全容量の
うち大きい方、ＶＴＨ：ダイオードのしきい値電圧）た
ことを特徴とする半導体メモリセル。1. A first conductivity type first FET having a first conducting electrode, a second conducting electrode, and a gate electrode connected to a first power source.
A first conducting electrode connected to the first conducting electrode of the first FET, a second conducting electrode connected to the gate electrode of the first FET, and a first FET
A second FET of a first conductivity type having a gate electrode connected to the second current-carrying electrode, and a semiconductor region adjacent to the second current-carrying electrodes of the first and second FETs is connected to the first power supply. A second conductive type third FET having a first conductive electrode, a second conductive electrode, and a gate electrode, which are regions of opposite conductivity type and are connected to a second power source having a lower potential than the first power source, and a first FET of the third FET. A first conducting electrode connected to the conducting electrode, a second conducting electrode connected to the gate electrode of the third FET, a third FET
Second FET of the second conductivity type having a gate electrode connected to the second current-carrying electrode of the third FET, and second FET of the third and fourth FETs.
A semiconductor region adjacent to the current-carrying electrode is a region of opposite conductivity type connected to the second power supply, and a first diode connected between the second current-carrying electrode of the first FET and the second current-carrying electrode of the third FET, and a second FET. A second diode connected between the second conducting electrode of the first FET and the second conducting electrode of the fourth FET, and a second diode connected between the gate electrode of the first FET and the gate electrode of the second FET, {C 01 · | ΔV | − | I 1 -I D | · Δt α} / C 1
> V a first capacitor of capacitance value C 01 satisfying TH, connected between the gate electrode of the gate electrode of the 3FET second 4FET, {C 01 · | ΔV | - | I 2 -I D | · Δt α } / C 2
A second capacitor having a capacitance value C 02 satisfying> V TH is provided (where Δ
V: potential change at one terminal of the capacitance due to the influence of alpha particles, Δt α : initial large current inflow time that cannot be ignored among the generated currents due to alpha particles, I 1 , I 2 ,
I D : current flowing through the first conductivity type FET, second conductivity type FET, diode during each Δt α , C 1 , C 2 : total capacitance connected to the other terminals of the first and second capacitances, respectively The larger of the two, V TH : threshold voltage of the diode), is a semiconductor memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58136130A JPH065714B2 (en) | 1983-07-26 | 1983-07-26 | Semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58136130A JPH065714B2 (en) | 1983-07-26 | 1983-07-26 | Semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6028262A JPS6028262A (en) | 1985-02-13 |
| JPH065714B2 true JPH065714B2 (en) | 1994-01-19 |
Family
ID=15168006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58136130A Expired - Lifetime JPH065714B2 (en) | 1983-07-26 | 1983-07-26 | Semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH065714B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141991A (en) * | 1988-11-21 | 1990-05-31 | Nec Corp | Semiconductor storage circuit and semiconductor memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SE444484B (en) * | 1979-02-26 | 1986-04-14 | Rca Corp | INTEGRATED CIRCUIT CONTAINING INCLUDING A MEMORY CELL WITH A FIRST AND ANOTHER INVERTER |
| JPS55158659A (en) * | 1979-05-30 | 1980-12-10 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor memory storage |
| JPS56107575A (en) * | 1980-01-29 | 1981-08-26 | Nec Corp | Manufacture of semicondutor device |
-
1983
- 1983-07-26 JP JP58136130A patent/JPH065714B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6028262A (en) | 1985-02-13 |
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