JPH06295675A - Manufacture of plasma display panel - Google Patents
Manufacture of plasma display panelInfo
- Publication number
- JPH06295675A JPH06295675A JP5084416A JP8441693A JPH06295675A JP H06295675 A JPH06295675 A JP H06295675A JP 5084416 A JP5084416 A JP 5084416A JP 8441693 A JP8441693 A JP 8441693A JP H06295675 A JPH06295675 A JP H06295675A
- Authority
- JP
- Japan
- Prior art keywords
- partition wall
- substrate
- plasma display
- display panel
- lower electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Gas-Filled Discharge Tubes (AREA)
- Manufacture Of Electron Tubes, Discharge Lamp Vessels, Lead-In Wires, And The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、放電空間を複数の単位
放電空間に分割するストライプ状の隔壁を有するプラズ
マディスプレイパネルの製造方法、特に隔壁の形状をほ
ぼ設計値どうりに形成できるプラズマディスプレイパネ
ルの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a plasma display panel having stripe-shaped barrier ribs for dividing a discharge space into a plurality of unit discharge spaces, and more particularly to a plasma display capable of forming the barrier ribs to have almost the designed values. The present invention relates to a panel manufacturing method.
【０００２】[0002]
【従来の技術】プラズマディスプレイパネル、たとえば
面放電型のプラズマディスプレイパネルは、図１に示す
ように微小間隙を介して互いの内面を対向した第１及び
第２基板11',12の周辺部を封止材12e で封止して内部空
間Ｓ’を形成した後に、この内部空間Ｓ’に放電ガスＧ
を充填して形成した放電空間Ｓをストライプ状の隔壁11
d'で複数の単位放電領域S-1,S-2,・・・に分割して構成
している。2. Description of the Related Art A plasma display panel, for example, a surface discharge type plasma display panel, is provided with a peripheral portion of first and second substrates 11 'and 12 which face each other with a small gap therebetween as shown in FIG. After forming the internal space S'by sealing with the sealing material 12e, the discharge gas G is placed in the internal space S '.
The discharge space S formed by filling the
It is divided into a plurality of unit discharge regions S-1, S-2, ... At d '.
【０００３】このように放電空間Ｓを単位放電領域S-1,
S-2,・・・に分割する隔壁11d'は、電極11b を並列した
ガラス基板11a に形成した誘電体層11c 上に、絶縁ペー
スト31 (図４参照) をスクリーン印刷した後に、この絶
縁ペースト31を５００℃前後の温度で焼成して形成した
ものである。In this way, the discharge space S is divided into unit discharge regions S-1,
The partition wall 11d 'to be divided into S-2, ... is formed by screen-printing the insulating paste 31 (see FIG. 4) on the dielectric layer 11c formed on the glass substrate 11a in which the electrodes 11b are arranged side by side. It is formed by firing 31 at a temperature of around 500 ° C.
【０００４】なお、12a は第２基板12の本体であるガラ
ス基板、12b はガラス基板12a の表面に形成された電極
（アドレス電極）、12c はガラス基板12a の表面側( プ
ラズマディスプレイパネルにおいては内面側となる) に
形成されて電極12b 上を横断するストライプ状の隔壁、
12d は隔壁12c 間においてガラス基板12a 上に形成した
蛍光体、12e はガラス基板12a の表面の周辺部に周回状
に被着させた封止材である。In addition, 12a is a glass substrate which is the main body of the second substrate 12, 12b is an electrode (address electrode) formed on the surface of the glass substrate 12a, and 12c is the surface side of the glass substrate 12a (in the plasma display panel, the inner surface). Side wall) and stripe-shaped partition walls that cross over the electrode 12b,
Reference numeral 12d is a phosphor formed on the glass substrate 12a between the partition walls 12c, and 12e is a sealing material that is circumferentially adhered to the peripheral portion of the surface of the glass substrate 12a.
【０００５】[0005]
【発明が解決しようとする課題】ところで、第１基板11
の隔壁11d'は１００μｍ程度の高さに形成することが必
要であるために、誘電体層11c に対して絶縁ペースト31
のスクリーン印刷を何回も繰り返すことが不可欠である
(図４(a) 〜(d) 参照) 。By the way, the first substrate 11
Since it is necessary to form the partition wall 11d 'of the dielectric layer 11c at a height of about 100 .mu.m, the insulating paste 31
It is essential to repeat the screen printing of many times
(See Figures 4 (a)-(d)).
【０００６】このようにして形成される隔壁11d'におい
ては印刷ずれのために、その側面が凹凸状態（図４(e)
参照) となることも少なくない。本発明は、このような
問題を解消するためになされたものであって、その目的
は隔壁の形状をほぼ設計値どうりに形成できるプラズマ
ディスプレイパネルの製造方法を提供することにある。In the partition wall 11d 'thus formed, the side surface thereof is in an uneven state due to print misalignment (see FIG. 4 (e)).
It is often the case). The present invention has been made to solve such a problem, and an object of the present invention is to provide a method of manufacturing a plasma display panel in which the shape of the barrier ribs can be formed substantially as designed.
【０００７】[0007]
【課題を解決するための手段】前記目的は、図１〜図３
に示す如く、少なくとも片側の基板上に複数の単位放電
領域に分割する隔壁を有するプラズマディスプレイパネ
ルの製造方法において、隔壁11d の製造が、この隔壁11
d を形成すべき基板上の領域に下部電極M-1 を形成する
工程と、隔壁11d の高さに対応する膜厚を有するととも
に、所定の単位放電領域に対応する部分に開口32a を設
けたレジストパターン32を基板上に形成する工程と、レ
ジストパターン32が形成された基板をめっき液に浸漬
し、このめっき液に含まれる金属を下部電極M-1 上に電
着して上部電極M-2 を形成する工程と、下部電極M-1 と
上部電極M-2 とを熱酸化してそれら電極の露出面に絶縁
膜を形成し、この絶縁膜の施された電極を隔壁とする工
程とを含んでなることを特徴とするプラズマディスプレ
イパネルの製造方法により達成される。[Means for Solving the Problems]
In the method for manufacturing a plasma display panel having a partition wall that divides into a plurality of unit discharge regions on at least one side of the substrate, as shown in FIG.
The step of forming the lower electrode M-1 in the region on the substrate where d is to be formed, and the opening 32a is provided in the portion corresponding to the predetermined unit discharge region while having a film thickness corresponding to the height of the barrier rib 11d. The step of forming the resist pattern 32 on the substrate, the substrate on which the resist pattern 32 is formed is immersed in a plating solution, and the metal contained in this plating solution is electrodeposited on the lower electrode M-1 to form the upper electrode M-. 2, a step of forming the insulating film on the exposed surfaces of the lower electrode M-1 and the upper electrode M-2 by thermal oxidation of the lower electrode M-1 and the upper electrode M-2, and using the electrode provided with the insulating film as a partition wall. And a plasma display panel manufacturing method.
【０００８】[0008]
【作用】下部電極M-1 上に金属を電着して形成した上部
電極M-2 の形状は、形成すべき隔壁11d の平面形状と略
同じ形状に形成されたレジストパターン32の開口32a に
規制される。[Function] The shape of the upper electrode M-2 formed by electrodepositing a metal on the lower electrode M-1 is formed in the opening 32a of the resist pattern 32 formed in substantially the same shape as the planar shape of the partition wall 11d to be formed. Regulated.
【０００９】したがって、下部電極M-1 と上部電極M-2
とを酸化して形成した隔壁11d の形状は、略設計値どう
りとなる。Therefore, the lower electrode M-1 and the upper electrode M-2
The shape of the partition 11d formed by oxidizing and is approximately the designed value.
【００１０】[0010]
【実施例】以下、本発明の一実施例による第１基板の形
成方法について図２及び図３を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of forming a first substrate according to an embodiment of the present invention will be described below with reference to FIGS.
【００１１】なお、本明細書においては、同一部品、同
一材料等に対しては全図をとおして同じ符号を付与して
ある。本発明の一実施例においては、まず、基板本体、
すなわちガラス基板11a の表面側 (プラズマディスプレ
イパネルにおいては内面側となる) に形成された誘電体
層11C 上に、ニッケル(Ni)を蒸着して膜厚が１０００Å
程度のニッケル膜M-1'を形成する (図２(a) 及び図２
(b) 参照) 。In the present specification, the same parts, the same materials and the like are designated by the same reference numerals throughout the drawings. In one embodiment of the present invention, first, the substrate body,
That is, nickel (Ni) is vapor-deposited on the dielectric layer 11C formed on the front surface side (which is the inner surface side in the plasma display panel) of the glass substrate 11a to have a film thickness of 1000 Å.
Forming a nickel film M-1 'to a certain extent (Fig. 2 (a) and Fig. 2)
(See (b)).
【００１２】次に、誘電体層11c 上の隔壁11d を形成す
べき領域に密着したニッケル膜M-1'だけを残しながら、
他の領域に密着したニッケル膜M-1'を通常のホトリソ技
術とエッチング技術とで除去し、ニッケル(Ni)よりなる
下部電極M-1 を形成する (図２(c) 参照) 。Next, leaving only the nickel film M-1 'adhered to the region on the dielectric layer 11c where the partition wall 11d is to be formed,
The nickel film M-1 'which is in close contact with other regions is removed by the usual photolithography technique and etching technique to form the lower electrode M-1 made of nickel (Ni) (see FIG. 2 (c)).
【００１３】なお、ホトリソ技術とエッチング技術とで
形成した下部電極M-1 の平面視の形状は、設計どうりに
完成された場合の隔壁11d の平面視の形状と略同じであ
ることは勿論である。Of course, the shape of the lower electrode M-1 formed by the photolithography technique and the etching technique in plan view is almost the same as the shape of the partition wall 11d in plan view when completed as designed. Is.
【００１４】この後、ガラス基板11a の表面側に１２０
μｍ程度の厚さでネガタイプのレジスト膜32' を被着
し、このレジスト膜32' 上に遮光性材料、たとえばクロ
ム(Cr)を蒸着してクロム膜33' を形成する (図２(d) 及
び図２(e) 参照) 。After that, the glass substrate 11a is provided with 120
A negative type resist film 32 'having a thickness of about .mu.m is deposited, and a light-shielding material such as chromium (Cr) is deposited on the resist film 32' to form a chromium film 33 '(FIG. 2 (d)). And Figure 2 (e)).
【００１５】次に、下部電極M-1 に対応するクロム膜3
3' だけを残しながら、他のクロム膜33' を通常のホト
リソ技術とエッチング技術とで除去してクロム(Cr)から
なる露光マスク33を形成する (図３(a) 参照) 。Next, the chromium film 3 corresponding to the lower electrode M-1
While leaving only 3 ', the other chromium film 33' is removed by the usual photolithography technique and etching technique to form an exposure mask 33 made of chromium (Cr) (see FIG. 3 (a)).
【００１６】この後、露光マスク33を被着したレジスト
膜32' 上に紫外線（図示せず）を照射するとともに、こ
のレジスト膜32' を現像してレジストパターン32を形成
すると、このレジストパターン32の開口32a からは下部
電極M-1 の表面だけが露出することとなる (図３(b) 参
照) 。After that, while irradiating the resist film 32 'with the exposure mask 33 with ultraviolet rays (not shown) and developing the resist film 32' to form a resist pattern 32, the resist pattern 32 'is formed. Only the surface of the lower electrode M-1 is exposed through the opening 32a (see FIG. 3 (b)).
【００１７】このレジストパターン32の開口32a の平面
視の形状は、上述の下部電極と同様に設計どうりに完成
された場合の隔壁11d の平面視の形状と略同じであるこ
とは当然である。It is natural that the shape of the opening 32a of the resist pattern 32 in plan view is substantially the same as the shape of the partition wall 11d in plan view when it is completed by the same design as the lower electrode described above. .
【００１８】次いで、このようなレジストパターン32等
が形成されたガラス基板11a をニッケルめっき液（図示
せず）に浸漬し、下部電極M-1 上にニッケル(Ni)を電着
して膜厚が１００μｍ程度での上部電極M-2 を形成す
る。Next, the glass substrate 11a on which the resist pattern 32 and the like are formed is immersed in a nickel plating solution (not shown), and nickel (Ni) is electrodeposited on the lower electrode M-1 to form a film thickness. Form an upper electrode M-2 having a thickness of about 100 μm.
【００１９】なお、この上部電極M-2 は、設計どうりに
完成された場合の隔壁11d の平面視の形状と略同じ平面
視を有するレジストパターン32の開口32a に規制された
状態で形成されていることはむろんである。The upper electrode M-2 is formed in a state of being regulated by the opening 32a of the resist pattern 32 having a plan view substantially the same as the plan view shape of the partition wall 11d when completed as designed. What you are doing is crazy.
【００２０】この後、上部電極M-2 が形成されたガラス
基板11a を６００℃程度の温度で２時間前後加熱すれ
ば、下部電極M-1 と上部電極M-2 とがそれぞれの内部ま
で完全に酸化されて酸化ニッケル(NiO) よりなる略設計
値どうりの隔壁11d が完成することとなる。After that, if the glass substrate 11a having the upper electrode M-2 formed thereon is heated at a temperature of about 600 ° C. for about 2 hours, the lower electrode M-1 and the upper electrode M-2 are completely filled. Thus, the partition wall 11d made of nickel oxide (NiO) and having a substantially designed value is completed by being oxidized.
【００２１】[0021]
【発明の効果】以上説明したように本発明は、隔壁の形
状をほぼ設計値どうりに形成できるプラズマディスプレ
イパネルの製造方法の提供を可能にする。As described above, the present invention makes it possible to provide a method of manufacturing a plasma display panel in which the shape of the barrier ribs can be formed substantially according to the design value.
【図１】は、プラズマディスプレイパネルの模式的な側
断面図FIG. 1 is a schematic side sectional view of a plasma display panel.
【図２】は、本発明の一実施例による隔壁の製造工程順
要部側断面図FIG. 2 is a sectional side view of an essential part of a manufacturing process of a partition according to an embodiment of the present invention.
【図３】は、本発明の一実施例による隔壁の製造工程順
要部側断面図FIG. 3 is a side sectional view of an essential part of a manufacturing process of a partition according to an embodiment of the present invention.
【図４】は、従来の製造方法による隔壁の製造工程順要
部側断面図FIG. 4 is a side sectional view of a main part of a manufacturing process of a partition wall according to a conventional manufacturing method.
11,11'は第１基板 11a は、ガラス基板 (基板本体) 11b は、電極 11c は、誘電体層 11d,11d'は、隔壁 12は、第２基板 12a は、ガラス基板 12b は、電極 12c は、隔壁 12d は、蛍光体 12e は、封止材 31は、絶縁ペースト 32' は、レジスト膜 32は、レジストパターン 32a は、開口 33' は、クロム膜 33は、露光マスク M-1'は、ニッケル膜 M-1 は、下部電極 M-2 は、上部電極 11, 11 'is the first substrate 11a, the glass substrate (substrate body) 11b, the electrode 11c, the dielectric layers 11d and 11d', the partition wall 12, the second substrate 12a, the glass substrate 12b, the electrode 12c. Is the partition wall 12d, the phosphor 12e, the encapsulant 31, the insulating paste 32 ', the resist film 32, the resist pattern 32a, the opening 33', the chrome film 33, the exposure mask M-1 '. , Nickel film M-1 is the lower electrode M-2 is the upper electrode
Claims (1)
電領域に分割する隔壁(11d) を有するプラズマディスプ
レイパネルの製造方法において、 前記隔壁(11d) の製造が、前記隔壁(11d) を形成すべき
前記基板上の領域に下部電極(M-1) を形成する工程と、 前記隔壁(11d) の高さに対応する膜厚を有するととも
に、所定の単位放電領域に対応する部分に開口(32a) を
設けたレジストパターン(32)を前記基板上に形成する工
程と、 前記レジストパターン(32)が形成された前記基板をめっ
き液に浸漬し、このめっき液に含まれる金属を前記下部
電極(M-1) 上に電着して上部電極(M-2) を形成する工程
と、 前記下部電極(M-1) と前記上部電極(M-2) とを熱酸化し
てそれら電極の露出面に絶縁膜を形成し、この絶縁膜の
施された電極を隔壁とする工程とを含んでなることを特
徴とするプラズマディスプレイパネルの製造方法。1. A method of manufacturing a plasma display panel having a partition (11d) on at least one side of a substrate, the partition (11d) being divided into a plurality of unit discharge regions, wherein the manufacturing of the partition (11d) forms the partition (11d). Forming a lower electrode (M-1) in a region on the substrate to be formed, and having a film thickness corresponding to the height of the barrier ribs (11d), and opening (32a in a portion corresponding to a predetermined unit discharge region). ) Is provided on the substrate to form a resist pattern (32), the substrate on which the resist pattern (32) is formed is immersed in a plating solution, and the metal contained in the plating solution is added to the lower electrode ( M-1) to form an upper electrode (M-2) by electrodeposition, and the lower electrode (M-1) and the upper electrode (M-2) are thermally oxidized to expose the electrodes. A step of forming an insulating film on the surface and using the electrode provided with the insulating film as a partition wall. Manufacturing method of plasma display panel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5084416A JPH06295675A (en) | 1993-04-12 | 1993-04-12 | Manufacture of plasma display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5084416A JPH06295675A (en) | 1993-04-12 | 1993-04-12 | Manufacture of plasma display panel |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06295675A true JPH06295675A (en) | 1994-10-21 |
Family
ID=13829990
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5084416A Withdrawn JPH06295675A (en) | 1993-04-12 | 1993-04-12 | Manufacture of plasma display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06295675A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010004092A (en) * | 1999-06-28 | 2001-01-15 | 김영환 | Method for forming electrode of plasma display panel by using electrolysis plating |
| KR100340076B1 (en) * | 1999-06-28 | 2002-06-12 | 박종섭 | Method for simultaneous forming electrode and barrier rib of plasma display panel by electroplating |
| US6508685B1 (en) | 1998-07-21 | 2003-01-21 | Lg Electronics Inc. | Plasma display panel and method of fabricating barrier rib therefor |
| KR100459890B1 (en) * | 1999-05-26 | 2004-12-03 | 삼성에스디아이 주식회사 | Method for fabricating a barrier rib of plasma display panel |
-
1993
- 1993-04-12 JP JP5084416A patent/JPH06295675A/en not_active Withdrawn
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6508685B1 (en) | 1998-07-21 | 2003-01-21 | Lg Electronics Inc. | Plasma display panel and method of fabricating barrier rib therefor |
| US6783416B2 (en) | 1998-07-21 | 2004-08-31 | Lg Electronics Inc. | Plasma display panel and method of fabricating barrier rib thereof |
| KR100459890B1 (en) * | 1999-05-26 | 2004-12-03 | 삼성에스디아이 주식회사 | Method for fabricating a barrier rib of plasma display panel |
| KR20010004092A (en) * | 1999-06-28 | 2001-01-15 | 김영환 | Method for forming electrode of plasma display panel by using electrolysis plating |
| KR100340076B1 (en) * | 1999-06-28 | 2002-06-12 | 박종섭 | Method for simultaneous forming electrode and barrier rib of plasma display panel by electroplating |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000704 |