JPH0629202U - Adapters for mounting circuit boards and dielectric filters - Google Patents
Adapters for mounting circuit boards and dielectric filtersInfo
- Publication number
- JPH0629202U JPH0629202U JP6856192U JP6856192U JPH0629202U JP H0629202 U JPH0629202 U JP H0629202U JP 6856192 U JP6856192 U JP 6856192U JP 6856192 U JP6856192 U JP 6856192U JP H0629202 U JPH0629202 U JP H0629202U
- Authority
- JP
- Japan
- Prior art keywords
- dielectric filter
- input
- circuit board
- electrodes
- output electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Control Of Motors That Do Not Use Commutators (AREA)
Abstract
(57)【要約】
【目的】 誘電体フィルタの特性改善を図ることのでき
る回路基板および実装用アダプタを提供することであ
る。
【構成】 誘電体フィルタ２は、アダプタ３が装着され
た後、回路基板１の上に実装される。このとき、誘電体
フィルタ２の入出力電極と回路基板の入出力電極１１，
１２とがアダプタ３の接続用電極３１，３２を介して接
続される。回路基板１には入出力電極１１と１２との間
にスルーホール１３が形成され、アダプタ３には接続用
電極３１と３２との間にスルーホール３３が形成され
る。これらスルーホール１３，３３によって、入出力電
極１１と１２との間の寄生容量および接続用電極３１と
３２との間の寄生容量容量が低減され、誘電体フィルタ
２の減衰特性が改善される。
(57) [Abstract] [Purpose] To provide a circuit board and a mounting adapter capable of improving the characteristics of a dielectric filter. [Constitution] The dielectric filter 2 is mounted on the circuit board 1 after the adapter 3 is mounted. At this time, the input / output electrodes of the dielectric filter 2 and the input / output electrodes 11 of the circuit board,
12 is connected via the connection electrodes 31 and 32 of the adapter 3. A through hole 13 is formed between the input / output electrodes 11 and 12 on the circuit board 1, and a through hole 33 is formed between the connection electrodes 31 and 32 on the adapter 3. These through holes 13 and 33 reduce the parasitic capacitance between the input / output electrodes 11 and 12 and the parasitic capacitance between the connection electrodes 31 and 32, and improve the attenuation characteristic of the dielectric filter 2.
Description
【０００１】[0001]
この考案は、回路基板および誘電体フィルタの実装用アダプタに関し、より特 定的には、誘電体フィルタが実装される回路基板および誘電体フィルタを回路基 板に実装する際に用いられるアダプタに関する。 The present invention relates to an adapter for mounting a circuit board and a dielectric filter, and more particularly to an adapter used for mounting the circuit board on which the dielectric filter is mounted and the dielectric filter on a circuit board.
【０００２】[0002]
図３および図４は、誘電体フィルタの実装構造の一例を示す図であり、特に、 図３はその分解斜視図であり、図４はその断面図である。図３および図４に示す ように、ＰＣＢ（プリント基板）等の回路基板１の一方主表面１ａの上には、入 出力電極１１，１２が形成されている。一方、誘電体フィルタ２の実装面にも入 出力電極２１，２２が形成されている。誘電体フィルタ２は、入出力電極１１， １２の上に表面実装される。このとき、誘電体フィルタ２の入出力電極２１，２ ２は、それぞれ、回路基板１の入出力電極１１，１２と接続される。 3 and 4 are views showing an example of the mounting structure of the dielectric filter, in particular, FIG. 3 is an exploded perspective view thereof, and FIG. 4 is a sectional view thereof. As shown in FIGS. 3 and 4, input / output electrodes 11 and 12 are formed on one main surface 1a of the circuit board 1 such as a PCB (printed circuit board). On the other hand, input / output electrodes 21 and 22 are also formed on the mounting surface of the dielectric filter 2. The dielectric filter 2 is surface-mounted on the input / output electrodes 11 and 12. At this time, the input / output electrodes 21 and 22 of the dielectric filter 2 are connected to the input / output electrodes 11 and 12 of the circuit board 1, respectively.
【０００３】 図５および図６は、誘電体フィルタの実装構造の他の例を示す図であり、特に 、図５はその分解斜視図であり、図６はその断面図である。図５および図６にお いて、誘電体フィルタ２にはアダプタ３が装着される。誘電体フィルタ２は、こ のアダプタ３を介して回路基板１の一方主表面１ａの上に実装される。アダプタ ３は、絶縁性基板３ａを含み、この絶縁性基板３ａの上に接続用電極３１，３２ が形成されている。接続用電極３１，３２は、互いに配置間隔の異なる誘電体フ ィルタ２の入出力電極２１，２２と回路基板１の入出力電極１１，１２とを相互 に接続する。このようなアダプタ３は、本願出願人の提案によるもので、本願に 先行して出願されている。5 and 6 are diagrams showing another example of the mounting structure of the dielectric filter, in particular, FIG. 5 is an exploded perspective view thereof, and FIG. 6 is a sectional view thereof. In FIG. 5 and FIG. 6, an adapter 3 is attached to the dielectric filter 2. Dielectric filter 2 is mounted on one main surface 1a of circuit board 1 via adapter 3. The adapter 3 includes an insulating substrate 3a, and the connecting electrodes 31 and 32 are formed on the insulating substrate 3a. The connection electrodes 31 and 32 connect the input / output electrodes 21 and 22 of the dielectric filter 2 and the input / output electrodes 11 and 12 of the circuit board 1 which are arranged at mutually different intervals. Such an adapter 3 is proposed by the applicant of the present application and filed prior to the present application.
【０００４】[0004]
図４に示すように、回路基板１には、入出力電極１１と１２との間に寄生容量 Ｃａが発生する。この寄生容量Ｃａによって、入出力電極１１と１２との間で高 周波信号の不所望なリーク経路が形成され、誘電体フィルタ２の減衰特性が悪化 する。 As shown in FIG. 4, in the circuit board 1, a parasitic capacitance Ca is generated between the input / output electrodes 11 and 12. Due to this parasitic capacitance Ca, an undesired leak path of a high frequency signal is formed between the input / output electrodes 11 and 12, and the attenuation characteristic of the dielectric filter 2 deteriorates.
【０００５】 同様に、アダプタ３においても接続用電極３１と３２との間に寄生容量Ｃｂが 発生する（図６参照）。その結果、接続用電極３１と３２との間で、高周波信号 の不所望なリーク経路が形成され、誘電体フィルタ２の減衰特性が悪化する。Similarly, also in the adapter 3, a parasitic capacitance Cb is generated between the connecting electrodes 31 and 32 (see FIG. 6). As a result, an undesired leak path for high-frequency signals is formed between the connecting electrodes 31 and 32, and the attenuation characteristic of the dielectric filter 2 deteriorates.
【０００６】 それゆえに、この考案の目的は、誘電体フィルタの特性を改善し得る回路基板 およびアダプタを提供することである。Therefore, it is an object of the present invention to provide a circuit board and an adapter that can improve the characteristics of a dielectric filter.
【０００７】[0007]
請求項１に係る考案は、その一方主表面上に誘電体フィルタが実装され、かつ その一方主表面上に当該誘電体フィルタと接続される複数の入出力電極が形成さ れた回路基板であって、 各入出力電極間に生じる寄生容量を低減させるために、各入出力電極間に削除 領域を設けたことを特徴とする。 The invention according to claim 1 is a circuit board in which a dielectric filter is mounted on one main surface thereof, and a plurality of input / output electrodes connected to the dielectric filter are formed on one main surface thereof. In addition, in order to reduce the parasitic capacitance generated between the input / output electrodes, a deleted region is provided between the input / output electrodes.
【０００８】 請求項２に係る考案は、誘電体フィルタを回路基板に実装する際に、当該誘電 体フィルタに装着されるアダプタであって、 絶縁性基板、および 絶縁性基板の表面上に形成され、互いに配置間隔の異なる誘電体フィルタ側の 各入出力電極と回路基板側の各入出力電極とを相互に接続するための複数の接続 用電極を備え、 各接続用電極間に生じる寄生容量を低減させるために、絶縁性基板における各 接続用電極間に削除領域を設けたことを特徴とする。According to a second aspect of the present invention, there is provided an adapter, which is mounted on a dielectric filter when the dielectric filter is mounted on a circuit board, the adapter being formed on an insulating substrate and a surface of the insulating substrate. , The input / output electrodes on the dielectric filter side and the input / output electrodes on the circuit board side, which are arranged at different intervals from each other, are provided with a plurality of connecting electrodes, and the parasitic capacitance generated between the connecting electrodes is In order to reduce the number, it is characterized in that a deletion region is provided between each connection electrode on the insulating substrate.
【０００９】[0009]
請求項１に係る考案においては、回路基板に形成された複数の入出力電極間に 削除領域を設けることにより、各入出力電極間に生じる寄生容量を低減させるよ うにしている。これによって、回路基板に実装される誘電体フィルタの特性の改 善を図ることができる。 In the device according to the first aspect, the deletion region is provided between the plurality of input / output electrodes formed on the circuit board to reduce the parasitic capacitance generated between the input / output electrodes. As a result, the characteristics of the dielectric filter mounted on the circuit board can be improved.
【００１０】 請求項２に係る考案においては、互いに配置間隔の異なる誘電体フィルタ側の 各入出力電極と回路基板側の各入出力電極とを接続するためのアダプタに形成さ れた複数の接続用電極間に削除領域を設けることにより、各接続用電極間に生じ る寄生容量を低減させるようにしている。これによって、アダプタに装着される 誘電体フィルタの特性の改善を図ることができる。According to a second aspect of the present invention, a plurality of connections formed on an adapter for connecting each input / output electrode on the dielectric filter side and each input / output electrode on the circuit board side having different arrangement intervals from each other. By providing a deletion region between the connection electrodes, the parasitic capacitance generated between the connection electrodes is reduced. As a result, the characteristics of the dielectric filter attached to the adapter can be improved.
【００１１】[0011]
まず、図１を参照して、この考案の一実施例に係る回路基板の構成を説明する 。図１に示すように、回路基板１の一方主表面１ａの上には、入出力電極１１， １２が形成されている。この入出力電極１１，１２の上には、誘電体フィルタ１ が実装される。ここまでの構成は、図３の構成と同様である。この実施例の特徴 は、入出力電極１１と１２とを結ぶ直線上の略中央に複数個の円形のスルーホー ル１３を形成したことである。 First, the structure of a circuit board according to an embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, input / output electrodes 11 and 12 are formed on one main surface 1a of the circuit board 1. The dielectric filter 1 is mounted on the input / output electrodes 11 and 12. The configuration up to this point is similar to that of FIG. The feature of this embodiment is that a plurality of circular through-holes 13 are formed substantially in the center on a straight line connecting the input / output electrodes 11 and 12.
【００１２】 回路基板１に上記のようなスルーホール１３を設けることにより、入出力電極 １１と１２との間に空気の障壁が形成される。空気の比誘電率εｏは、回路基板 １の比誘電率εｓよりも格段に低いので、入出力電極１１と１２との間に生じる 寄生容量Ｃａ（図４参照）の値は、極めて小さくなる。したがって、入出力電極 １１と１２との間の容量性インダクタンスが大きくなり、入出力電極１１と１２ との間に流れる高周波信号のリーク量が著しく低減される。その結果、図３およ び図４に示す回路基板に比べて、誘電体フィルタ１の減衰特性を大幅に改善する ことができる。By providing the through hole 13 as described above in the circuit board 1, an air barrier is formed between the input / output electrodes 11 and 12. Since the relative permittivity εo of air is much lower than the relative permittivity εs of the circuit board 1, the value of the parasitic capacitance Ca (see FIG. 4) generated between the input / output electrodes 11 and 12 is extremely small. Therefore, the capacitive inductance between the input / output electrodes 11 and 12 becomes large, and the leak amount of the high-frequency signal flowing between the input / output electrodes 11 and 12 is significantly reduced. As a result, the attenuation characteristic of the dielectric filter 1 can be significantly improved as compared with the circuit boards shown in FIGS. 3 and 4.
【００１３】 次に、図２を参照して、この考案の一実施例に係る実装用アダプタの構成を説 明する。図２において、アダプタ３の絶縁性基板の上に形成された接続用電極３ １と３２とを結ぶ直線上の略中央には、接続用電極３１と３２とを結ぶ直線と直 交する方向に延びる略楕円形上のスルーホール３３が形成される。このスルーホ ール３３は、前述のスルーホール２２と同様に作用し、接続用電極３１と３２と の間に生じる寄生容量Ｃｂ（図６参照）の値を小さくする。したがって、接続用 電極３１と３２との間の容量性インダクタンスが大きくなり、入出力電極３１と ３２との間に流れる高周波信号のリーク量が著しく低減される。その結果、図５ および図６に示す回路基板に比べて、誘電体フィルタ１の減衰特性を大幅に改善 することができる。なお、図１の実施例と同様に、回路基板１においても入出力 電極１１と１２との間にスルーホール１３を形成すれば、誘電体フィルタ１の減 衰特性をより一層改善できる。Next, the configuration of the mounting adapter according to the embodiment of the present invention will be described with reference to FIG. In FIG. 2, in the approximate center of the straight line connecting the connecting electrodes 31 and 32 formed on the insulating substrate of the adapter 3, in the direction perpendicular to the straight line connecting the connecting electrodes 31 and 32. A substantially elliptical through hole 33 is formed. The through hole 33 acts in the same manner as the through hole 22 described above, and reduces the value of the parasitic capacitance Cb (see FIG. 6) generated between the connecting electrodes 31 and 32. Therefore, the capacitive inductance between the connecting electrodes 31 and 32 becomes large, and the leak amount of the high-frequency signal flowing between the input / output electrodes 31 and 32 is significantly reduced. As a result, the attenuation characteristic of the dielectric filter 1 can be significantly improved as compared with the circuit boards shown in FIGS. As in the embodiment of FIG. 1, if the through hole 13 is formed between the input / output electrodes 11 and 12 also in the circuit board 1, the attenuation characteristic of the dielectric filter 1 can be further improved.
【００１４】 なお、スルーホール１３は入出力電極１１と１２を結ぶ直線上に、またスルー ホール３３は接続用電極３１と３２とを結ぶ直線上に形成するのが誘電体フィル タの特性改善上最も好ましいが、この考案は特にこれに限定されることはなく、 スルーホールは他の位置に形成されてもよい。また、スルーホールの形状も上記 実施例のような円形，楕円形上に限らず、他の形状であってもよい。さらに、ス ルーホールを設ける数も上記実施例のものに限定されることはない。The through hole 13 is formed on a straight line connecting the input / output electrodes 11 and 12, and the through hole 33 is formed on a straight line connecting the connecting electrodes 31 and 32 in order to improve the characteristics of the dielectric filter. Most preferably, the invention is not limited to this, and the through holes may be formed at other positions. Further, the shape of the through hole is not limited to the circular shape or the elliptical shape as in the above embodiment, but may be other shapes. Further, the number of through holes provided is not limited to that in the above embodiment.
【００１５】[0015]
請求項１に係る考案によれば、回路基板に形成された複数の入出力電極間に削 除領域を設けることにより、各入出力電極間に生じる寄生容量を著しく低減させ るようにしているので、回路基板に実装される誘電体フィルタの特性を大幅に改 善させることができる。 According to the first aspect of the present invention, the parasitic capacitance generated between the input / output electrodes is remarkably reduced by providing the removal region between the plurality of input / output electrodes formed on the circuit board. The characteristics of the dielectric filter mounted on the circuit board can be greatly improved.
【００１６】 請求項２に係る考案によれば、互いに配置間隔の異なる誘電体フィルタ側の各 入出力電極と回路基板側の各入出力電極とを接続するためのアダプタに形成され た複数の接続用電極間に削除領域を設けることにより、各接続用電極間に生じる 寄生容量を著しく低減させるようにしているので、アダプタに装着される誘電体 フィルタの特性を大幅に改善させることができる。According to the second aspect of the invention, a plurality of connections formed on the adapter for connecting the input / output electrodes on the dielectric filter side and the input / output electrodes on the circuit board side, which are arranged at different intervals, from each other. By providing the deleted region between the connection electrodes, the parasitic capacitance generated between the connection electrodes is significantly reduced, so that the characteristics of the dielectric filter mounted on the adapter can be significantly improved.
【図１】この考案の一実施例に係る回路基板の構成を説
明するための分解斜視図である。FIG. 1 is an exploded perspective view illustrating a configuration of a circuit board according to an embodiment of the present invention.
【図２】この考案の一実施例に係るアダプタの構成を説
明するための分解斜視図である。FIG. 2 is an exploded perspective view for explaining a configuration of an adapter according to an embodiment of the present invention.
【図３】誘電体フィルタの実装構造の一例を示す分解斜
視図である。FIG. 3 is an exploded perspective view showing an example of a mounting structure of a dielectric filter.
【図４】誘電体フィルタの実装構造の一例を示す断面図
である。FIG. 4 is a cross-sectional view showing an example of a dielectric filter mounting structure.
【図５】誘電体フィルタの実装構造の他の例を示す分解
斜視図である。FIG. 5 is an exploded perspective view showing another example of the mounting structure of the dielectric filter.
【図６】誘電体フィルタの実装構造の他の例を示す断面
図である。FIG. 6 is a cross-sectional view showing another example of the mounting structure of the dielectric filter.
１： 回路基板 １１，１２： 入出力電極 １３： スルーホール ２： 誘電体フィルタ ２１，２２： 入出力電極 ３： アダプタ ３１，３２： 接続用電極 ３３： スルーホール 1: Circuit board 11, 12: Input / output electrode 13: Through hole 2: Dielectric filter 21, 22: Input / output electrode 3: Adapter 31, 32: Connection electrode 33: Through hole
Claims (2)
装され、かつその一方主表面上に当該誘電体フィルタと
接続される複数の入出力電極が形成された回路基板であ
って、 各前記入出力電極間に生じる寄生容量を低減させるため
に、各前記入出力電極間に削除領域を設けたことを特徴
とする、回路基板。1. A circuit board in which a dielectric filter is mounted on one main surface thereof, and a plurality of input / output electrodes connected to the dielectric filter are formed on one main surface thereof. A circuit board, wherein a deletion region is provided between each of the input / output electrodes in order to reduce a parasitic capacitance generated between the writing and outputting electrodes.
に、当該誘電体フィルタに装着されるアダプタであっ
て、 絶縁性基板、および前記絶縁性基板の表面上に形成さ
れ、互いに配置間隔の異なる誘電体フィルタ側の各入出
力電極と回路基板側の各入出力電極とを相互に接続する
ための複数の接続用電極を備え、 各前記接続用電極間に生じる寄生容量を低減させるため
に、前記絶縁性基板における各前記接続用電極間に削除
領域を設けたことを特徴とする、誘電体フィルタの実装
用アダプタ。2. An adapter, which is mounted on a dielectric filter when the dielectric filter is mounted on a circuit board, comprising: an insulating substrate; In order to reduce the parasitic capacitance generated between the connection electrodes, a plurality of connection electrodes for mutually connecting the input / output electrodes on different dielectric filter sides and the input / output electrodes on the circuit board side are provided. An adapter for mounting a dielectric filter, characterized in that a deletion region is provided between each of the connecting electrodes on the insulating substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6856192U JPH0629202U (en) | 1992-09-04 | 1992-09-04 | Adapters for mounting circuit boards and dielectric filters |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6856192U JPH0629202U (en) | 1992-09-04 | 1992-09-04 | Adapters for mounting circuit boards and dielectric filters |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0629202U true JPH0629202U (en) | 1994-04-15 |
Family
ID=13377302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6856192U Pending JPH0629202U (en) | 1992-09-04 | 1992-09-04 | Adapters for mounting circuit boards and dielectric filters |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0629202U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004247980A (en) * | 2003-02-14 | 2004-09-02 | Hitachi Ltd | Connection structure and method of transmission line |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6348002A (en) * | 1986-08-18 | 1988-02-29 | Oki Electric Ind Co Ltd | Dielectric filter |
-
1992
- 1992-09-04 JP JP6856192U patent/JPH0629202U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6348002A (en) * | 1986-08-18 | 1988-02-29 | Oki Electric Ind Co Ltd | Dielectric filter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004247980A (en) * | 2003-02-14 | 2004-09-02 | Hitachi Ltd | Connection structure and method of transmission line |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3448341B2 (en) | Dielectric filter device | |
| JPH0725602U (en) | Dielectric filter mounting structure | |
| JPH0629202U (en) | Adapters for mounting circuit boards and dielectric filters | |
| JP4103466B2 (en) | High-frequency connector surface mounting method, high-frequency connector mounting printed circuit board, and printed circuit board | |
| JP2004328118A (en) | Dielectric filter | |
| JPH0741176Y2 (en) | Printed wiring board | |
| JP2524535Y2 (en) | Dielectric filter | |
| JP2503443Y2 (en) | Dielectric filter | |
| JPH0582936A (en) | Electric circuit for leadless component-loading substrate | |
| JPH075682Y2 (en) | Dielectric device with terminal | |
| JP3660539B2 (en) | Directional coupler | |
| JP2704055B2 (en) | High frequency semiconductor device | |
| JP3592875B2 (en) | Dielectric filter | |
| JPH06268406A (en) | Laminated filter | |
| JP2000208670A (en) | Package board and electronic device using the same | |
| JPH05102710A (en) | High frequency transmission circuit | |
| JPH02217012A (en) | Noise filter for face mounting | |
| JPH0230843Y2 (en) | ||
| JPH09121102A (en) | Surface mount structure for layered dielectric filter | |
| JPH0576096U (en) | Mounting structure for laminated integrated components | |
| JPH0672181U (en) | Multi-pin connector | |
| JPH0766606A (en) | Surface mounted type electronic parts | |
| JPH02301311A (en) | Chip type noise elimination filter | |
| JP2000022480A (en) | Laminated filter | |
| JPH0371611A (en) | Packaging method for laminated chip capacitor |