JPH06251981A - Multilayer chip capacitor provided with discharge - Google Patents
Multilayer chip capacitor provided with dischargeInfo
- Publication number
- JPH06251981A JPH06251981A JP3787793A JP3787793A JPH06251981A JP H06251981 A JPH06251981 A JP H06251981A JP 3787793 A JP3787793 A JP 3787793A JP 3787793 A JP3787793 A JP 3787793A JP H06251981 A JPH06251981 A JP H06251981A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- discharge
- bare chip
- electrode
- pair
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はベアチップの両端部に一
対の外部電極を有する積層チップコンデンサに関する。
更に詳しくは、これらの外部電極に接続されてベアチッ
プの外面に形成された放電用電極を有し、この放電用電
極によりサージ電圧を吸収し得る積層チップコンデンサ
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer chip capacitor having a pair of external electrodes on both ends of a bare chip.
More specifically, the present invention relates to a multilayer chip capacitor which has a discharge electrode connected to these external electrodes and formed on the outer surface of a bare chip and which can absorb a surge voltage by the discharge electrode.
【０００２】[0002]
【従来の技術】積層チップコンデンサはプリント回路基
板の表面にリードレスで直接実装できる小型の電子部品
であるため、各種の電子機器の軽薄短小化に必要不可欠
の電子部品として広く一般的に使用されている。特に小
型でかつ大容量にするために積層チップコンデンサは、
その内部の誘電体層を薄くして積層数を増大している。
このためこの種の積層チップコンデンサは、従来のリー
ド線付きのコンデンサと比較して誘電体の絶縁破壊強度
が低く、サージ電圧やパルスなどの異常電圧が印加する
回路ではサージアブソーバと併用しない限り、使用する
ことができなかった。しかしサージアブソーバと併用し
た場合には、基板に実装する部品点数が増大し、かつ基
板上に多くの取付スペースを必要とする不具合があっ
た。2. Description of the Related Art Since a multilayer chip capacitor is a small electronic component that can be directly mounted on the surface of a printed circuit board in a leadless manner, it is widely and generally used as an electronic component indispensable for making various electronic devices lighter, thinner and smaller. ing. In particular, in order to make it small and have a large capacity, multilayer chip capacitors are
The number of laminated layers is increased by thinning the dielectric layer inside.
For this reason, this type of multilayer chip capacitor has a lower dielectric breakdown strength of the dielectric than conventional capacitors with lead wires, and unless used in combination with a surge absorber in a circuit to which abnormal voltage such as surge voltage or pulse is applied. Could not be used. However, when used in combination with the surge absorber, there are problems that the number of components mounted on the board increases and a large mounting space is required on the board.
【０００３】従来、積層チップコンデンサの絶縁破壊を
防止するために、サージ電圧印加時にチップコンデンサ
に接続される入出力端子においてスパークを発生させる
技術が開示されている（特開平２−１４４８６３）。こ
の入出力端子は金属ケース内に絶縁体を介して接触片を
納めるように構成され、接触片の先端に鋭角状の突起を
形成している。サージ電圧印加時にはこの突起と金属ケ
ースとの間でスパークを生じるようにしている。この入
出力端子を用いれば、サージアブソーバを併用すること
なくまた基板に実装する部品点数や取付スペースを増や
すことなく積層チップコンデンサを異常電圧から保護す
ることができる。Conventionally, in order to prevent dielectric breakdown of a multilayer chip capacitor, a technique has been disclosed in which a spark is generated at an input / output terminal connected to a chip capacitor when a surge voltage is applied (JP-A-2-144863). The input / output terminal is configured so that the contact piece is housed in a metal case via an insulator, and a sharp-angled projection is formed at the tip of the contact piece. When a surge voltage is applied, a spark is generated between the protrusion and the metal case. By using this input / output terminal, it is possible to protect the multilayer chip capacitor from abnormal voltage without using a surge absorber together and without increasing the number of parts to be mounted on the board or the mounting space.
【０００４】[0004]
【発明が解決しようとする課題】しかし、回路設計上、
特開平２−１４４８６３号公報に示される入出力端子に
直接接続できない積層チップコンデンサに対しては、依
然としてサージ電圧などの異常電圧から保護することが
できない問題点があった。また上記入出力端子では、そ
の突起と金属ケースとのギャップの広狭により放電開始
電圧が決まるため、ギャップ調整が容易でなく、所望の
放電開始電圧を得ることが困難な欠点があった。However, due to the circuit design,
The multilayer chip capacitor disclosed in JP-A-2-144863, which cannot be directly connected to the input / output terminal, still has a problem that it cannot be protected from abnormal voltage such as surge voltage. Further, in the above-mentioned input / output terminal, since the discharge start voltage is determined by the width of the gap between the protrusion and the metal case, it is difficult to adjust the gap and it is difficult to obtain a desired discharge start voltage.
【０００５】本発明の目的は、実装部品の点数や基板上
の取付スペースを増大させずに、サージ電圧やパルスな
どの異常電圧に対して適切にスパークし、これらの異常
電圧により内部の誘電体層を絶縁破壊しない放電ギャッ
プ付き積層チップコンデンサを提供することにある。An object of the present invention is to appropriately spark an abnormal voltage such as a surge voltage or a pulse without increasing the number of mounted parts or a mounting space on a substrate, and to use the abnormal voltage to cause an internal dielectric substance to be generated. An object is to provide a multilayer chip capacitor with a discharge gap that does not cause dielectric breakdown of layers.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
の本発明の構成を、実施例に対応する図１及び図２を用
いて説明する。本発明は、誘電体層１１と内部電極１２
とを交互に積層して焼成一体化して形成されたベアチッ
プ１３と、このベアチップ１３の互いに対向する両端部
に形成され前記積層された複数の内部電極１２に交互に
電気的に接続する一対の第１外部電極１４，１５とを備
えた積層チップコンデンサ１０の改良である。その特徴
ある構成は、誘電体層１１の絶縁破壊電圧よりも放電開
始電圧の低い一対の放電用電極１６，１７が所定のギャ
ップＧをあけてかつ一対の外部電極１４，１５にそれぞ
れ電気的に接続されてベアチップ１３の外面に形成され
たことにある。A configuration of the present invention for achieving the above object will be described with reference to FIGS. 1 and 2 corresponding to the embodiments. The present invention relates to the dielectric layer 11 and the internal electrode 12.
Bare chips 13 formed by alternately laminating and firing and a pair of first electrodes alternately formed on both ends of the bare chip 13 facing each other and electrically connected to the laminated internal electrodes 12. 1 is an improvement of the multilayer chip capacitor 10 including the external electrodes 14 and 15. The characteristic structure is that the pair of discharge electrodes 16 and 17 having a lower discharge start voltage than the dielectric breakdown voltage of the dielectric layer 11 are electrically connected to the pair of external electrodes 14 and 15 with a predetermined gap G. It is connected to and formed on the outer surface of the bare chip 13.
【０００７】[0007]
【作用】外部電極１４，１５に接続する放電用電極１
６，１７をベアチップ１３の外面に形成すると、このチ
ップコンデンサ１０へのサージ電圧印加時にギャップＧ
に臨む一対の放電用電極１６，１７の各先端に電界が集
中する。この印加電圧が電極１６，１７の放電開始電圧
以上であれば、ここでスパークが発生してチップコンデ
ンサ１０の内部電極１２，１２間にはサージ電流は流れ
ない。Operation: Discharge electrode 1 connected to external electrodes 14 and 15
6 and 17 are formed on the outer surface of the bare chip 13, a gap G is generated when a surge voltage is applied to the chip capacitor 10.
The electric field is concentrated on the respective tips of the pair of discharge electrodes 16 and 17 facing the. If the applied voltage is equal to or higher than the discharge start voltage of the electrodes 16 and 17, a spark is generated here and no surge current flows between the internal electrodes 12 and 12 of the chip capacitor 10.
【０００８】[0008]
【実施例】次に本発明の実施例を図面に基づいて詳しく
説明する。図１及び図２は第１実施例の２端子型の放電
ギャップ付き積層チップコンデンサ１０を示す。図１及
び図２に示すように、積層チップコンデンサ１０は、誘
電体層１１と内部電極１２とを交互に積層して焼成一体
化して形成されたベアチップ１３と、このベアチップ１
３の互いに対向する両端部に形成された一対の第１外部
電極１４，１５とを備える。これらの外部電極１４，１
５は積層された複数の内部電極１２に交互に電気的に接
続する。ベアチップ１３の上面には一対の放電用電極１
６，１７が一対の外部電極１４，１５にそれぞれ電気的
に接続されて形成される。これらの電極１６，１７はそ
の放電開始電圧が誘電体層１１の絶縁破壊電圧よりも低
くなるように、各先端が所定のギャップＧをあけて形成
される。これらの放電用電極は、導電性ペーストをスク
リーン印刷、或いは転写した後、焼付けて形成される。
別の方法として、めっき又は蒸着などの公知の薄膜形成
技術により形成してもよい。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 and 2 show a two-terminal type multilayer chip capacitor 10 with a discharge gap according to the first embodiment. As shown in FIGS. 1 and 2, the multilayer chip capacitor 10 includes a bare chip 13 formed by alternately laminating dielectric layers 11 and internal electrodes 12 and firing and integrating the bare chip 13 and the bare chip 1.
3 and a pair of first external electrodes 14 and 15 formed at both end portions facing each other. These external electrodes 14, 1
5 are electrically connected to the plurality of laminated internal electrodes 12 alternately. A pair of discharge electrodes 1 is formed on the upper surface of the bare chip 13.
6 and 17 are formed by being electrically connected to the pair of external electrodes 14 and 15, respectively. Each of the electrodes 16 and 17 is formed with a predetermined gap G at each tip so that the discharge start voltage becomes lower than the dielectric breakdown voltage of the dielectric layer 11. These discharge electrodes are formed by screen-printing or transferring a conductive paste and then baking it.
Alternatively, it may be formed by a known thin film forming technique such as plating or vapor deposition.
【０００９】このような構成の積層チップコンデンサ１
０をプリント回路基板に実装して、この回路にサージ電
圧のような異常電圧が印加されると、ギャップＧに臨む
一対の放電用電極１６，１７の各先端に電界が集中す
る。この印加電圧が電極１６，１７の放電開始電圧以上
であれば、ここでスパークが発生してチップコンデンサ
１０の内部電極１２，１２間にサージ電流を流さない。A multilayer chip capacitor 1 having such a configuration
When 0 is mounted on a printed circuit board and an abnormal voltage such as a surge voltage is applied to this circuit, an electric field is concentrated at the tips of the pair of discharge electrodes 16 and 17 facing the gap G. If this applied voltage is equal to or higher than the discharge start voltage of the electrodes 16 and 17, a spark is generated here and a surge current does not flow between the internal electrodes 12 and 12 of the chip capacitor 10.
【００１０】図３〜図５は本発明第２実施例の高周波ノ
イズ除去機能を有する３端子型の放電ギャップ付き積層
チップコンデンサ２０を示す。図３〜図５の各符号は図
１及び図２の同一構成部品の各符号に１０を加えて示
す。この例のベアチップ２３は誘電体層２１とアース電
極２８と内部電極２２とを交互に積層して焼成一体化し
て形成される。この例ではアース電極２８は交互に積層
される内部電極２２，２２の重なり合う部分に対応し
て、かつ内部電極が延びる誘電体層２１の端縁とは異な
る端縁にまで延びて形成される。一対の第１外部電極２
４，２５はベアチップ２３の互いに対向する両端部に形
成され、積層された複数の内部電極２２，２２に交互に
電気的に接続される。一対の第１外部電極２４，２５の
間のベアチップ２３の外周面には第２外部電極２９が形
成される。この電極２９はベアチップ２３の両側面に現
れるアース電極２８に電気的に接続される。3 to 5 show a three-terminal type multilayer chip capacitor 20 with a discharge gap having a high frequency noise removing function according to a second embodiment of the present invention. Each reference numeral in FIGS. 3 to 5 is shown by adding 10 to each reference numeral of the same component in FIGS. 1 and 2. The bare chip 23 of this example is formed by alternately stacking the dielectric layers 21, the ground electrodes 28, and the internal electrodes 22, and firing and integrating them. In this example, the ground electrode 28 is formed so as to correspond to the overlapping portions of the internal electrodes 22, 22 that are alternately stacked and extend to an edge different from the edge of the dielectric layer 21 in which the internal electrodes extend. A pair of first external electrodes 2
4, 25 are formed on both ends of the bare chip 23 facing each other, and are electrically connected to the plurality of stacked internal electrodes 22, 22 alternately. A second external electrode 29 is formed on the outer peripheral surface of the bare chip 23 between the pair of first external electrodes 24, 25. The electrode 29 is electrically connected to the ground electrodes 28 appearing on both side surfaces of the bare chip 23.
【００１１】この例では、第１外部電極２４，２５と第
２外部電極２９との間のベアチップ２３の上面に２対の
放電用電極２６ａ，２６ｂ及び２７ａ，２７ｂが形成さ
れる。電極２６ａは第１外部電極２４に、電極２６ｂは
第２外部電極２９の一方の側端に、電極２７ｂは第２外
部電極２９の他方の側端に、また電極２７ａは第１外部
電極２５にそれぞれ電気的に接続される。放電用電極２
６ａ，２６ｂの間のギャップＧ及び放電用電極２７ａ，
２７ｂの間のギャップＧは同一であって、それぞれベア
チップ２３を構成する誘電体層２１の絶縁破壊電圧より
も低い電圧でこれらの電極２６ａ，２６ｂ及び２７ａ，
２７ｂが放電を開始するように所定の寸法に決められ
る。これらの放電用電極の形成方法は第１実施例と同様
である。In this example, two pairs of discharge electrodes 26a, 26b and 27a, 27b are formed on the upper surface of the bare chip 23 between the first external electrodes 24, 25 and the second external electrode 29. The electrode 26a is the first external electrode 24, the electrode 26b is one side end of the second external electrode 29, the electrode 27b is the other side end of the second external electrode 29, and the electrode 27a is the first external electrode 25. Each is electrically connected. Discharge electrode 2
Gap G between 6a and 26b and discharge electrode 27a,
The gaps G between the electrodes 27b are the same, and the electrodes 26a, 26b and 27a, 27a, 27a, 27a,
27b is sized to initiate the discharge. The method of forming these discharge electrodes is the same as in the first embodiment.
【００１２】このような構成の積層チップコンデンサ２
０では、第１実施例と同様にサージ電圧のような異常電
圧が印加されると、ギャップＧに臨む放電用電極２６
ａ，２６ｂ及び２７ａ，２７ｂの各先端に電界が集中す
る。この印加電圧が電極２６ａ，２６ｂ及び２７ａ，２
７ｂの放電開始電圧以上であれば、ここでスパークが発
生してチップコンデンサ２０の内部電極２２，２２間に
サージ電流を流さない。The multilayer chip capacitor 2 having such a structure
At 0, when an abnormal voltage such as a surge voltage is applied as in the first embodiment, the discharge electrode 26 facing the gap G is exposed.
The electric field is concentrated at the tips of a, 26b and 27a, 27b. This applied voltage is applied to the electrodes 26a, 26b and 27a, 2
If the discharge starting voltage of 7b is exceeded, a spark is generated here and no surge current flows between the internal electrodes 22 and 22 of the chip capacitor 20.
【００１３】なお、第１及び第２実施例ではベアチップ
の上面にのみ放電用電極を設けたが、誘電体層の絶縁破
壊強度に応じて、ベアチップの上下の両面に設けても、
或いは両側面に設けてもよく、放電用電極の数は上記例
に限るものではない。また、放電用電極の形状も鋸歯状
のものを対向させるなど、上記例に限定されない。更
に、第２実施例の積層チップコンデンサのアース電極２
８及び第２外部電極２９の形成方法は一例であって、本
発明はこれに限らず、他の公知の３端子型のチップコン
デンサにも適用することができる。Although the discharge electrodes are provided only on the upper surface of the bare chip in the first and second embodiments, they may be provided on both upper and lower surfaces of the bare chip depending on the dielectric breakdown strength of the dielectric layer.
Alternatively, they may be provided on both side surfaces, and the number of discharge electrodes is not limited to the above example. Further, the shape of the discharge electrode is not limited to the above example, for example, the sawtooth shape is opposed. Furthermore, the ground electrode 2 of the multilayer chip capacitor of the second embodiment.
The method of forming the second external electrode 29 and the second external electrode 29 is an example, and the present invention is not limited to this, and can be applied to other known three-terminal type chip capacitors.
【００１４】[0014]
【発明の効果】以上述べたように、従来の積層チップコ
ンデンサは、コンデンサ内部の誘電体層が絶縁破壊する
ような高いサージ電圧やパルスなどの異常電圧が印加さ
れる回路には単独で使用できなかったものが、ベアチッ
プの外面に放電用電極を設けることにより、サージアブ
ソーバと併用しなくても、また特殊な入出力端子を用い
なくても、絶縁破壊せずに単独で使用することができ
る。この結果、本発明の積層チップコンデンサを用いれ
ば、高い異常電圧を吸収し得るサージアブソーバを組込
めないような小型の回路や電子機器が実現できる。ま
た、本発明の積層チップコンデンサ単独で、サージ吸収
機能とノイズ除去機能を兼備することができる。更に、
放電用電極をベアチップの外面に導電性ペーストをスク
リーン印刷し乾燥した後、焼付けて形成すれば、所望の
ギャップが得られるとともに、チップ毎のギャップのば
らつきが小さくなり、放電用電極の放電開始電圧を正確
に決めることができる。As described above, the conventional multilayer chip capacitor can be used alone in a circuit to which an abnormal voltage such as a high surge voltage or pulse that causes dielectric breakdown of the dielectric layer inside the capacitor is applied. By providing a discharge electrode on the outer surface of the bare chip, it was possible to use it alone without dielectric breakdown without using it together with a surge absorber or using special input / output terminals. . As a result, by using the multilayer chip capacitor of the present invention, it is possible to realize a small circuit or electronic device in which a surge absorber capable of absorbing a high abnormal voltage cannot be incorporated. Further, the multilayer chip capacitor of the present invention alone can have both a surge absorbing function and a noise removing function. Furthermore,
If the discharge electrode is formed by screen-printing a conductive paste on the outer surface of the bare chip, drying it, and then baking it, a desired gap can be obtained, and the variation in the gap between chips is reduced, and the discharge start voltage of the discharge electrode is reduced. Can be accurately determined.
【図１】本発明第１実施例の放電ギャップ付き積層チッ
プコンデンサの図２のＡ−Ａ線断面図。FIG. 1 is a sectional view taken along line AA of FIG. 2 of a multilayer chip capacitor with a discharge gap according to a first embodiment of the present invention.
【図２】その外観斜視図。FIG. 2 is an external perspective view thereof.
【図３】本発明第２実施例の放電ギャップ付き積層チッ
プコンデンサの図４のＢ−Ｂ線断面図。3 is a sectional view taken along line BB of FIG. 4 of the multilayer chip capacitor with a discharge gap according to the second embodiment of the present invention.
【図４】その外観斜視図。FIG. 4 is an external perspective view thereof.
【図５】第２実施例の積層グリーン体の構成を示す斜視
図。FIG. 5 is a perspective view showing a configuration of a laminated green body according to a second embodiment.
Ｇ ギャップ １０，２０ 放電ギャップ付き積層チップコンデンサ １１，２１ 誘電体層 １２，２２ 内部電極 １３，２３ ベアチップ １４，１５，２４，２５ 第１外部電極 １６，１７，２６ａ，２６ｂ，２７ａ，２７ｂ 放電用
電極 ２８ アース電極 ２９ 第２外部電極G gap 10,20 Multi-layer chip capacitor with discharge gap 11,21 Dielectric layer 12,22 Internal electrode 13,23 Bare chip 14,15,24,25 First external electrode 16,17,26a, 26b, 27a, 27b For discharging Electrode 28 Earth electrode 29 Second external electrode
Claims (3)
積層して焼成一体化して形成されたベアチップ(13)と、
前記ベアチップ(13)の互いに対向する両端部に形成され
前記積層された複数の内部電極(12)に交互に電気的に接
続する一対の第１外部電極(14,15)とを備えた積層チッ
プコンデンサにおいて、 前記誘電体層(11)の絶縁破壊電圧よりも放電開始電圧の
低い一対の放電用電極(16,17)が所定のギャップ(G)をあ
けてかつ前記一対の外部電極(14,15)にそれぞれ電気的
に接続されて前記ベアチップ(13)の外面に形成されたこ
とを特徴とする放電ギャップ付き積層チップコンデン
サ。1. A bare chip (13) formed by alternately laminating dielectric layers (11) and internal electrodes (12) and firing them together,
A laminated chip having a pair of first external electrodes (14, 15) formed on opposite ends of the bare chip (13) and electrically connected to the laminated internal electrodes (12) alternately In the capacitor, a pair of discharge electrodes (16, 17) having a lower discharge starting voltage than the dielectric breakdown voltage of the dielectric layer (11) and a predetermined gap (G) and the pair of external electrodes (14, A multilayer chip capacitor with a discharge gap, which is electrically connected to each of 15) and formed on the outer surface of the bare chip (13).
外面に導電性ペーストを印刷乾燥後焼付けて形成された
請求項１記載の放電ギャップ付き積層チップコンデン
サ。2. The multilayer chip capacitor with a discharge gap according to claim 1, wherein the discharge electrodes (16, 17) are formed by printing, drying, and baking a conductive paste on the outer surface of the bare chip (13).
極(22)とを交互に積層して焼成一体化して形成されたベ
アチップ(23)と、前記ベアチップ(23)の互いに対向する
両端部に形成され前記積層された複数の内部電極(22)に
交互に電気的に接続する一対の第１外部電極(24,25)
と、前記一対の第１外部電極(24,25)の間のベアチップ
(23)の外周面に形成され前記アース電極(28)に電気的に
接続する第２外部電極(29)とを備えた積層チップコンデ
ンサにおいて、 前記誘電体層(21)の絶縁破壊電圧よりも放電開始電圧の
低い複数対の放電用電極(26a,26b,27a,27b)がそれぞれ
所定のギャップ(G)をあけてかつ前記第１及び第２外部
電極(24,25,29)にそれぞれ電気的に接続されて前記第１
外部電極(24,25)と前記第２外部電極(29)の間のベアチ
ップ(23)の外面に形成されたことを特徴とする放電ギャ
ップ付き積層チップコンデンサ。3. A bare chip (23) formed by alternately laminating a dielectric layer (21), an earth electrode (28) and an internal electrode (22) and firing them, and the bare chip (23) with respect to each other. A pair of first external electrodes (24, 25) formed at opposite ends and electrically connected to the plurality of laminated internal electrodes (22) alternately.
And a bare chip between the pair of first external electrodes (24, 25)
A multilayer chip capacitor provided with a second external electrode (29) formed on the outer peripheral surface of (23) and electrically connected to the ground electrode (28), wherein the dielectric breakdown voltage of the dielectric layer (21) is higher than that of the dielectric layer (21). A plurality of pairs of discharge electrodes (26a, 26b, 27a, 27b) having a low discharge start voltage are provided with a predetermined gap (G) and are electrically connected to the first and second external electrodes (24, 25, 29), respectively. First connected to the first
A multilayer chip capacitor with a discharge gap, which is formed on an outer surface of a bare chip (23) between an external electrode (24, 25) and the second external electrode (29).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3787793A JPH06251981A (en) | 1993-02-26 | 1993-02-26 | Multilayer chip capacitor provided with discharge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3787793A JPH06251981A (en) | 1993-02-26 | 1993-02-26 | Multilayer chip capacitor provided with discharge |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06251981A true JPH06251981A (en) | 1994-09-09 |
Family
ID=12509768
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3787793A Pending JPH06251981A (en) | 1993-02-26 | 1993-02-26 | Multilayer chip capacitor provided with discharge |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06251981A (en) |
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-
1993
- 1993-02-26 JP JP3787793A patent/JPH06251981A/en active Pending
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