JPH06244360A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPH06244360A JPH06244360A JP5027707A JP2770793A JPH06244360A JP H06244360 A JPH06244360 A JP H06244360A JP 5027707 A JP5027707 A JP 5027707A JP 2770793 A JP2770793 A JP 2770793A JP H06244360 A JPH06244360 A JP H06244360A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- chip
- stacked
- semiconductor elements
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 abstract description 6
- 229920005989 resin Polymers 0.000 abstract description 6
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/0651—Wire or wire-like electrical connections from device to substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
層してなる半導体装置であって、積層される半導体素子
3は、その周縁部が中央部に対して薄肉に形成された段
差6を有し、この周縁部にはワイヤ4が接続される電極
パッド7が形成されており、このように構成された半導
体素子を積層すると共に、前記電極パッド7に接続され
たワイヤを前記回路基板1に接続したことを特徴とする
半導体装置。 【効果】 チップのパッシベーション膜をチップ間の絶
縁膜に利用することにより厚さの薄い3次元積層実装体
を実現できる。
Description
半導体実装技術における半導体素子の積層実装技術に関
するものである。
小型化が著しく、そこに実装される半導体素子も高性能
化が進み、また高密度実装されることが要求されてい
る。このため、半導体素子を3次元的に実装するという
要求がIC、メモリーカードに代表される薄型、大容量
機器において顕著になってきている。
半導体素子の3次元実装方法の一例について説明する。
すものである。図3において、41は配線基板、42は
複数の半導体素子(または、単にチップと呼ぶこととす
る)、43は実装に用いられたTABリード、44は全
体の封止に用いられた絶縁封止樹脂である。
説明する。まず図4(a)に示すように、複数の半導体
素子42に転写バンプ法によりTAB用フィルムキャリ
ア45のインナーリード46を接続する。その後、複数
の半導体素子42のそれぞれの非共通端子のTAB用フ
ィルムキャリアのアウターリード47を切断する。次
に、TABフィルムキャリア45に実装された半導体素
子42を配線基板41の電極パッド48とTABフィル
ムキャリア45のアウターリード47を位置合わせし積
層する。その後、ボンディングツール49によりアウタ
ーリード47と配線基板41の電極パッド48を一括に
加圧、加熱し接合する。最後に、アウターリード47の
外側のテープ部分を取り除き、絶縁樹脂44により全体
を封止することにより、図3に示す3次元の実装体が完
成する。この様な製造方法は、例えば特開平2−290
048号公報に記載されている。
うな構成では、アウターリード47と配線基板41の電
極パッド48とを正確に位置合わせしなければならず、
またアウターリード47のボンディングにも特殊なボン
ディングツール49を使用しなければならないといった
問題点があり、またチップ間の絶縁層が必要であり、イ
ンナーリード46および層間絶縁樹脂の分だけ全体の厚
みが厚くなるといった問題を有していた。
わせ工程を必要とせず、チップの厚みのみでチップ積層
が可能な3次元実装形態を提供するものである。
めに本発明では、一主面の電極パッドにリード、または
ワイヤが接続された構造を持つ半導体素子片の、他面の
少なくとも電極パッド領域が切削され、他の部分に対し
薄くなるように段切りが形成された半導体素子片の複数
個を積層し、前記電極パッドに接続されたリードを回路
基板に接続した半導体装置を提案する。このとき、第一
の半導体素子片の第一の段部に第二の半導体素子片の電
極パッドとこれに接続されたリードの一部が配置され
る。
おいて、第一の半導体素子片の第一の段部に第二の半導
体素子片の電極パッドとこれに接続されたリードの一部
を配置する構成を繰り返すため、また、チップのパッシ
ベーシン膜をチップ間の絶縁膜に利用することによりチ
ップ厚さのチップ3次元積層実装を可能とすることがで
きる。
しながら説明する。
形態の断面図を示すものである。図1において、1は配
線基板、2は第1の半導体素子(または、単にチップと
呼ぶこととする。)、3は第1のチップの上に積層され
る裏面が切削された複数のチップ、4はワイヤ(実施例
ではリードではなくワイヤを用いた場合をモデルに説明
する。)、5は絶縁封止樹脂、6は切削された段部を表
す。
工程について、以下図2を用いて説明する。
(裏面が切削されていなくてもかまわない)を配線基板
1に接着し、対応する電極どうしをワイヤにより電気的
に接続する。次に、図2(b)に示す様に、第1のチッ
プ上に積載される第2、第3といったチップ3の裏面周
縁部をダイサーにより切削し、段部6を形成する。ワイ
ヤ4が接続される電極パッド7は、この周縁部に形成さ
れている。その後、図2(c)に示すように、この第
2、第3のチップ3をチップ1上に積層し、対応する電
極どうしをワイヤにより接続する。図2(d)は、図2
(c)の上面図である。最後に、図2(e)に示すよう
に、全体を絶縁樹脂により封止する。これにより半導体
素子2、3の配線基板1への3次元的実装が完了する。
は、第1のチップを基板上に載置した後に段差を形成し
ているが、第1のチップを基板上に載置する前に予め段
差を形成しておいても勿論かまわない。
チップにおける電極パッドは平坦な主面側に形成されて
いるが、段差6側に形成してもよいことは勿論である。
更には、図2における最下層のチップ2においても、周
縁部に段差があっても何等差し支えはなく、そうするこ
とにより、使用する半導体素子の形状を一種類に統一す
ることができるので、自動組立における半導体素子の形
状判別操作が省略できる等の利点が得られる。
極パッドにリード、またはワイヤが接続された構造を持
つ半導体素子片の、他面の少なくとも電極パッド領域が
他の部分に対し薄くなるように段切りが形成された半導
体素子片の複数個を第一の半導体素子片の第一の段部に
第二の半導体素子片の電極パッドとこれに接続されたリ
ードの一部が配置されるように積層し、前記電極パッド
に接続されたリードを回路基板に接続した半導体装置を
提案することにより、チップの積層においてチップのパ
ッシベーシン膜をチップ間の絶縁膜に利用することによ
りチップ厚さのチップ3次元積層実装を可能とすること
ができる。
示す断面図
Claims (1)
- 【請求項1】複数個の半導体素子を回路基板に積層して
なる半導体装置であって、積層される半導体素子は、そ
の周縁部が中央部に対して薄肉に形成されると共に前記
周縁部にはリード、またはワイヤが接続される電極パッ
ドが形成されており、このように構成された半導体素子
を積層すると共に、前記電極パッドに接続されたワイヤ
もしくはリードを前記回路基板に接続したことを特徴と
する半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5027707A JP2953899B2 (ja) | 1993-02-17 | 1993-02-17 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5027707A JP2953899B2 (ja) | 1993-02-17 | 1993-02-17 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06244360A true JPH06244360A (ja) | 1994-09-02 |
JP2953899B2 JP2953899B2 (ja) | 1999-09-27 |
Family
ID=12228471
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5027707A Expired - Fee Related JP2953899B2 (ja) | 1993-02-17 | 1993-02-17 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2953899B2 (ja) |
Cited By (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20000061035A (ko) * | 1999-03-23 | 2000-10-16 | 최완균 | 반도체 칩과 그의 제조 방법과 그 반도체 칩을 이용한 적층 칩패키지 및 그 적층 칩 패키지의 제조 방법 |
KR20030007098A (ko) * | 2001-07-11 | 2003-01-23 | 닛뽕덴끼 가부시끼가이샤 | 치수를 감소시킬 수 있는 적층형 칩-사이즈 패키지 반도체장치 |
US6576499B2 (en) | 1999-12-10 | 2003-06-10 | Nec Corporation | Electronic device assembly and a method of connecting electronic devices constituting the same |
KR100407472B1 (ko) * | 2001-06-29 | 2003-11-28 | 삼성전자주식회사 | 트렌치가 형성된 상부 칩을 구비하는 칩 적층형 패키지소자 및 그 제조 방법 |
US6657290B2 (en) | 2001-01-24 | 2003-12-02 | Sharp Kabushiki Kaisha | Semiconductor device having insulation layer and adhesion layer between chip lamination |
KR100379083B1 (ko) * | 1996-11-28 | 2004-02-05 | 앰코 테크놀로지 코리아 주식회사 | 리드온칩에어리어어레이범프드반도체패키지 |
US6777797B2 (en) | 2002-06-27 | 2004-08-17 | Oki Electric Industry. Co., Ltd. | Stacked multi-chip package, process for fabrication of chip structuring package, and process for wire-bonding |
JP2004356529A (ja) * | 2003-05-30 | 2004-12-16 | Renesas Technology Corp | 半導体装置および半導体装置の製造方法 |
KR100464561B1 (ko) * | 2000-04-11 | 2004-12-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 이것의 제조방법 |
KR100525450B1 (ko) * | 2001-02-14 | 2005-11-02 | 앰코 테크놀로지 코리아 주식회사 | 반도체 칩 적층형 반도체 패키지 |
US7067926B2 (en) | 2002-12-19 | 2006-06-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor chip and method for manufacturing the same |
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