JPH06232412A - Nonvolatile memory cell - Google Patents
Nonvolatile memory cellInfo
- Publication number
- JPH06232412A JPH06232412A JP1984693A JP1984693A JPH06232412A JP H06232412 A JPH06232412 A JP H06232412A JP 1984693 A JP1984693 A JP 1984693A JP 1984693 A JP1984693 A JP 1984693A JP H06232412 A JPH06232412 A JP H06232412A
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- drain
- gate electrode
- voltage
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/561—Multilevel memory cell aspects
- G11C2211/5612—Multilevel memory cell with more than one floating gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は不揮発性メモリセルに関
する。FIELD OF THE INVENTION The present invention relates to non-volatile memory cells.
【０００２】[0002]
【従来の技術】図５に従来の不揮発性メモリセルの断面
図であり、その断面はトランジスタ部のチャネル幅と直
交する方向である。図５に示すように、２段縦積み階段
ゲート絶縁膜型不揮発性メモリセル４３は、Ｐ型シリコ
ン基板４２のソース４０とドレイン４１間に不均一な厚
さから成るゲート酸化膜３９を介してシリコン窒化膜３
８と制御電極３７が形成され構成されている（特願昭４
６−９７２８７号）。2. Description of the Related Art FIG. 5 is a cross-sectional view of a conventional non-volatile memory cell, the cross section being in a direction orthogonal to the channel width of a transistor portion. As shown in FIG. 5, the two-stage vertically stacked staircase gate insulating film type nonvolatile memory cell 43 has a gate oxide film 39 having a non-uniform thickness between the source 40 and the drain 41 of the P-type silicon substrate 42. Silicon nitride film 3
8 and a control electrode 37 are formed (Japanese Patent Application No. 4).
6-97287).
【０００３】[0003]
【発明が解決しようとする課題】従来の２段縦積み階段
ゲート絶縁膜型不揮発性メモリセルは、ソース・ドレイ
ン端上部シリコン窒化膜への書き込み注入量の偏りを防
止する目的で作成されており、ゲート絶縁膜の厚みの違
いを利用して、メモリセルの多値化を図るものはない。The conventional two-stage vertically stacked staircase gate insulating film type non-volatile memory cell is formed for the purpose of preventing uneven distribution of the write injection amount into the upper silicon nitride film at the source / drain end. There is nothing to achieve multi-valued memory cells by utilizing the difference in thickness of the gate insulating film.
【０００４】２段縦積み階段ゲート絶縁膜型構造を利用
して不揮発性メモリセルへの書き込み注入量の多値化を
図る場合には、階段形状のゲート絶縁膜上部の制御電極
の電圧を変化させることにより注入電荷の変化を生させ
て行う。従来、この書き込み注入量を制御するためには
制御電極からの印加電圧を大きく変化させていた（１９
９２年秋季応用物理学会、予稿集 17a-ZS-9,10）。In order to increase the write injection amount into the nonvolatile memory cell by utilizing the two-stage vertically stacked staircase gate insulating film type structure, the voltage of the control electrode above the staircase-shaped gate insulating film is changed. By doing so, a change in injected charge is generated. Conventionally, in order to control the write injection amount, the applied voltage from the control electrode is largely changed (19
1992 Autumn Society of Applied Physics, Proceedings 17a-ZS-9, 10).
【０００５】しかしゲート絶縁膜が薄膜化すると、制御
電極からの印加電圧のわずかな変化により書き込み注入
量に大きなばらつきが生じ、注入量の電圧だけによる制
御に限界がある。However, when the gate insulating film is thinned, a slight change in the voltage applied from the control electrode causes a large variation in the write injection amount, and there is a limit to the control by only the injection amount voltage.
【０００６】また、ゲート絶縁膜を階段形状の厚さに形
成することは非常に困難である。従って、従来の２段縦
積み階段ゲート絶縁膜型不揮発性メモリセルにおいては
制御電極からの印加電圧の変化により、書き込み注入量
の多値化を図るには精度が悪いという問題点があった。Further, it is very difficult to form the gate insulating film to have a stepped thickness. Therefore, in the conventional two-stage vertically stacked staircase gate insulating film type non-volatile memory cell, there is a problem in that it is not accurate to achieve multi-valued write injection amount due to a change in the voltage applied from the control electrode.
【０００７】本発明は上記問題点を解決することができ
る不揮発性メモリセルを提供するものである。The present invention provides a non-volatile memory cell that can solve the above problems.
【０００８】[0008]
【課題を解決するための手段】本発明は、第１導電型半
導体基板に形成された第２導電型の一対の高濃度不純物
領域即ちソース及びドレインと、このソース、ドレイン
の上部に一対の厚みの異なる薄い絶縁膜を介してフロー
ティングゲート電極を、さらにソース、ドレイン間に上
記厚みの異なる薄い絶縁膜よりも厚い絶縁膜を介して制
御電極が形成された不揮発性メモリセルにおいて、薄い
絶縁膜を有するソース側を、制御電極からの１０Ｖ程度
の電圧印加によりソースからのトンネル電流を流せる程
度に薄く形成し、ソース側の絶縁膜よりも厚い絶縁膜を
有するドレイン側を、制御電極からの１５Ｖ程度の電圧
印加によりドレインからのトンネル電流を流せる程度に
厚く形成する。According to the present invention, a pair of high-concentration impurity regions of the second conductivity type, that is, a source and a drain, formed on a semiconductor substrate of the first conductivity type, and a pair of thicknesses above the source and the drain. In a non-volatile memory cell in which a floating gate electrode is formed through a thin insulating film of different thickness, and a control electrode is formed between a source and a drain through an insulating film thicker than the thin insulating film of different thickness described above, a thin insulating film is formed. The source side is thinly formed so that a tunnel current from the source can flow by applying a voltage of about 10 V from the control electrode, and the drain side having an insulating film thicker than the insulating film on the source side is about 15 V from the control electrode. It is formed thick enough to pass the tunnel current from the drain by applying the voltage.
【０００９】この厚みの異なる絶縁膜の厚さは例えば各
々１０ｎｍ、１５ｎｍ程度が良いが、少なくとも制御電
極への１０Ｖ程度の電圧印加により、ソースからフロー
ティングゲート電極に、トンネル電流が流れる厚さに設
定する。また、制御電極への１５Ｖの程度の電圧印加に
より、ソースとドレインの両方からフローティングゲー
ト電極にトンネル電流が流れる厚さに設定する。さら
に、ゲート絶縁膜の厚さは制御電極からの電圧印加によ
りソースからドレインに、チャネル電流が流れる厚さ、
例えば２０ｎｍ程度に設定する。The thicknesses of the insulating films having different thicknesses are, for example, about 10 nm and 15 nm, respectively, but are set to a thickness at which a tunnel current flows from the source to the floating gate electrode by applying a voltage of at least about 10 V to the control electrode. To do. Further, by applying a voltage of about 15 V to the control electrode, the thickness is set to a thickness at which the tunnel current flows from both the source and the drain to the floating gate electrode. Furthermore, the thickness of the gate insulating film is the thickness at which the channel current flows from the source to the drain by applying a voltage from the control electrode,
For example, it is set to about 20 nm.
【００１０】[0010]
【作用】本発明によれば、一対の高濃度不純物領域上部
の各々の絶縁膜が臨界点の異なる電圧によりトンネル電
流が流れるように極めて薄く且つ厚みが異なるよう形成
されているため、制御電極に１０Ｖ程度の電圧を印加す
る書き込み時にはこの高濃度不純物領域の一方、即ちソ
ースからフローティングゲート電極に電荷が注入され、
１５Ｖ程度の電圧を印加する書き込み時にはこの高濃度
不純物領域の両方、即ちソース及びドレインからフロー
ティングゲート電極に電荷が注入される。また、一対の
高濃度不純物領域間では少なくともチャネル電流が流れ
る程度に酸化膜が厚く形成されているため制御電極に５
V、ドレインに１V程度の電圧を印加する読み出し時に
は、フローティングゲート電極に書き込まれた電荷を保
持したまま、ソースからドレインに必要且つ十分なチャ
ネル電流が流れる。According to the present invention, the insulating films above the pair of high-concentration impurity regions are formed so as to be extremely thin and have different thicknesses so that the tunnel currents flow by the voltages having different critical points. At the time of writing in which a voltage of about 10 V is applied, charges are injected from one of the high concentration impurity regions, that is, the source, to the floating gate electrode,
At the time of writing in which a voltage of about 15 V is applied, charges are injected from both of the high-concentration impurity regions, that is, the source and drain into the floating gate electrode. In addition, since the oxide film is formed between the pair of high-concentration impurity regions so thick that at least the channel current flows, the control electrode has 5
At the time of reading by applying a voltage of about 1 V to V and drain, a necessary and sufficient channel current flows from the source to the drain while holding the charges written in the floating gate electrode.
【００１１】[0011]
【実施例】以下本発明の一実施例の不揮発性メモリセル
について、図面を参照しながら説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A non-volatile memory cell according to an embodiment of the present invention will be described below with reference to the drawings.
【００１２】図１A、B、Cは本発明の実施例における不
揮発性メモリセルの製法例、図２A、B、C、Dは不揮発性
メモリセルの書き込み時、読みだし時、消去時の電極の
制御と電荷との関係からメモリセルの動作を示すもので
ある。図３は、本発明の実施例における不揮発性メモリ
セルの、書き込み時の制御電極からの印加電圧の変化と
そのときの注入電荷の変化の関係を示すものである。図
４は、本発明の実施例における不揮発性メモリセルの、
読み出し時のチャネル電流特性図である。図５は本発明
の従来例における２段縦積み階段ゲート絶縁膜型不揮発
性メモリセルの構造断面図である。1A, 1B, 1C show an example of a method of manufacturing a non-volatile memory cell according to an embodiment of the present invention, and FIGS. 2A, 2B, 2C, 2D show electrodes of a non-volatile memory cell during writing, reading and erasing. The operation of the memory cell is shown from the relationship between control and electric charge. FIG. 3 shows the relationship between the change of the applied voltage from the control electrode during writing and the change of the injected charge at that time in the nonvolatile memory cell in the example of the present invention. FIG. 4 shows a nonvolatile memory cell according to an embodiment of the present invention.
It is a channel current characteristic diagram at the time of reading. FIG. 5 is a structural cross-sectional view of a two-stage vertically stacked staircase gate insulating film type nonvolatile memory cell in a conventional example of the present invention.
【００１３】図１A、B、C、図２A、B、C、D、図３、図
５において１は不揮発性メモリセル、１１はP型シリコ
ン基板、１２は厚い熱酸化膜、１４はコントロールゲー
ト電極、１５A、１５Bは薄い熱酸化膜、１７A、１７Bは
フローティングゲート電極，１８は層間絶縁膜、２０S
はソース電極、２０Dはドレイン電極、２９はチャネ
ル、３０A、３０Bはエレクトロン、３１A、３１Bは寄生
抵抗、３７は制御電極、３８はシリコン窒化膜、３９は
ゲート酸化膜、４０はソース、４１はドレイン、４２は
シリコン基板、４３は不揮発性メモリセルを示す。1A, B, C, 2A, B, C, D, 3 and 5, 1 is a non-volatile memory cell, 11 is a P-type silicon substrate, 12 is a thick thermal oxide film, and 14 is a control gate. Electrodes, 15A and 15B are thin thermal oxide films, 17A and 17B are floating gate electrodes, 18 is an interlayer insulating film, 20S
Is a source electrode, 20D is a drain electrode, 29 is a channel, 30A and 30B are electrons, 31A and 31B are parasitic resistances, 37 is a control electrode, 38 is a silicon nitride film, 39 is a gate oxide film, 40 is a source, and 41 is a drain. , 42 is a silicon substrate, and 43 is a non-volatile memory cell.
【００１４】以下図１を用いて実施例を製法例と共に説
明する。まず図１Aに示すように、導電型例えばP型シリ
コン基板１１の全面にゲート酸化膜即ち、厚い熱酸化膜
１２を形成した後、ポリシリコンをCVD法により成長さ
せてコントロールゲート層を形成し、次に写真食刻法を
用いてコントロールゲート電極１４を所定のパターンに
エッチングする。 そして、このコントロールゲート電
極１４をマスクとしてヒ素イオンAs＋を注入して高濃度
不純物領域即ちソース２４、ドレイン２５を形成する。An embodiment and a manufacturing method will be described below with reference to FIG. First, as shown in FIG. 1A, after forming a gate oxide film, that is, a thick thermal oxide film 12 on the entire surface of a conductive type, for example, P type silicon substrate 11, polysilicon is grown by a CVD method to form a control gate layer, Next, the control gate electrode 14 is etched into a predetermined pattern by using a photolithography method. Then, using the control gate electrode 14 as a mask, arsenic ions As + are implanted to form high-concentration impurity regions, that is, the source 24 and the drain 25.
【００１５】次に図１Bに示すように、全面に熱酸化膜
を形成し、写真食刻法を用いてソース・ドレイン上部の
絶縁膜を所定の厚みの薄い熱酸化膜１５Aになるようエ
ッチングする。次に全面に薄い熱酸化膜１５Bを形成
し、続けてドレイン側にレジストを堆積した後、写真食
刻法を用いてドレイン上部以外の上記薄い熱酸化膜１５
Bをエッチングし、結果としてゲート酸化膜よりも薄く
形成する。続けてポリシリコンをCVD法により成長させ
てフローティングゲート層を形成した後、異方性エッチ
ングにより上記コントロールゲート電極１４の側壁にフ
ローティングゲート電極１７A、１７Bを形成する。Next, as shown in FIG. 1B, a thermal oxide film is formed on the entire surface, and the insulating film above the source / drain is etched to a thin thermal oxide film 15A having a predetermined thickness by photolithography. . Next, a thin thermal oxide film 15B is formed on the entire surface, a resist is continuously deposited on the drain side, and then the thin thermal oxide film 15 other than the upper portion of the drain is formed by photolithography.
B is etched, resulting in a thinner layer than the gate oxide. Subsequently, polysilicon is grown by the CVD method to form a floating gate layer, and then anisotropic etching is performed to form the floating gate electrodes 17A and 17B on the sidewalls of the control gate electrode 14.
【００１６】次に図１Cに示すように層間膜１８、ソー
ス電極２０S及びドレイン電極２０Dを形成し本発明に関
わる不揮発性メモリセル１の構造を得る。Next, as shown in FIG. 1C, the interlayer film 18, the source electrode 20S and the drain electrode 20D are formed to obtain the structure of the nonvolatile memory cell 1 according to the present invention.
【００１７】次に、この不揮発性メモリの動作について
図２を用いて説明する。図２Aに示すように上記の製法
により得られた不揮発性メモリセル１（ソース、ドレイ
ン電極は図示せず）のコントロールゲート電極１４とソ
ース２４とドレイン２５に各々に例えば１０ボルト、０
ボルト、０ボルト程度の電圧を印加すると、ソース２４
からみたコントロールゲート電極１４方向へのゲート酸
化膜即ち薄い熱酸化膜１５Aのエレクトロンに対するエ
ネルギ障壁が実効的に低くなり、フローティングゲート
電極１７Aとソース２４各々との間をエレクトロンがト
ンネリングしフローティングゲート電極１７Aにエレク
トロン３０Aが注入される。Next, the operation of this nonvolatile memory will be described with reference to FIG. As shown in FIG. 2A, the control gate electrode 14, the source 24, and the drain 25 of the nonvolatile memory cell 1 (source and drain electrodes not shown) obtained by the above-described manufacturing method are respectively supplied with 10 V, 0, respectively.
When a voltage of about 0 V is applied, the source 24
The energy barrier to electrons of the gate oxide film, that is, the thin thermal oxide film 15A toward the control gate electrode 14 when viewed is effectively lowered, and the electrons tunnel between the floating gate electrode 17A and the source 24 to cause floating gate electrode 17A. Electrons 30A are injected into.
【００１８】次に図２Bに示すようにコントロールゲー
ト電極１４とソース２４とドレイン２５に各々に例えば
１５ボルト、０ボルト、０ボルト程度の電圧を印加する
と、ソース２４及びドレイン２５からみたコントロール
ゲート電極１４方向へのゲート酸化膜即ち薄い熱酸化膜
１５Bのエレクトロンに対するエネルギ障壁が実効的に
低くなり、フローティングゲート電極１７Aとソース２
４、フローティングゲート電極１７Bとドレイン２５各
々との間をエレクトロンがトンネリングしフローティン
グゲート電極１７Aとフローティングゲート電極１７Bに
エレクトロン３０Bが注入されメモリセルに２値の情報
が書き込まれることになる。Next, as shown in FIG. 2B, when a voltage of, for example, about 15 volts, 0 volts, or 0 volts is applied to the control gate electrode 14, the source 24, and the drain 25, the control gate electrode viewed from the source 24 and the drain 25. The energy barrier to electrons of the gate oxide film in the 14 direction, that is, the thin thermal oxide film 15B is effectively lowered, and the floating gate electrode 17A and the source 2
4. Electrons tunnel between the floating gate electrode 17B and the drain 25, electrons 30B are injected into the floating gate electrode 17A and the floating gate electrode 17B, and binary information is written in the memory cell.
【００１９】このようにコントロールゲート電極１４に
印加する２種類の電圧により、フローティングゲート電
極１７Ａ,１７Ｂにエレクトロンが蓄積されるのでメモ
リセルに２値の情報が書き込まれる。Electrons are accumulated in the floating gate electrodes 17A and 17B by the two kinds of voltages applied to the control gate electrode 14 in this manner, so that binary information is written in the memory cell.
【００２０】次に図２Cに示すように不揮発性メモリセ
ル１のコントロールゲート電極１４に例えば５ボルト、
ドレイン２４に１ボルト程度の電圧を各々印加すること
によりチャネル２９が形成される。このチャネル電流値
は図４に示すようにフローティングゲート電極１７A、B
に注入されているエレクトロン３０A、Bの量に起因する
ドレイン２５、ソース２４の寄生抵抗３１A、３１Bに支
配され、この値をもとに不揮発性メモリセル１の”２”
と”１”及び”０”の状態を読み出す。Next, as shown in FIG. 2C, the control gate electrode 14 of the nonvolatile memory cell 1 has, for example, 5 volts,
A channel 29 is formed by applying a voltage of about 1 volt to the drain 24, respectively. This channel current value is, as shown in FIG. 4, floating gate electrodes 17A, B.
Is controlled by the parasitic resistances 31A and 31B of the drain 25 and the source 24, which are caused by the amount of electrons 30A and B injected into the non-volatile memory cell 1.
And the states of "1" and "0" are read.
【００２１】次に図２Dに示すように不揮発性メモリセ
ル１のコントロールゲート電極１４に−１５ボルト程度
の電圧を印加すると、フローティングゲート電極１７
A、１７Bからエレクトロン３０A、３０Bがソース２４及
びドレイン２５にトンネリングにより放出され、メモリ
セルから消去される。Next, as shown in FIG. 2D, when a voltage of about -15 V is applied to the control gate electrode 14 of the non-volatile memory cell 1, the floating gate electrode 17 is formed.
Electrons 30A and 30B are emitted from A and 17B to the source 24 and the drain 25 by tunneling and erased from the memory cell.
【００２２】図３にコントロールゲート電極からの印加
電圧とフローティングゲート電極への注入電荷の２値化
の関係を示す。コントロールゲート電圧により、注入電
荷が変化していることがわかる。これを利用して注入電
荷のばらつきが重なりあわない範囲でコントロールゲー
ト電圧を設定すれば、２値のメモリセルを構成できる。FIG. 3 shows the relationship between the voltage applied from the control gate electrode and the binarization of the charge injected into the floating gate electrode. It can be seen that the injected charge changes depending on the control gate voltage. By utilizing this, a binary memory cell can be constructed by setting the control gate voltage within a range where variations in injected charges do not overlap.
【００２３】また蓄積した電荷の読みだしも、図４に示
すとおり、メモリセルに蓄積した電荷の大きさによっ
て、ドレイン電圧が一定であってもドレイン電流が異な
るので、２値の値を読み出すことができる。ドレイン電
流が異なるのは、図２(c)で示した通り、フローティン
グゲート電極に蓄積したエレクトロンの量によって、ソ
ース、ドレインの寄生抵抗が異なるためである。つま
り、コントロールゲート電極１４に電圧を印加して、チ
ャネルを形成しても、フローティングゲートに蓄積した
エレクトロンの量により寄生抵抗が異なり、ドレイン電
圧が一定であってもドレイン電流は異なるのである。Further, as shown in FIG. 4, the reading of the accumulated charge also depends on the magnitude of the accumulated charge in the memory cell, because the drain current is different even if the drain voltage is constant. You can The drain current is different because the parasitic resistance of the source and drain is different depending on the amount of electrons accumulated in the floating gate electrode, as shown in FIG. That is, even if a voltage is applied to the control gate electrode 14 to form a channel, the parasitic resistance varies depending on the amount of electrons accumulated in the floating gate, and the drain current varies even if the drain voltage is constant.
【００２４】[0024]
【発明の効果】以上のように本発明によれば、高濃度不
純物間半導体基板上部の絶縁膜より薄い範囲で一対の高
濃度不純物領域上部に一対の異なる厚さの絶縁膜を設け
ることにより、メモリセルの容易に多値化を図る。As described above, according to the present invention, by providing a pair of insulating films having different thicknesses above a pair of high-concentration impurity regions in a range thinner than the insulating film above the high-concentration impurity semiconductor substrate, A memory cell can be easily multi-valued.
【００２５】さらにこのとき不揮発性メモリセルの書き
込み、読みだし、消去のための電気的制御は極めて単純
化され、かつ、フローティングゲート電極への注入及び
放出電荷を精度良く制御することができる。また、高濃
度不純物領域からのトンネル電流は制御電極内には注入
されず、MOSFET特性は劣化しない。Further, at this time, electrical control for writing, reading, and erasing of the nonvolatile memory cell is extremely simplified, and injection and emission charges to the floating gate electrode can be controlled with high accuracy. Further, the tunnel current from the high-concentration impurity region is not injected into the control electrode, and the MOSFET characteristics are not deteriorated.
【図１】本発明の第１の実施例における不揮発性メモリ
セルの製法例を示す工程図FIG. 1 is a process drawing showing an example of a method of manufacturing a nonvolatile memory cell according to a first embodiment of the present invention.
【図２】本発明の第１の実施例における不揮発性メモリ
セルの書き込み、読み出し、消去の動作を示す断面構造
図FIG. 2 is a sectional structural view showing the write, read, and erase operations of the nonvolatile memory cell according to the first embodiment of the present invention.
【図３】本発明の第１の実施例における不揮発性メモリ
セルの書き込み時の制御電極からの印加電圧と注入電荷
量の関係図FIG. 3 is a diagram showing a relationship between an applied voltage from a control electrode and an amount of injected charges when writing data in the nonvolatile memory cell according to the first embodiment of the present invention.
【図４】本発明の第１の実施例における不揮発性メモリ
セルの読み出し時のドレイン電流特性図FIG. 4 is a drain current characteristic diagram during reading of the nonvolatile memory cell according to the first embodiment of the present invention.
【図５】本発明の従来例を示す２段縦積み階段ゲート絶
縁膜型不揮発性メモリセルの断面構造図FIG. 5 is a cross-sectional structural view of a two-stage vertically stacked staircase gate insulating film type nonvolatile memory cell showing a conventional example of the present invention.
１ 不揮発性メモリセル １１ P型シリコン基板 １２ 厚い熱酸化膜 １４ コントロールゲート電極 １５A 薄い熱酸化膜 １５B 薄い熱酸化膜 １７A フローティングゲート電極 １７B フローティングゲート電極 １８ 層間絶縁膜 ２０S ソース ２０D ドレイン ２９ チャネル ３０A エレクトロン ３０B エレクトロン ３１A 寄生抵抗 ３１B 寄生抵抗 ３７ 制御電極 ３８ シリコン窒化膜 ３９ ゲート酸化膜 ４０ ソース ４１ ドレイン ４２ シリコン基板 ４３ 不揮発性メモリセル 1 Non-Volatile Memory Cell 11 P-Type Silicon Substrate 12 Thick Thermal Oxide Film 14 Control Gate Electrode 15A Thin Thermal Oxide Film 15B Thin Thermal Oxide Film 17A Floating Gate Electrode 17B Floating Gate Electrode 18 Interlayer Insulation Film 20S Source 20D Drain 29 Channel 30A Electron 30B Electron 31A Parasitic resistance 31B Parasitic resistance 37 Control electrode 38 Silicon nitride film 39 Gate oxide film 40 Source 41 Drain 42 Silicon substrate 43 Non-volatile memory cell
Claims (1)
半導体基板に第２導電型の一対の高濃度不純物領域と、
前記不純物領域の上部に一対の厚みの異なる薄い絶縁膜
を介してフローティングゲート電極を設け、前記一対の
高濃度不純物領域間に前記第１導電型半導体基板と前記
一対の厚みの異なる薄い絶縁膜よりも厚い絶縁膜を介し
て、制御電極が形成されていることを特徴とする不揮発
性メモリセル。1. A semiconductor substrate of a first conductivity type, and a pair of high-concentration impurity regions of a second conductivity type on the semiconductor substrate of the first conductivity type,
A floating gate electrode is provided on the impurity region via a pair of thin insulating films having different thicknesses, and the first conductive type semiconductor substrate and the pair of thin insulating films having different thicknesses are provided between the pair of high concentration impurity regions. A non-volatile memory cell having a control electrode formed through a thick insulating film.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984693A JPH06232412A (en) | 1993-02-08 | 1993-02-08 | Nonvolatile memory cell |
| EP93113747A EP0590319B1 (en) | 1992-10-02 | 1993-08-27 | A non-volatile memory cell |
| DE69316298T DE69316298T2 (en) | 1992-10-02 | 1993-08-27 | Non-volatile memory cell |
| US08/245,253 US5424979A (en) | 1992-10-02 | 1994-05-17 | Non-volatile memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984693A JPH06232412A (en) | 1993-02-08 | 1993-02-08 | Nonvolatile memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06232412A true JPH06232412A (en) | 1994-08-19 |
Family
ID=12010626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984693A Pending JPH06232412A (en) | 1992-10-02 | 1993-02-08 | Nonvolatile memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06232412A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7164167B2 (en) | 2001-11-21 | 2007-01-16 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
-
1993
- 1993-02-08 JP JP1984693A patent/JPH06232412A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7164167B2 (en) | 2001-11-21 | 2007-01-16 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
| US7582926B2 (en) | 2001-11-21 | 2009-09-01 | Sharp Kabushiki Kaisha | Semiconductor storage device, its manufacturing method and operating method, and portable electronic apparatus |
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