JPH06232332A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06232332A
JPH06232332A JP1985393A JP1985393A JPH06232332A JP H06232332 A JPH06232332 A JP H06232332A JP 1985393 A JP1985393 A JP 1985393A JP 1985393 A JP1985393 A JP 1985393A JP H06232332 A JPH06232332 A JP H06232332A
Authority
JP
Japan
Prior art keywords
circuit
semiconductor chip
esd
inner leads
diode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1985393A
Other languages
Japanese (ja)
Inventor
Yoshinori Atsuwata
好則 厚綿
Hidezo Kaneko
秀蔵 金子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1985393A priority Critical patent/JPH06232332A/en
Publication of JPH06232332A publication Critical patent/JPH06232332A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To realize the improvement of an ESD strength and an LU strength by a method wherein a resistor, an inductor, a capacitor and a diode are respectively mounted on inner leads and ESD protective circuits and LU generation preventive circuits are respectively formed on the inner leads. CONSTITUTION:Insulating sheet 9 is respectively jointed to the surfaces of inner leads 5, a single components of a resistor 1, an inductor 2, a capacitor 3 or a diode 4 or a semiconductor chip 10, including an ESD protective circuit and an LU generation preventive circuit, is mounted on the sheet 9 and the ESD protective circuit and the LU generation preventive circuit are constituted. Thereby, the improvement of an ESD resistance and an LU resistance can be realized. Moreover, by constituting respectively the ESD protective circuit and the LU generation preventive circuit on the inner lead parts and the inner leads miniaturization of the chip 10 and an increase in the integration degree the chip 10 can be realized because there is no need to form the ESD protective circuit and the LU generation preventive circuit in the interior of the semiconductor chip.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、ＩＣ，ＬＳＩの静電破
壊（ＥＳＤ），ラッチアップ（ＬＵ）耐量等の電気的特
性の向上を実現する有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an effective technique for improving electric characteristics such as electrostatic breakdown (ESD) and latch-up (LU) resistance of ICs and LSIs.

【０００２】[0002]

【従来の技術】従来の技術は、特願昭57−160002号に示
すように、インナーリード間にテープ状の抵抗，容量を
取り付けることによって、半導体チップ外に取り付ける
外部接続部品数を減らすことを目的としたものである。
従って、抵抗，容量のみでは、静電気ノイズを回避する
ことは困難であろう。また、半導体チップ内のＥＳＤ保
護とＬＵ発生防止に用いる電気回路素子である抵抗，容
量を半導体チップ外に取り出すものではなく、半導体チ
ップの小型化は実現できなかった。2. Description of the Related Art In the prior art, as shown in Japanese Patent Application No. 57-160002, it is possible to reduce the number of external connection parts to be mounted on the outside of a semiconductor chip by mounting tape-shaped resistors and capacitors between inner leads. It is intended.
Therefore, it will be difficult to avoid static electricity noise only with resistors and capacitors. Further, the resistance and capacitance, which are electric circuit elements used for ESD protection in the semiconductor chip and prevention of LU generation, are not taken out of the semiconductor chip, and miniaturization of the semiconductor chip cannot be realized.

【０００３】さらに、現状のＬＳＩのインナーリードで
は、本構造に示す抵抗，容量等の部品取り付けは困難で
ある。Furthermore, it is difficult to attach the components such as the resistance and capacitance shown in this structure to the inner leads of the current LSI.

【０００４】[0004]

【発明が解決しようとする課題】半導体チップを製作す
るには、ＥＳＤ保護回路，ＬＵ防止回路を半導体チップ
内部に形成している。しかし、半導体チップ内部のみで
は、ＥＳＤ，ＬＵ耐量を向上させるのに限界があった。
さらに、半導体チップの小型，高集積化を図る上でも、
半導体チップのみで充分なＥＳＤ保護回路および、ＬＵ
発生防止回路を形成することは困難となっていた。この
ため、半導体チップのＥＳＤとＬＵ耐量をより向上する
ことが課題であった。To manufacture a semiconductor chip, an ESD protection circuit and an LU prevention circuit are formed inside the semiconductor chip. However, there is a limit in improving the ESD and LU withstand capability only inside the semiconductor chip.
Furthermore, in terms of miniaturization and high integration of semiconductor chips,
An ESD protection circuit and LU that are sufficient only with a semiconductor chip
It has been difficult to form an occurrence prevention circuit. Therefore, it has been a problem to further improve the ESD and LU withstand capability of the semiconductor chip.

【０００５】[0005]

【課題を解決するための手段】従来の半導体装置の半導
体チップ内で形成しているＥＳＤ保護回路および、ＬＵ
発生防止回路を使用せずに、本発明の半導体装置によっ
て、課題を解決したものである。An ESD protection circuit and an LU formed in a semiconductor chip of a conventional semiconductor device.
The problem is solved by the semiconductor device of the present invention without using an occurrence prevention circuit.

【０００６】さらに、従来の半導体チップの内部に形成
したＥＳＤ保護回路および、ＬＵ発生防止回路と本発明
を併用することによって、課題を解決したものである。Further, the problem is solved by using the present invention together with the conventional ESD protection circuit and LU generation prevention circuit formed inside the semiconductor chip.

【０００７】本発明の半導体装置の構造は、インナーリ
ード上部にインナーリードが短絡しないように絶縁シー
トをはりつけ、この絶縁シート上に抵抗，インダクタン
ス，容量，ダイオード等の単体部品あるいは、ＥＳＤ保
護回路，ＬＵ発生防止回路を有する半導体チップを取付
けることによって、ＥＳＤ保護とＬＵ発生防止等の特性
改善を達成したものである。According to the structure of the semiconductor device of the present invention, an insulating sheet is attached to the upper portion of the inner lead so that the inner lead is not short-circuited. By mounting a semiconductor chip having an LU generation prevention circuit, characteristic improvements such as ESD protection and LU generation prevention are achieved.

【０００８】[0008]

【作用】上記の手段によって製作した半導体装置のＥＳ
Ｄ保護回路は、インナーリード上部の抵抗，ダイオー
ド，インダクタンスによって、ＥＳＤ保護回路を構成し
て達成できる。The ES of the semiconductor device manufactured by the above means
The D protection circuit can be achieved by forming an ESD protection circuit by the resistance, the diode and the inductance on the upper part of the inner lead.

【０００９】さらに、半導体チップ内部にＥＳＤ保護回
路を有するものは、インナーリード上部の絶縁シート上
の抵抗，ダイオード，インダクタンスによって構成され
たＥＳＤ保護回路とを併用することによって達成でき
る。Further, a semiconductor chip having an ESD protection circuit can be achieved by using in combination with an ESD protection circuit composed of a resistor, a diode and an inductance on the insulating sheet above the inner lead.

【００１０】一方、ＬＵ発生防止についても、絶縁シー
ト上の抵抗，ダイオード，インダクタンス等の部品でＬ
Ｕ発生防止回路を構成して達成できる。On the other hand, with respect to prevention of LU generation, parts such as resistors, diodes, and inductances on the insulating sheet are used as L
This can be achieved by configuring a U generation prevention circuit.

【００１１】さらに、半導体チップ内部にＬＵ発生防止
回路を有するものは、インナーリード上部の抵抗，ダイ
オード，インダクタンス等の部品で構成されたＬＵ発生
防止回路を併用することによって達成できる。Further, a semiconductor chip having an LU generation prevention circuit can be achieved by using an LU generation prevention circuit which is composed of parts such as a resistor, a diode and an inductance above the inner lead.

【００１２】[0012]

【実施例】以下、本発明の実施例を図１により説明す
る。図１に示すように、インナーリード５の表面に絶縁
シート９を貼り、この絶縁シート９上に、抵抗１，イン
ダクタンス２，容量３，ダイオード４の単体部品、ある
いは、ＥＳＤ保護回路，ＬＵ発生防止回路を有する半導
体チップ１０を取り付けて、ＥＳＤ保護回路および、Ｌ
Ｕ発生防止回路を構成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. As shown in FIG. 1, an insulating sheet 9 is attached to the surface of the inner lead 5, and on the insulating sheet 9, a single component of a resistor 1, an inductance 2, a capacitor 3 and a diode 4, or an ESD protection circuit, LU generation prevention. A semiconductor chip 10 having a circuit is attached, and an ESD protection circuit and L
A U generation prevention circuit is configured.

【００１３】抵抗１，インダクタンス，容量３，ダイオ
ード４，半導体チップ１０の取り付けは、半導体装置の
製造工程のインナーリード製作段階、あるいは、半導体
チップ６とインナーリード５を接続するワイヤーボンデ
ィング工程において取り付けを行う。その後、抵抗１，
インダクタンス２，容量３，ダイオード４の取り付け部
品全体を樹脂８で封止する。The resistors 1, the inductances, the capacitors 3, the diodes 4, and the semiconductor chip 10 are attached in the step of manufacturing the inner leads of the semiconductor device manufacturing process, or in the wire bonding process for connecting the semiconductor chip 6 and the inner leads 5. To do. After that, the resistance 1,
The entire mounting parts including the inductance 2, the capacitance 3, and the diode 4 are sealed with resin 8.

【００１４】[0014]

【発明の効果】本発明の半導体装置によれば、インナー
リード製作段階、あるいは、半導体チップとインナーリ
ードを接続するワイヤーボンディング工程において、抵
抗，インダクタンス，容量，ダイオードの取り付けＥＳ
Ｄ保護回路，ＬＵ発生防止回路をインナーリード上につ
くることによって、ＥＳＤ，ＬＵ耐量向上を実現でき
る。さらに、インナーリード部および、インナーリード
上にＥＳＤ保護回路，ＬＵ発生防止回路を構成すること
は、半導体チップ内部にＥＳＤ保護回路，ＬＵ発生防止
回路を形成する必要がないため、半導体チップの小型，
高集積化を実現できる。According to the semiconductor device of the present invention, the resistance ES, the inductance ES, the capacitance ES, and the diode ES are attached in the inner lead manufacturing stage or in the wire bonding process for connecting the semiconductor chip and the inner lead.
By forming the D protection circuit and the LU generation prevention circuit on the inner lead, the ESD and LU withstanding capability can be improved. Further, since the ESD protection circuit and the LU generation prevention circuit are formed on the inner lead portion and the inner lead, it is not necessary to form the ESD protection circuit and the LU generation prevention circuit inside the semiconductor chip.
High integration can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例を示す図である。FIG. 1 is a diagram showing an embodiment of the present invention.

【図２】本発明の一実施例の断面図である。FIG. 2 is a sectional view of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

１…抵抗、２…インダクタンス、３…容量、４…ダイオ
ード、５…インナーリード、６…半導体チップ、７…ワ
イヤー、８…封止樹脂、９…絶縁シート、１０…ＥＳＤ
保護回路，ＬＵ発生防止回路を有する半導体チップ。1 ... Resistance, 2 ... Inductance, 3 ... Capacitance, 4 ... Diode, 5 ... Inner lead, 6 ... Semiconductor chip, 7 ... Wire, 8 ... Sealing resin, 9 ... Insulating sheet, 10 ... ESD
A semiconductor chip having a protection circuit and an LU generation prevention circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】半導体チップの電気信号を入出力するイン
ナーリードに絶縁シートをはりつけ、この上部に抵抗，
インダクタンス，容量，ダイオード等の部品を取り付け
たことを特徴とする半導体装置。1. An insulating sheet is attached to an inner lead for inputting and outputting an electric signal of a semiconductor chip, and a resistor,
A semiconductor device characterized in that parts such as inductance, capacitance and diode are attached. 【請求項２】半導体チップの電気信号を入出力するイン
ナーリードに絶縁シートをはりつけ、この上部に半導体
チップを取り付けたことを特徴とする半導体装置。2. A semiconductor device characterized in that an insulating sheet is attached to an inner lead for inputting and outputting an electric signal of the semiconductor chip, and the semiconductor chip is attached to the upper part of the insulating sheet.
JP1985393A 1993-02-08 1993-02-08 Semiconductor device Pending JPH06232332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985393A JPH06232332A (en) 1993-02-08 1993-02-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985393A JPH06232332A (en) 1993-02-08 1993-02-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06232332A true JPH06232332A (en) 1994-08-19

Family

ID=12010799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985393A Pending JPH06232332A (en) 1993-02-08 1993-02-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06232332A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998010457A1 (en) * 1996-09-04 1998-03-12 Micron Technology,Inc. Matrix addressable display with electrostatic discharge protection
EP0773586A3 (en) * 1995-11-13 1999-05-12 SILICONIX Incorporated Separate circuit devices in an intrapackage configuration and assembly techniques
US6476472B1 (en) * 2000-08-18 2002-11-05 Agere Systems Inc. Integrated circuit package with improved ESD protection for no-connect pins
EP1415378A1 (en) * 2001-07-13 2004-05-06 Cree Microwave, Inc. Voltage limiting protection for high frequency power device
DE10243981B4 (en) * 2002-09-20 2015-06-03 Robert Bosch Gmbh Electronic assembly, in particular regulator for generators in motor vehicles
EP2894952A4 (en) * 2012-09-07 2017-01-25 Mitsubishi Electric Corporation Power semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0773586A3 (en) * 1995-11-13 1999-05-12 SILICONIX Incorporated Separate circuit devices in an intrapackage configuration and assembly techniques
US6066890A (en) * 1995-11-13 2000-05-23 Siliconix Incorporated Separate circuit devices in an intra-package configuration and assembly techniques
WO1998010457A1 (en) * 1996-09-04 1998-03-12 Micron Technology,Inc. Matrix addressable display with electrostatic discharge protection
US5844370A (en) * 1996-09-04 1998-12-01 Micron Technology, Inc. Matrix addressable display with electrostatic discharge protection
US6266034B1 (en) 1996-09-04 2001-07-24 Micron Technology, Inc. Matrix addressable display with electrostatic discharge protection
US6356250B1 (en) 1996-09-04 2002-03-12 Micron Technology, Inc. Matrix addressable display with electrostatic discharge protection
US6476472B1 (en) * 2000-08-18 2002-11-05 Agere Systems Inc. Integrated circuit package with improved ESD protection for no-connect pins
EP1415378A1 (en) * 2001-07-13 2004-05-06 Cree Microwave, Inc. Voltage limiting protection for high frequency power device
EP1415378A4 (en) * 2001-07-13 2008-10-08 Cree Microwave Llc Voltage limiting protection for high frequency power device
DE10243981B4 (en) * 2002-09-20 2015-06-03 Robert Bosch Gmbh Electronic assembly, in particular regulator for generators in motor vehicles
EP2894952A4 (en) * 2012-09-07 2017-01-25 Mitsubishi Electric Corporation Power semiconductor device

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