JPH06232304A - Lead frame for full mold package - Google Patents

Lead frame for full mold package

Info

Publication number
JPH06232304A
JPH06232304A JP3415193A JP3415193A JPH06232304A JP H06232304 A JPH06232304 A JP H06232304A JP 3415193 A JP3415193 A JP 3415193A JP 3415193 A JP3415193 A JP 3415193A JP H06232304 A JPH06232304 A JP H06232304A
Authority
JP
Japan
Prior art keywords
lead frame
mold package
view
semiconductor element
full
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3415193A
Other languages
Japanese (ja)
Other versions
JP3159555B2 (en
Inventor
Koji Kawakubo
孝司 川久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP3415193A priority Critical patent/JP3159555B2/en
Publication of JPH06232304A publication Critical patent/JPH06232304A/en
Application granted granted Critical
Publication of JP3159555B2 publication Critical patent/JP3159555B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To avoid the swelling of sealing resin making the defective appearance. CONSTITUTION:Within this lead frame for full mold package wherein multiple recessed grooves are formed in the rear side of a semiconductor chip mounting piece 300 whereon semiconductor chips are to be mounted, protrusions 420 are to be formed toward the inside of the rectangular grooves 400 at the ends of protrusions 410 between the rectangular grooves 400.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、例えば電力用半導体装
置に用いられるフルモールドパッケージ用リードフレー
ムに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame for a full mold package used, for example, in a power semiconductor device.

【０００２】[0002]

【従来の技術】従来の電力用半導体装置に用いられてい
るフルモールドパッケージ用リードフレームを図３〜図
５を参照しつつ説明する。図３は従来のフルモールドパ
ッケージ用リードフレームの図面であって、同図（Ａ）
は平面図、同図（Ｂ）は側面図、同図（Ｃ）は裏面図、
同図（Ｄ）は（Ｂ）のＢ−Ｂ線断面図である。また、図
４はこのフルモールドパッケージ用リードフレームに半
導体素子を搭載した状態を示す図面であって、同図
（Ａ）は平面図、同図（Ｂ）は側面図、図５はこのフル
モールドパッケージ用リードフレームを樹脂封止した状
態を示す図面であって、同図（Ａ）は平面図、同図
（Ｂ）は側面図である。2. Description of the Related Art A lead frame for a full mold package used in a conventional power semiconductor device will be described with reference to FIGS. FIG. 3 is a drawing of a conventional lead frame for a full-mold package.
Is a plan view, (B) is a side view, (C) is a rear view,
FIG. 6D is a sectional view taken along line BB of FIG. 4 is a drawing showing a state in which a semiconductor element is mounted on the lead frame for a full mold package, FIG. 4 (A) is a plan view, FIG. 4 (B) is a side view, and FIG. It is a figure which shows the state which sealed the package lead frame with resin, (A) of this figure is a top view and (B) of this figure is a side view.

【０００３】従来の電力用半導体装置に用いられている
フルモールドパッケージ用リードフレームは、図３に示
すように、横枠１００と、この横枠１００から延設され
た複数本（図面では４本）のリード端子２００と、この
リード端子２００の１つの先端に形成された半導体素子
搭載片３００とを有しており、これらが横枠１００の長
手方向に複数個連なって形成されている。As shown in FIG. 3, a lead frame for a full-mold package used in a conventional power semiconductor device has a horizontal frame 100 and a plurality of lead frames (four in the drawing) extending from the horizontal frame 100. 2) and a semiconductor element mounting piece 300 formed at one end of the lead terminal 200, and a plurality of these are formed in the longitudinal direction of the horizontal frame 100.

【０００４】そして、前記半導体素子搭載片３００の裏
面側は先端部分を除いて他の部分は厚く形成されてお
り、当該厚くなった部分には、複数本の凹溝４００が形
成されている。この凹溝４００は、半導体素子７００か
ら発生する熱を放熱し易くするために形成されている。
なお、この凹溝４００と凹溝４００との間にある凸部４
１０は、図３（Ｄ）に示すように、凹溝４００の底部に
対して直角に形成されている。On the back surface side of the semiconductor element mounting piece 300, other than the tip portion, other portions are formed thick, and a plurality of concave grooves 400 are formed in the thickened portion. The groove 400 is formed so as to easily dissipate the heat generated from the semiconductor element 700.
In addition, the convex portion 4 between the concave groove 400 and the concave groove 400.
As shown in FIG. 3D, 10 is formed at a right angle to the bottom of the groove 400.

【０００５】このようなフルモールドパッケージ用リー
ドフレームには、以下のような工程が施されて電力用半
導体装置が完成する。まず、半導体素子搭載片３００の
表面側に半導体素子７００を搭載し、当該半導体素７０
０の図示しない電極と３本のリード端子２００とをボン
ディングワイヤ２１０で接続する（図４参照）。次に、
トランスファーモールド法によって半導体素子７００を
半導体素子搭載片３００とともに封止樹脂６００で封止
する（図５参照）。その後、タイバー５００を切断して
電力用半導体装置が完成する。The lead frame for such a full mold package is subjected to the following steps to complete a power semiconductor device. First, the semiconductor element 700 is mounted on the front surface side of the semiconductor element mounting piece 300, and the semiconductor element 70
The electrode 0 (not shown) and the three lead terminals 200 are connected by the bonding wires 210 (see FIG. 4). next,
The semiconductor element 700 is sealed together with the semiconductor element mounting piece 300 with the sealing resin 600 by the transfer molding method (see FIG. 5). Then, the tie bar 500 is cut to complete the power semiconductor device.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、上述し
た従来のフルモールドパッケージ用リードフレームには
以下のような問題点がある。すなわち、半導体素子７０
０を半導体素子搭載片３００とともに樹脂封止すると、
半導体素子搭載片３００の凹溝４００に相当する部分に
図５（Ｂ）に示すような膨らみ６１０が生ずる。これ
は、半導体素子搭載片３００の裏面側に凹溝４００と凸
部４１０とを形成し、半導体素子搭載片３００の裏面と
封止樹脂６００との密着面積を広げているにもかかわら
ず、まだそれらの密着性が悪く、封止樹脂６００を成形
後、半導体素子搭載片３００の裏面と封止樹脂６００と
の間に隙間が生じることによる。このような膨らみ６１
０がある電力用半導体装置は、外観不良品となる。However, the above-described conventional lead frame for a full mold package has the following problems. That is, the semiconductor device 70
When 0 is resin-sealed together with the semiconductor element mounting piece 300,
A bulge 610 as shown in FIG. 5B is generated in a portion of the semiconductor element mounting piece 300 corresponding to the concave groove 400. This is because although the concave groove 400 and the convex portion 410 are formed on the back surface side of the semiconductor element mounting piece 300, and the contact area between the back surface of the semiconductor element mounting piece 300 and the sealing resin 600 is widened, The adhesiveness is poor, and a gap is formed between the back surface of the semiconductor element mounting piece 300 and the sealing resin 600 after the sealing resin 600 is molded. Such a bulge 61
A power semiconductor device having 0 is a defective appearance product.

【０００７】本発明は上記事情に鑑みて創案されたもの
で、外観不良の原因となる封止樹脂の膨らみが生じない
フルモールドパッケージ用リードフレームを提供するこ
とを目的としている。The present invention was devised in view of the above circumstances, and an object of the present invention is to provide a lead frame for a full-mold package in which the swelling of the sealing resin, which causes a defective appearance, does not occur.

【０００８】[0008]

【課題を解決するための手段】本発明に係るフルモール
ドパッケージ用リードフレームは、半導体素子が搭載さ
れる半導体素子搭載片の裏面側に複数本の凹溝が形成さ
れたフルモールドパッケージ用リードフレームであっ
て、前記凹溝の間にある凸部の先端には凹溝の内側に向
かった突起部が形成されている。A lead frame for a full mold package according to the present invention is a lead frame for a full mold package in which a plurality of recessed grooves are formed on the back surface side of a semiconductor element mounting piece on which a semiconductor element is mounted. In addition, at the tip of the convex portion between the concave grooves, a protruding portion that faces the inside of the concave groove is formed.

【０００９】[0009]

【実施例】図１は本発明の一実施例に係るフルモールド
パッケージ用リードフレームを示す図面であって、同図
（Ａ）は平面図、同図（Ｂ）は側面図、同図（Ｃ）は裏
面図、同図（Ｄ）は（Ｂ）のＡ−Ａ線断面図である。ま
た、図２はこのフルモールドパッケージ用リードフレー
ムを樹脂封止した状態を示す図面であって、同図（Ａ）
は平面図、同図（Ｂ）は側面図である。なお、従来のも
のと略同一の部品等には同一の符号を付して説明を行
う。1 is a drawing showing a lead frame for a full mold package according to an embodiment of the present invention, in which FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. ) Is a rear view, and FIG. 6D is a sectional view taken along line AA of FIG. Further, FIG. 2 is a drawing showing a state in which the lead frame for the full mold package is resin-sealed, and FIG.
Is a plan view and FIG. 3B is a side view. It should be noted that parts and the like that are substantially the same as the conventional ones will be given the same reference numerals for the description.

【００１０】本実施例に係るフルモールドパッケージ用
リードフレームは、横枠１００と、この横枠１００から
延設された複数本（図面では４本）のリード端子２００
と、このリード端子２００の１つの先端に形成された半
導体素子搭載片３００とを有している。そして、前記半
導体素子搭載片３００の裏面側は先端部分を除いて他の
部分は厚く形成されており、当該厚くなった部分には、
複数本の凹溝４００が形成されている。The lead frame for a full-mold package according to this embodiment includes a horizontal frame 100 and a plurality of (four in the drawing) lead terminals 200 extending from the horizontal frame 100.
And a semiconductor element mounting piece 300 formed at one end of the lead terminal 200. Then, the back surface side of the semiconductor element mounting piece 300 is formed thick except for the tip portion, and the thickened portion is
A plurality of recessed grooves 400 are formed.

【００１１】凹溝４００が形成された部分には、たたき
が加えられており、凹溝４００の間にある凸部４１０の
先端には凹溝４００の内側に向かった突起部４２０が形
成されている。この突起部４２０は、略三角形のオーバ
ーハング状に形成されている。A tapping is applied to the portion where the concave groove 400 is formed, and a protrusion portion 420 facing the inside of the concave groove 400 is formed at the tip of the convex portion 410 between the concave grooves 400. There is. The protrusion 420 is formed in a substantially triangular overhang shape.

【００１２】かかる突起部４２０が凸部４１０に設けら
れたフルモールドパッケージ用リードフレームを封止樹
脂６００で樹脂封止すると、凹溝４００に流れ込んだ封
止樹脂６００が突起部４２０と絡み合って、それらの密
着性をいっそう高める。When the lead frame for a full mold package in which the protrusion 420 is provided on the protrusion 410 is resin-sealed with the sealing resin 600, the sealing resin 600 flowing into the concave groove 400 is entangled with the protrusion 420, Further improve their adhesion.

【００１３】なお、上述した実施例では、凸部４１０の
先端に形成される突起部４２０は略三角形のオーバーハ
ング状に形成されているとしたが、流入した封止樹脂６
００が絡み合う形状であれば、どのような形状でもよい
ことは勿論である。In the above-mentioned embodiment, the projection 420 formed at the tip of the projection 410 is formed in the shape of a substantially triangular overhang, but the sealing resin 6 that has flowed in is described.
Of course, any shape may be used as long as 00 is intertwined.

【００１４】[0014]

【発明の効果】本発明に係るフルモールドパッケージ用
リードフレームは、半導体素子が搭載される半導体素子
搭載片の裏面側に複数本の凹溝が形成されたフルモール
ドパッケージ用リードフレームにおいて、前記凹溝の間
にある凸部の先端には凹溝の内側に向かった突起部が形
成されている。このため、凹溝に流れ込んだ封止樹脂が
突起部と絡み合うので凹溝には封止樹脂が隙間なく流入
する。従って、従来にみられたような封止樹脂の膨らみ
が発生せず、外観不良品を低減することができる。The lead frame for a full mold package according to the present invention is a lead frame for a full mold package in which a plurality of concave grooves are formed on the back surface side of a semiconductor element mounting piece on which a semiconductor element is mounted. A protrusion that faces the inside of the concave groove is formed at the tip of the convex portion between the grooves. For this reason, the sealing resin that has flowed into the groove is entangled with the protrusions, so that the sealing resin flows into the groove without any gap. Therefore, the swelling of the sealing resin unlike in the past does not occur, and the number of defective appearance products can be reduced.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例に係るフルモールドパッケー
ジ用リードフレームを示す図面であって、同図（Ａ）は
平面図、同図（Ｂ）は側面図、同図（Ｃ）は裏面図、同
図（Ｄ）は（Ｂ）のＡ−Ａ線断面図である。1A and 1B are views showing a lead frame for a full-mold package according to an embodiment of the present invention, wherein FIG. 1A is a plan view, FIG. 1B is a side view, and FIG. The figure and the figure (D) are the sectional views on the AA line of (B).

【図２】このフルモールドパッケージ用リードフレーム
を樹脂封止した状態を示す図面であって、同図（Ａ）は
平面図、同図（Ｂ）は側面図である。2A and 2B are drawings showing a state in which the lead frame for a full mold package is resin-sealed, FIG. 2A being a plan view and FIG. 2B being a side view.

【図３】従来のフルモールドパッケージ用リードフレー
ムの図面であって、同図（Ａ）は平面図、同図（Ｂ）は
側面図、同図（Ｃ）は裏面図、同図（Ｄ）は（Ｂ）のＢ
−Ｂ線断面図である。3A and 3B are drawings of a conventional lead frame for a full-mold package, where FIG. 3A is a plan view, FIG. 3B is a side view, FIG. 3C is a rear view, and FIG. Is B of (B)
It is a -B line sectional view.

【図４】このフルモールドパッケージ用リードフレーム
に半導体素子を搭載した状態を示す図面であって、同図
（Ａ）は平面図、同図（Ｂ）は側面図である。4A and 4B are diagrams showing a state in which a semiconductor element is mounted on the lead frame for a full mold package, FIG. 4A being a plan view and FIG. 4B being a side view.

【図５】このフルモールドパッケージ用リードフレーム
を樹脂封止した状態を示す図面であって、同図（Ａ）は
平面図、同図（Ｂ）は側面図である。5A and 5B are drawings showing a state in which the lead frame for a full mold package is resin-sealed, FIG. 5A being a plan view and FIG. 5B being a side view.

【符号の説明】[Explanation of symbols]

３００ 半導体素子搭載片 ４００ 凹溝 ４１０ 凸部 ４２０ 突起部 300 semiconductor element mounting piece 400 concave groove 410 convex portion 420 protruding portion

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 半導体素子が搭載される半導体素子搭載
片の裏面側に複数本の凹溝が形成されたフルモールドパ
ッケージ用リードフレームにおいて、前記凹溝の間にあ
る凸部の先端には凹溝の内側に向かった突起部が形成さ
れていることを特徴とするフルモールドパッケージ用リ
ードフレーム。1. A lead frame for a full mold package, wherein a plurality of recessed grooves are formed on the back surface side of a semiconductor element mounting piece on which a semiconductor element is mounted. A lead frame for a full-mold package, characterized in that a protrusion is formed toward the inside of the groove.
JP3415193A 1993-01-28 1993-01-28 Method for manufacturing power semiconductor device Expired - Fee Related JP3159555B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3415193A JP3159555B2 (en) 1993-01-28 1993-01-28 Method for manufacturing power semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3415193A JP3159555B2 (en) 1993-01-28 1993-01-28 Method for manufacturing power semiconductor device

Publications (2)

Publication Number Publication Date
JPH06232304A true JPH06232304A (en) 1994-08-19
JP3159555B2 JP3159555B2 (en) 2001-04-23

Family

ID=12406205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3415193A Expired - Fee Related JP3159555B2 (en) 1993-01-28 1993-01-28 Method for manufacturing power semiconductor device

Country Status (1)

Country Link
JP (1) JP3159555B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5911105A (en) * 1996-07-12 1999-06-08 Nec Corporation Flash memory manufacturing method
US6373124B1 (en) 1998-08-24 2002-04-16 Matsushita Electric Industrial Co., Ltd. Lead frame and method of producing the same, and a semiconductor device using the same
JP2008028053A (en) * 2006-07-20 2008-02-07 Hitachi Ltd Resin-mold power semiconductor apparatus

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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