JPH06216313A - Semiconductor device sealed with resin - Google Patents
Semiconductor device sealed with resinInfo
- Publication number
- JPH06216313A JPH06216313A JP673193A JP673193A JPH06216313A JP H06216313 A JPH06216313 A JP H06216313A JP 673193 A JP673193 A JP 673193A JP 673193 A JP673193 A JP 673193A JP H06216313 A JPH06216313 A JP H06216313A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- resin layer
- insulating
- lead
- electrodeposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、プラスチックパッケー
ジ等樹脂で封止された樹脂封止半導体装置に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device sealed with resin such as a plastic package.
【０００２】[0002]
【従来の技術】従来、この種の樹脂封止半導体装置は、
搭載される半導体ペレットの大型化に伴い、パッケージ
側端とデバイス取付部であるダイパッドとの間の寸法が
一段と狭くなる傾向にある。これは、デバイスサイズが
大きくなっているのに、これを収納するパッケージのサ
イズが規格化されているため、大きくすることができな
いことに起因する。その結果、デバイスより電気的に接
続する内部リードの引き廻しの制限、外部リードの引抜
き強度の低下、および半田耐熱性の低下が生じる。2. Description of the Related Art Conventionally, this type of resin-sealed semiconductor device has been
As the size of semiconductor pellets mounted increases, the size between the package side edge and the die pad that is the device mounting portion tends to become narrower. This is because the device size is large, but the size of the package that houses the device is standardized, and therefore cannot be increased. As a result, the routing of the internal leads electrically connected to the device is limited, the pull-out strength of the external leads is reduced, and the solder heat resistance is reduced.
【０００３】そこで、例えば、特開昭６１−２１８１３
９号公報に開示されているように、デバイスの非回路形
成面に、ボンディングパッドに被らない大きさの絶縁シ
ートを接着し、この絶縁シート上面には、内部リードを
延在することにより、内部リードと樹脂との接着力を大
幅に向上させ、大型デバイスを搭載する場合でも、樹脂
からのリード抜けを防止できる構造が示されている。Therefore, for example, Japanese Patent Laid-Open No. 61-21813
As disclosed in Japanese Patent Laid-Open Publication No. 9-90, an insulating sheet having a size that does not cover the bonding pad is adhered to the non-circuit forming surface of the device, and internal leads are extended on the upper surface of the insulating sheet. A structure is shown in which the adhesive force between the internal lead and the resin is significantly improved and the lead can be prevented from coming off from the resin even when a large device is mounted.
【０００４】図８は従来の樹脂封止半導体装置を示す断
面図であり、特にＬＯＣ（リード・オン・チップ）を示
す。図において、１はデバイス、２は両面に接着剤が塗
布された絶縁性両面接着テープであり、この絶縁性両面
接着テープ２の下面にはデバイスの上面が接着固定され
ている。３はこの絶縁性両面接着テープ２の上面に接着
固定した内部リード、４はこの内部リード３上に設けた
ボンディングワイヤ用の金属被膜、５はデバイス１のボ
ンディングパッド、６はこのボンディングパッドと内部
リード３とを電気的に接続するＡｕ線などのボンディン
グワイヤ、７は樹脂である。FIG. 8 is a cross-sectional view showing a conventional resin-encapsulated semiconductor device, particularly showing a LOC (lead-on-chip). In the figure, 1 is a device, 2 is an insulating double-sided adhesive tape having adhesive applied on both sides, and the upper surface of the device is adhesively fixed to the lower surface of this insulating double-sided adhesive tape 2. Reference numeral 3 is an internal lead which is adhesively fixed to the upper surface of the insulating double-sided adhesive tape 2, 4 is a metal film for a bonding wire provided on the internal lead 3, 5 is a bonding pad of the device 1, and 6 is this bonding pad and the inside. A bonding wire such as an Au wire for electrically connecting the lead 3 and 7 are resins.
【０００５】この構成による樹脂封止半導体装置は、ダ
イパッドがなく、デバイス１の表面と内部リード３の下
面とを絶縁性両面接着テープ２を挟んで張り合わせて固
定する。そして、デバイス１のボンディングパッド５と
内部リード３の金属被膜４とをボンディングワイヤ６に
より電気的に接続する。そして、全体を樹脂７で封止し
たものである。The resin-sealed semiconductor device having this structure has no die pad, and the front surface of the device 1 and the lower surface of the inner lead 3 are bonded and fixed with the insulating double-sided adhesive tape 2 sandwiched therebetween. Then, the bonding pad 5 of the device 1 and the metal coating 4 of the internal lead 3 are electrically connected by the bonding wire 6. And the whole is sealed with resin 7.
【０００６】図９は従来の他の樹脂封止半導体装置を示
す断面図であり、特にＣＯＬ（チップ・オン・リード）
を示す。図において、８は両面に接着剤が塗布された絶
縁性両面接着テープであり、この絶縁性両面接着テープ
８の上面にデバイス１の下面が接着固定される。９はこ
の絶縁性両面接着テープ８の下面に接着固定された内部
リード、１０はこの内部リード９上に設けたボンディン
グ用の金属被膜、１１はデバイス１のボンディングパッ
ド５と内部リード９とを電気的に接続するＡｕ線などの
ボンディングワイヤである。FIG. 9 is a sectional view showing another conventional resin-encapsulated semiconductor device, particularly COL (chip-on-lead).
Indicates. In the figure, reference numeral 8 is an insulating double-sided adhesive tape whose both surfaces are coated with an adhesive, and the lower surface of the device 1 is adhesively fixed to the upper surface of this insulating double-sided adhesive tape 8. Reference numeral 9 is an internal lead that is adhesively fixed to the lower surface of the insulating double-sided adhesive tape 8, 10 is a metal coating for bonding provided on the internal lead 9, and 11 is an electrical connection between the bonding pad 5 of the device 1 and the internal lead 9. It is a bonding wire such as an Au wire that is electrically connected.
【０００７】この構成による樹脂封止半導体装置は、ダ
イパッドがなく、デバイス１の裏面と内部リード９の上
面とを絶縁性両面接着テープ８を挟んで張り合わせて固
定する。そして、デバイス１のボンディングパッド５と
内部リード９とをボンディングワイヤ１１により電気的
に接続する。そして、全体を樹脂７で封止したものであ
る。The resin-sealed semiconductor device having this structure does not have a die pad, and the back surface of the device 1 and the top surface of the internal lead 9 are fixed by sticking the insulating double-sided adhesive tape 8 therebetween. Then, the bonding pad 5 of the device 1 and the internal lead 9 are electrically connected by the bonding wire 11. And the whole is sealed with resin 7.
【０００８】[0008]
【発明が解決しようとする課題】しかしながら、上記構
成のＬＯＣ、ＣＯＬといった樹脂封止半導体装置では、
デバイスを単体でしか接着し、電気的に接続することが
できず、装置単体で、デバイス単体の機能および容量し
か得られないという問題点があった。However, in the resin-sealed semiconductor device such as LOC and COL having the above structure,
There is a problem that the device can be adhered and electrically connected only by itself, and only the function and capacity of the device can be obtained by the device alone.
【０００９】この発明は、装置単体で、デバイス単体の
機能および容量しか得られないという問題点を除去する
ため、リードフレームの内部リードの表面および裏面に
絶縁性電着樹脂層を電着し、この絶縁性電着樹脂層を用
いて上部デバイスと下部デバイスを接着した優れた装置
を提供することを目的とする。According to the present invention, in order to eliminate the problem that only the function and capacity of the device itself can be obtained by the device alone, an insulating electrodeposition resin layer is electrodeposited on the front and back surfaces of the inner leads of the lead frame, An object of the present invention is to provide an excellent device in which an upper device and a lower device are bonded by using this insulating electrodeposition resin layer.
【００１０】[0010]
【課題を解決するための手段】本発明に係る樹脂封止半
導体装置は、内部リードの表面および裏面に電着した絶
縁性電着樹脂層を挟んで、上部デバイスと下部デバイス
を接着し、この上部デバイスおよび下部デバイスのボン
ディングパッドと内部リードをワイヤボンディングする
ものである。In a resin-sealed semiconductor device according to the present invention, an upper electrode and a lower device are adhered to each other with an insulative electrodeposition resin layer electrodeposited on the front surface and the back surface of an internal lead being sandwiched between them. Wire bonding the bonding pads of the upper device and the lower device to the internal leads.
【００１１】[0011]
【作用】本発明は、装置当りの機能および容量が増加
し、集積度を向上することができる。According to the present invention, the function and capacity per device can be increased and the degree of integration can be improved.
【００１２】[0012]
【実施例】図１は本発明に係る樹脂封止半導体装置の第
１実施例を示す概略断面図であり、図２は図１の樹脂を
破断した斜視図である。図において、１２は上部デバイ
ス、１３はこの上部デバイス１２と同じデバイスサイズ
の下部デバイス、１４はリードフレームの第１内部リー
ドであり、この第１内部リード１４は、その詳細を図３
に示すように上部デバイス１２と下部デバイス１３との
接着部分に設けられている。そして、この第１内部リー
ド１４の表面には、第１絶縁性電着樹脂層１５があらか
じめ電着されており、第１内部リード１４の裏面には第
２絶縁性電着樹脂層１６があらかじめ電着されている。
ここで、電着樹脂はリードフレームの最終工程に電着さ
れ、アクリル系（アニオン型電着樹脂）、エポキシ系
（カチオン型電着樹脂）を使用している。この組成は主
骨格樹脂、水溶性官能基、架橋成分、中和剤、添加剤、
助剤、硬化触媒、希釈剤などである。この電着樹脂をリ
ードフレームの周りを被う様にする。この厚さは１５〜
３０μｍであり、ダイスボンドの時に熱圧着によって接
着される（熱８０〜１５０℃、荷重０．２〜１．０ｋ
ｇ）。１７は第２内部リードであり、この第２内部リー
ド１７の裏面には図３に示すように第２絶縁性電着樹脂
層１６があらかじめ電着されている。１８は図３に示す
ように、第１内部リード１４および第２内部リード１７
上に設けたボンディングワイヤ用の金属被膜、１９はボ
ンディングパッド、２０は金属被膜１８とボンディング
パッド１９とを電気的に接続するボンディングワイヤで
ある。1 is a schematic sectional view showing a first embodiment of a resin-encapsulated semiconductor device according to the present invention, and FIG. 2 is a perspective view in which the resin of FIG. 1 is cut away. In the figure, 12 is an upper device, 13 is a lower device having the same device size as the upper device 12, 14 is a first internal lead of a lead frame, and the first internal lead 14 is shown in detail in FIG.
As shown in FIG. 3, it is provided at the bonding portion between the upper device 12 and the lower device 13. The first insulative electrodeposition resin layer 15 is previously electrodeposited on the surface of the first inner lead 14, and the second insulative electrodeposition resin layer 16 is previously deposited on the back surface of the first inner lead 14. It is electrodeposited.
Here, the electrodeposition resin is electrodeposited in the final step of the lead frame, and acrylic type (anion type electrodeposition resin) or epoxy type (cation type electrodeposition resin) is used. This composition has a main skeleton resin, a water-soluble functional group, a crosslinking component, a neutralizing agent, an additive,
Examples include auxiliary agents, curing catalysts, diluents, and the like. The electrodeposition resin is placed so as to cover the lead frame. This thickness is 15 ~
It is 30 μm and is bonded by thermocompression bonding at the time of die bonding (heat 80 to 150 ° C., load 0.2 to 1.0 k).
g). Reference numeral 17 denotes a second inner lead, and a second insulating electrodeposition resin layer 16 is electrodeposited on the back surface of the second inner lead 17 in advance as shown in FIG. As shown in FIG. 3, reference numeral 18 denotes a first internal lead 14 and a second internal lead 17.
A metal film for the bonding wire provided above, 19 is a bonding pad, and 20 is a bonding wire for electrically connecting the metal film 18 and the bonding pad 19.
【００１３】なお、ボンディングワイヤ用の金属被膜１
８上には第１絶縁性電着樹脂層１５を電着しないように
する。これはリード裏面の電着樹脂が金属被膜１８を被
った場合ワイヤボンディングを行う時に金属接合できな
いからである。また、第１絶縁性電着樹脂層１５および
第２絶縁性電着樹脂層１６は、例えば１５〜３０μｍの
厚さであり、それ以下になるとデバイス表面と内部リー
ドとの絶縁性が、信頼性試験によって低下することが懸
念される。The metal coating 1 for the bonding wire
The first insulating electrodeposition resin layer 15 is not electrodeposited on the surface 8. This is because if the electrodeposition resin on the back surface of the lead covers the metal coating 18, metal bonding cannot be performed when wire bonding is performed. Further, the first insulating electrodeposition resin layer 15 and the second insulating electrodeposition resin layer 16 have a thickness of, for example, 15 to 30 μm, and if the thickness is less than that, the insulation between the device surface and the internal leads is not reliable. There is a concern that it will be reduced by the test.
【００１４】また、上部デバイス１２と下部デバイス１
３のデバイスサイズを同じにした場合を示し、しかも上
部デバイス１２と下部デバイス１３の各ボンディングパ
ッド１９を片側、例えば長辺に集めた構造とし、近くに
ボンディングしなければいけない第２内部リード１７を
ＬＯＣタイプとし、第１内部リード１４の引き廻しはＣ
ＯＬタイプとしている。Also, the upper device 12 and the lower device 1
3 shows the case where the device size is the same, and the bonding pads 19 of the upper device 12 and the lower device 13 are gathered on one side, for example, the long side, and the second internal lead 17 that must be bonded nearby is formed. LOC type, the first internal lead 14 is C
It is an OL type.
【００１５】次に、上記構成による樹脂封止半導体装置
の製造工程について説明する。まず、第１内部リード１
４および第２内部リード１７上に、ボンディング用の金
属被膜１８を形成する。そして、上部デバイス１２と下
部デバイス１３との接着部分に設けられる第１内部リー
ド１４の表面に、第１絶縁性電着樹脂層１５を電着する
と共に、この第１内部リード１４の裏面に、第２絶縁性
電着樹脂層１６を電着する。そして、第２内部リード１
７の裏面に、第２絶縁性電着樹脂層１６を電着する。そ
して、第１内部リード１４を挟んで上部デバイス１２を
第１絶縁性電着樹脂層１５により熱圧着し、下部デバイ
ス１３を第２絶縁性電着樹脂層１６により熱圧着し、第
２内部リード１７を第２絶縁性電着樹脂層１６により下
部デバイスに熱圧着し、例えば８０〜１５０℃で１０〜
３０分で硬化させる。その後、上部デバイス１２および
下部デバイス１３の各ボンディングパッド１９と、第１
内部リード１４および第２内部リード１７の各金属被膜
１８とをボンディングワイヤ２０でボンディングして、
上部デバイス１２と下部デバイス１３とを電気的に導通
する。そして、全体を樹脂７で封止する。Next, a manufacturing process of the resin-sealed semiconductor device having the above structure will be described. First, the first internal lead 1
A metal film 18 for bonding is formed on the fourth and second inner leads 17. Then, the first insulative electrodeposition resin layer 15 is electrodeposited on the surface of the first inner lead 14 provided at the bonding portion between the upper device 12 and the lower device 13, and the back surface of the first inner lead 14 is The second insulating electrodeposition resin layer 16 is electrodeposited. And the second internal lead 1
The second insulating electrodeposition resin layer 16 is electrodeposited on the back surface of 7. Then, the upper device 12 is thermocompression-bonded by the first insulating electrodeposition resin layer 15 with the first internal lead 14 sandwiched therebetween, and the lower device 13 is thermocompression-bonded by the second insulating electrodeposition resin layer 16 by the second internal lead. 17 is thermocompression-bonded to the lower device by the second insulative electrodeposition resin layer 16, for example, at 80 to 150 ° C.
Cure in 30 minutes. Then, each bonding pad 19 of the upper device 12 and the lower device 13
The inner leads 14 and the respective metal coatings 18 of the second inner leads 17 are bonded with the bonding wires 20,
The upper device 12 and the lower device 13 are electrically connected. Then, the whole is sealed with resin 7.
【００１６】なお、上部デバイス１２のボンディングパ
ッド１９へのワイヤボンディングの際、上部デバイス１
２の裏面の受けがないため、上部デバイス１２がクラッ
クを起こし易いので、上部デバイス１２の裏面側で、こ
のボンディングパッド１９に対向する部分には、第１内
部リード１４を引き廻し、上部デバイス１２にクラック
が生じないようにすることも必要である。When wire bonding to the bonding pad 19 of the upper device 12, the upper device 1
Since the upper device 12 does not receive the back surface of the upper device 12, the upper device 12 is apt to crack. Therefore, on the back surface side of the upper device 12, the first internal lead 14 is routed around the portion facing the bonding pad 19. It is also necessary to prevent cracks from occurring in the.
【００１７】また、図４は上部デバイス２１と下部デバ
イス２２のデバイスサイズを同じにし、各ボンディング
パッド１９を短辺に集めた構造である。Further, FIG. 4 shows a structure in which the upper device 21 and the lower device 22 have the same device size and each bonding pad 19 is gathered on the short side.
【００１８】また、図５は上部デバイス２３と下部デバ
イス２４のデバイスサイズを同じにし、各ボンディング
パッド１９を短辺および長辺の１辺ずつに集めた構造で
ある。Further, FIG. 5 shows a structure in which the upper device 23 and the lower device 24 have the same device size and each bonding pad 19 is gathered on one side of the short side and one side of the long side.
【００１９】図６は本発明に係る樹脂封止半導体装置の
第２実施例を示す概略断面図であり、図７は図６の樹脂
を破断した斜視図である。この第２実施例では、上部デ
バイス２５のデバイスサイズに対して、下部デバイスサ
イズ２６のデバイスサイズを大きくした場合を示す。FIG. 6 is a schematic sectional view showing a second embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 7 is a perspective view in which the resin of FIG. 6 is broken. In the second embodiment, a case where the device size of the lower device size 26 is made larger than the device size of the upper device 25 is shown.
【００２０】なお、この第２実施例の製造工程について
は、図１と同様であり、その詳細な説明を省略する。The manufacturing process of the second embodiment is the same as that shown in FIG. 1, and its detailed description is omitted.
【００２１】[0021]
【発明の効果】以上詳細に説明したように、本発明に係
る樹脂封止半導体装置によれば、絶縁性電着樹脂を電着
した内部リードを挟んで、上部デバイスと下部デバイス
を接着し、この内部リードと各デバイスとの間をボンデ
ィングワイヤにより電気的に接続する構成としたので、
１つのパッケージに対する集積度が向上する効果があ
る。As described above in detail, according to the resin-sealed semiconductor device of the present invention, the upper device and the lower device are bonded to each other with the inner lead electrodeposited with the insulating electrodeposition resin sandwiched therebetween, Since this internal lead and each device are electrically connected by a bonding wire,
This has the effect of increasing the degree of integration with respect to one package.
【図１】本発明に係る樹脂封止半導体装置の第１実施例
を示す断面図である。FIG. 1 is a sectional view showing a first embodiment of a resin-sealed semiconductor device according to the present invention.
【図２】図１における樹脂を破断した斜視図である。FIG. 2 is a perspective view in which the resin in FIG. 1 is broken.
【図３】図２の一部詳細な斜視図である。3 is a partially detailed perspective view of FIG. 2. FIG.
【図４】図１におけるボンディングパッドをデバイスの
短辺に設けた場合の斜視図である。FIG. 4 is a perspective view when the bonding pad in FIG. 1 is provided on the short side of the device.
【図５】図１におけるボンディングパッドをデバイスの
短辺および長辺の一辺ずつに設けた場合の斜視図であ
る。5 is a perspective view when the bonding pad in FIG. 1 is provided on each of the short side and the long side of the device.
【図６】本発明に係る樹脂封止半導体装置の第２実施例
を示す断面図である。FIG. 6 is a sectional view showing a second embodiment of the resin-sealed semiconductor device according to the present invention.
【図７】図６の樹脂を一部破断した斜視図である。FIG. 7 is a perspective view in which the resin of FIG. 6 is partially broken.
【図８】従来の樹脂封止半導体装置を示す断面図であ
る。FIG. 8 is a cross-sectional view showing a conventional resin-sealed semiconductor device.
【図９】従来の他の樹脂封止半導体装置を示す断面図で
ある。FIG. 9 is a cross-sectional view showing another conventional resin-sealed semiconductor device.
１２，２１，２３，２５ 上部デバイス １３，２２，２４，２６ 下部デバイス １４ 第１内部リード １５ 第１絶縁性電着樹脂層 １６ 第２絶縁性電着樹脂層 １７ 第２内部リード 12, 21, 23, 25 Upper device 13, 22, 24, 26 Lower device 14 First internal lead 15 First insulating electrodeposition resin layer 16 Second insulating electrodeposition resin layer 17 Second internal lead
Claims (1)
ドの表面および裏面に電着した絶縁性電着樹脂層を挟ん
で、上部デバイスと下部デバイスを接着し、この上部デ
バイスおよび下部デバイスのボンディングパッドと内部
リードをワイヤボンディングすることを特徴とする樹脂
封止半導体装置。1. In a resin-sealed semiconductor device, an upper electrode and a lower device are adhered to each other with an insulating electrodeposition resin layer electrodeposited on the front surface and the back surface of an internal lead, and a bonding pad for the upper device and the lower device. A resin-sealed semiconductor device, characterized in that the inner lead is wire-bonded to the inner lead.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP673193A JP3200488B2 (en) | 1993-01-19 | 1993-01-19 | Resin-sealed semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP673193A JP3200488B2 (en) | 1993-01-19 | 1993-01-19 | Resin-sealed semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06216313A true JPH06216313A (en) | 1994-08-05 |
| JP3200488B2 JP3200488B2 (en) | 2001-08-20 |
Family
ID=11646387
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP673193A Expired - Fee Related JP3200488B2 (en) | 1993-01-19 | 1993-01-19 | Resin-sealed semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3200488B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181165A (en) * | 1994-12-26 | 1996-07-12 | Nec Kyushu Ltd | Semiconductor integrated circuit |
| US6998190B2 (en) * | 2002-01-21 | 2006-02-14 | Nec Tokin Corporation | Battery having a sheet current collector fluid-tightly separating basic cells |
| WO2006028421A1 (en) * | 2004-09-09 | 2006-03-16 | United Test And Assembly Center Limited | Multi-die ic package and manufacturing method |
| US8159062B2 (en) | 2000-01-31 | 2012-04-17 | Elpida Memory, Inc. | Semiconductor and a method of manufacturing the same |
-
1993
- 1993-01-19 JP JP673193A patent/JP3200488B2/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08181165A (en) * | 1994-12-26 | 1996-07-12 | Nec Kyushu Ltd | Semiconductor integrated circuit |
| US8159062B2 (en) | 2000-01-31 | 2012-04-17 | Elpida Memory, Inc. | Semiconductor and a method of manufacturing the same |
| US8502395B2 (en) | 2000-01-31 | 2013-08-06 | Elpida Memory, Inc. | Semiconductor device and a method of manufacturing the same |
| US8853864B2 (en) | 2000-01-31 | 2014-10-07 | Ps4 Luxco S.A.R.L. | Semiconductor device and a method of manufacturing the same |
| US6998190B2 (en) * | 2002-01-21 | 2006-02-14 | Nec Tokin Corporation | Battery having a sheet current collector fluid-tightly separating basic cells |
| WO2006028421A1 (en) * | 2004-09-09 | 2006-03-16 | United Test And Assembly Center Limited | Multi-die ic package and manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3200488B2 (en) | 2001-08-20 |
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