JP3200488B2 - Resin-sealed semiconductor device and method of manufacturing the same - Google Patents

Resin-sealed semiconductor device and method of manufacturing the same

Info

Publication number
JP3200488B2
JP3200488B2 JP673193A JP673193A JP3200488B2 JP 3200488 B2 JP3200488 B2 JP 3200488B2 JP 673193 A JP673193 A JP 673193A JP 673193 A JP673193 A JP 673193A JP 3200488 B2 JP3200488 B2 JP 3200488B2
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
leads
manufacturing
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP673193A
Other languages
Japanese (ja)
Other versions
JPH06216313A (en
Inventor
悦夫 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP673193A priority Critical patent/JP3200488B2/en
Publication of JPH06216313A publication Critical patent/JPH06216313A/en
Application granted granted Critical
Publication of JP3200488B2 publication Critical patent/JP3200488B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826Connecting between the body and an opposite side of the item with respect to the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To raise the pull-out-proof strength of an outer lead and the resistance to solder and heat and besides improve integration degree, in a semiconductor device sealed with resin such as a plastic package, etc. CONSTITUTION:The first insulating resin layer 15 is electrodeposited on the surface of an inner lead 14, and the second resin layer 16 is electrodeposited on the rear of it, and an upper device 12 and a lower device 13 are fixed by this first insulating electrodeposited resin layer 15 and the second insulating electrodeposited resin layer 16, and the bonding pads 19 of the upper device 12 and 13 and the inner leads 14 and 17 are electrically connected with each other by bonding wires 20.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、プラスチックパッケー
ジ等樹脂で封止された樹脂封止型半導体装置及びその
製造方法に関するものである。
The present invention relates to a sealed resin-sealed semiconductor device and a resin such as a plastic package
It relates to a manufacturing method .

【0002】[0002]

【従来の技術】従来、この種の樹脂封止半導体装置は、
搭載される半導体ペレットの大型化に伴い、パッケージ
側端とデバイス取付部であるダイパッドとの間の寸法が
一段と狭くなる傾向にある。これは、デバイスサイズが
大きくなっているのに、これを収納するパッケージのサ
イズが規格化されているため、大きくすることができな
いことに起因する。その結果、デバイスより電気的に接
続する内部リードの引き廻しの制限、外部リードの引抜
き強度の低下、および半田耐熱性の低下が生じる。
2. Description of the Related Art Conventionally, this type of resin-sealed semiconductor device has been
As the size of the semiconductor pellet to be mounted increases, the dimension between the package side end and the die pad as a device mounting portion tends to be further reduced. This is because, although the device size is large, the size of the package for storing the device cannot be increased because the size of the package is standardized. As a result, there is a limitation on the routing of the internal leads that are electrically connected to the device, a decrease in the pull-out strength of the external leads, and a decrease in solder heat resistance.

【0003】そこで、例えば、特開昭61−21813
9号公報に開示されているように、デバイスの非回路形
成面に、ボンディングパッドに被らない大きさの絶縁シ
ートを接着し、この絶縁シート上面には、内部リードを
延在することにより、内部リードと樹脂との接着力を大
幅に向上させ、大型デバイスを搭載する場合でも、樹脂
からのリード抜けを防止できる構造が示されている。
For example, Japanese Patent Application Laid-Open No. 61-21813 discloses
As disclosed in Japanese Unexamined Patent Publication No. 9 (1999), an insulating sheet having a size that does not cover bonding pads is bonded to the non-circuit forming surface of the device, and internal leads are extended on the upper surface of the insulating sheet. A structure is shown in which the adhesive force between the internal lead and the resin is significantly improved, and even when a large device is mounted, the lead can be prevented from coming off from the resin.

【0004】図8は従来の樹脂封止半導体装置を示す断
面図であり、特にLOC(リード・オン・チップ)を示
す。図において、1はデバイス、2は両面に接着剤が塗
布された絶縁性両面接着テープであり、この絶縁性両面
接着テープ2の下面にはデバイスの上面が接着固定され
ている。3はこの絶縁性両面接着テープ2の上面に接着
固定した内部リード、4はこの内部リード3上に設けた
ボンディングワイヤ用の金属被膜、5はデバイス1のボ
ンディングパッド、6はこのボンディングパッドと内部
リード3とを電気的に接続するAu線などのボンディン
グワイヤ、7は樹脂である。
FIG. 8 is a cross-sectional view showing a conventional resin-encapsulated semiconductor device, particularly showing a LOC (lead-on-chip). In the figure, reference numeral 1 denotes a device, and 2 denotes an insulating double-sided adhesive tape having an adhesive applied to both surfaces. The upper surface of the device is bonded and fixed to the lower surface of the insulating double-sided adhesive tape 2. Reference numeral 3 denotes an internal lead adhered and fixed to the upper surface of the insulating double-sided adhesive tape 2, reference numeral 4 denotes a metal film for a bonding wire provided on the internal lead 3, reference numeral 5 denotes a bonding pad of the device 1, and reference numeral 6 denotes the bonding pad and the internal A bonding wire 7 such as an Au wire for electrically connecting the lead 3 and 7 are resin.

【0005】この構成による樹脂封止半導体装置は、ダ
イパッドがなく、デバイス1の表面と内部リード3の下
面とを絶縁性両面接着テープ2を挟んで張り合わせて固
定する。そして、デバイス1のボンディングパッド5と
内部リード3の金属被膜4とをボンディングワイヤ6に
より電気的に接続する。そして、全体を樹脂7で封止し
たものである。
The resin-encapsulated semiconductor device having this configuration has no die pad, and the surface of the device 1 and the lower surface of the internal lead 3 are adhered and fixed with the insulating double-sided adhesive tape 2 interposed therebetween. Then, the bonding pad 5 of the device 1 and the metal coating 4 of the internal lead 3 are electrically connected by the bonding wire 6. The entire structure is sealed with a resin 7.

【0006】図9は従来の他の樹脂封止半導体装置を示
す断面図であり、特にCOL(チップ・オン・リード)
を示す。図において、8は両面に接着剤が塗布された絶
縁性両面接着テープであり、この絶縁性両面接着テープ
8の上面にデバイス1の下面が接着固定される。9はこ
の絶縁性両面接着テープ8の下面に接着固定された内部
リード、10はこの内部リード9上に設けたボンディン
グ用の金属被膜、11はデバイス1のボンディングパッ
ド5と内部リード9とを電気的に接続するAu線などの
ボンディングワイヤである。
FIG. 9 is a cross-sectional view showing another conventional resin-encapsulated semiconductor device, particularly COL (chip-on-lead).
Is shown. In the figure, reference numeral 8 denotes an insulating double-sided adhesive tape having both sides coated with an adhesive, and the lower surface of the device 1 is bonded and fixed to the upper surface of the insulating double-sided adhesive tape 8. Reference numeral 9 denotes an internal lead adhered and fixed to the lower surface of the insulating double-sided adhesive tape 8, reference numeral 10 denotes a metal film for bonding provided on the internal lead 9, and reference numeral 11 denotes an electric connection between the bonding pad 5 and the internal lead 9 of the device 1. Bonding wires, such as Au wires, which are electrically connected.

【0007】この構成による樹脂封止半導体装置は、ダ
イパッドがなく、デバイス1の裏面と内部リード9の上
面とを絶縁性両面接着テープ8を挟んで張り合わせて固
定する。そして、デバイス1のボンディングパッド5と
内部リード9とをボンディングワイヤ11により電気的
に接続する。そして、全体を樹脂7で封止したものであ
る。
In the resin-encapsulated semiconductor device having this configuration, there is no die pad, and the back surface of the device 1 and the upper surface of the internal lead 9 are adhered and fixed with the insulating double-sided adhesive tape 8 interposed therebetween. Then, the bonding pads 5 of the device 1 and the internal leads 9 are electrically connected by the bonding wires 11. The entire structure is sealed with a resin 7.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、上記構
成のLOC、COLといった樹脂封止半導体装置では、
デバイスを単体でしか接着し、電気的に接続することが
できず、装置単体で、デバイス単体の機能および容量し
か得られないという問題点があった。
However, in the resin-encapsulated semiconductor devices such as LOC and COL having the above structure,
There is a problem in that the device can be bonded and electrically connected only by itself, and only the function and capacity of the device alone can be obtained by the device alone.

【0009】この発明は、装置単体で、デバイス単体の
機能および容量しか得られないという問題点を除去した
優れた装置を提供することを目的とする。
[0009] The present invention is a device itself, and to provide a <br/> excellent device removing the problem that give only the functions and capacity of the device itself.

【0010】[0010]

【課題を解決するための手段】本発明に係る樹脂封止
半導体装置は、上部デバイスの複数の電極と複数のリー
ドの主面とを接続する複数の第1ボンディングワイヤ
と、下部デバイスの複数の電極と複数のリードの主面と
を接続する複数の第2ボンディングワイヤとを有してお
り、上部デバイスと下部デバイスとは、上部デバイスの
端部が下部デバイスの端部とは平面的に異なるように、
かつ互いの電極が形成された面が略同一方向を向くよう
に配置されたものである。
Resin sealed according to the present invention SUMMARY OF THE INVENTION <br/> semiconductor device, a plurality of electrodes and a plurality of Lee upper device
Plural First Bonding Wires Connected to Main Surface of Node
And the main surfaces of the plurality of electrodes and the plurality of leads of the lower device.
And a plurality of second bonding wires for connecting
The upper device and the lower device are
So that the edge is different from the edge of the lower device in a plane
And the surfaces on which the electrodes are formed face in substantially the same direction.
It is arranged in.

【0011】[0011]

【作用】本発明は、装置当りの機能および容量が増加
し、集積度を向上することができる。
According to the present invention, the function and capacity per device are increased, and the degree of integration can be improved.

【0012】[0012]

【実施例】図1は本発明に係る樹脂封止半導体装置の第
1実施例を示す概略断面図であり、図2は図1の樹脂を
破断した斜視図である。図において、12は上部デバイ
ス、13はこの上部デバイス12と同じデバイスサイズ
の下部デバイス、14はリードフレームの第1内部リー
ドであり、この第1内部リード14は、その詳細を図3
に示すように上部デバイス12と下部デバイス13との
接着部分に設けられている。そして、この第1内部リー
ド14の表面には、第1絶縁性電着樹脂層15があらか
じめ電着されており、第1内部リード14の裏面には第
2絶縁性電着樹脂層16があらかじめ電着されている。
ここで、電着樹脂はリードフレームの最終工程に電着さ
れ、アクリル系(アニオン型電着樹脂)、エポキシ系
(カチオン型電着樹脂)を使用している。この組成は主
骨格樹脂、水溶性官能基、架橋成分、中和剤、添加剤、
助剤、硬化触媒、希釈剤などである。この電着樹脂をリ
ードフレームの周りを被う様にする。この厚さは15〜
30μmであり、ダイスボンドの時に熱圧着によって接
着される(熱80〜150℃、荷重0.2〜1.0k
g)。17は第2内部リードであり、この第2内部リー
ド17の裏面には図3に示すように第2絶縁性電着樹脂
層16があらかじめ電着されている。18は図3に示す
ように、第1内部リード14および第2内部リード17
上に設けたボンディングワイヤ用の金属被膜、19はボ
ンディングパッド、20は金属被膜18とボンディング
パッド19とを電気的に接続するボンディングワイヤで
ある。
FIG. 1 is a schematic sectional view showing a first embodiment of a resin-sealed semiconductor device according to the present invention, and FIG. 2 is a perspective view in which the resin of FIG. 1 is cut away. In the drawing, 12 is an upper device, 13 is a lower device having the same device size as the upper device 12, 14 is a first internal lead of a lead frame, and the first internal lead 14 is shown in detail in FIG.
As shown in the figure, the upper device 12 and the lower device 13 are provided at the bonding portion. A first insulating electrodeposition resin layer 15 is previously electrodeposited on the surface of the first internal lead 14, and a second insulating electrodeposition resin layer 16 is previously electrodeposited on the back surface of the first internal lead 14. Electrodeposited.
Here, the electrodeposited resin is electrodeposited in the final step of the lead frame, and an acrylic (anionic electrodeposited resin) or an epoxy (cationic electrodeposited resin) is used. This composition is composed of a main skeleton resin, a water-soluble functional group, a crosslinking component, a neutralizing agent, an additive,
Auxiliaries, curing catalysts, diluents and the like. This electrodeposited resin covers the lead frame. This thickness is 15 ~
30 μm and bonded by thermocompression bonding at the time of die bonding (heat: 80 to 150 ° C., load: 0.2 to 1.0 k)
g). Reference numeral 17 denotes a second internal lead. A second insulating electrodeposited resin layer 16 is electrodeposited on the back surface of the second internal lead 17 as shown in FIG. Reference numeral 18 denotes a first internal lead 14 and a second internal lead 17 as shown in FIG.
A metal film for a bonding wire provided above, 19 is a bonding pad, and 20 is a bonding wire for electrically connecting the metal film 18 and the bonding pad 19.

【0013】なお、ボンディングワイヤ用の金属被膜1
8上には第1絶縁性電着樹脂層15を電着しないように
する。これはリード裏面の電着樹脂が金属被膜18を被
った場合ワイヤボンディングを行う時に金属接合できな
いからである。また、第1絶縁性電着樹脂層15および
第2絶縁性電着樹脂層16は、例えば15〜30μmの
厚さであり、それ以下になるとデバイス表面と内部リー
ドとの絶縁性が、信頼性試験によって低下することが懸
念される。
The metal film 1 for the bonding wire
The first insulating electrodeposition resin layer 15 is not electrodeposited on the upper surface 8. This is because if the electrodeposition resin on the back surface of the lead is covered with the metal film 18, metal bonding cannot be performed when performing wire bonding. Further, the first insulating electrodeposition resin layer 15 and the second insulating electrodeposition resin layer 16 have a thickness of, for example, 15 to 30 μm. It is feared that it will be reduced by the test.

【0014】また、上部デバイス12と下部デバイス1
3のデバイスサイズを同じにした場合を示し、しかも上
部デバイス12と下部デバイス13の各ボンディングパ
ッド19を片側、例えば長辺に集めた構造とし、近くに
ボンディングしなければいけない第2内部リード17を
LOCタイプとし、第1内部リード14の引き廻しはC
OLタイプとしている。
The upper device 12 and the lower device 1
3 shows the case where the device size is the same, and furthermore, the bonding pads 19 of the upper device 12 and the lower device 13 are formed on one side, for example, on the long side, and the second internal lead 17 which must be bonded nearby is provided. LOC type, and the routing of the first internal lead 14 is C
OL type.

【0015】次に、上記構成による樹脂封止半導体装置
の製造工程について説明する。まず、第1内部リード1
4および第2内部リード17上に、ボンディング用の金
属被膜18を形成する。そして、上部デバイス12と下
部デバイス13との接着部分に設けられる第1内部リー
ド14の表面に、第1絶縁性電着樹脂層15を電着する
と共に、この第1内部リード14の裏面に、第2絶縁性
電着樹脂層16を電着する。そして、第2内部リード1
7の裏面に、第2絶縁性電着樹脂層16を電着する。そ
して、第1内部リード14を挟んで上部デバイス12を
第1絶縁性電着樹脂層15により熱圧着し、下部デバイ
ス13を第2絶縁性電着樹脂層16により熱圧着し、第
2内部リード17を第2絶縁性電着樹脂層16により下
部デバイスに熱圧着し、例えば80〜150℃で10〜
30分で硬化させる。その後、上部デバイス12および
下部デバイス13の各ボンディングパッド19と、第1
内部リード14および第2内部リード17の各金属被膜
18とをボンディングワイヤ20でボンディングして、
上部デバイス12と下部デバイス13とを電気的に導通
する。そして、全体を樹脂7で封止する。
Next, the steps of manufacturing the resin-encapsulated semiconductor device having the above-described configuration will be described. First, the first internal lead 1
A metal film 18 for bonding is formed on the fourth and second internal leads 17. Then, a first insulating electrodeposited resin layer 15 is electrodeposited on a surface of the first internal lead 14 provided at a bonding portion between the upper device 12 and the lower device 13, and a back surface of the first internal lead 14 is The second insulating electrodeposited resin layer 16 is electrodeposited. And the second internal lead 1
7, a second insulating electrodeposited resin layer 16 is electrodeposited. Then, the upper device 12 is thermocompression-bonded with the first insulating electrodeposition resin layer 15 with the first internal lead 14 interposed therebetween, and the lower device 13 is thermocompression-bonded with the second insulating electrodeposition resin layer 16. 17 is thermocompression-bonded to the lower device by the second insulating electrodeposition resin layer 16, for example, at 80 to 150 ° C.
Let cure in 30 minutes. Thereafter, each bonding pad 19 of the upper device 12 and the lower device 13 is
Bonding each metal film 18 of the internal lead 14 and the second internal lead 17 with a bonding wire 20
The upper device 12 and the lower device 13 are electrically connected. Then, the whole is sealed with resin 7.

【0016】なお、上部デバイス12のボンディングパ
ッド19へのワイヤボンディングの際、上部デバイス1
2の裏面の受けがないため、上部デバイス12がクラッ
クを起こし易いので、上部デバイス12の裏面側で、こ
のボンディングパッド19に対向する部分には、第1内
部リード14を引き廻し、上部デバイス12にクラック
が生じないようにすることも必要である。
When wire bonding the upper device 12 to the bonding pad 19, the upper device 1
2, the upper device 12 is liable to crack. Therefore, on the back surface of the upper device 12, the first internal lead 14 is laid around the bonding pad 19, and the upper device 12 is closed. It is also necessary to prevent cracks from occurring in

【0017】また、図4は上部デバイス21と下部デバ
イス22のデバイスサイズを同じにし、各ボンディング
パッド19を短辺に集めた構造である。
FIG. 4 shows a structure in which the upper device 21 and the lower device 22 have the same device size, and the bonding pads 19 are gathered on the short side.

【0018】また、図5は上部デバイス23と下部デバ
イス24のデバイスサイズを同じにし、各ボンディング
パッド19を短辺および長辺の1辺ずつに集めた構造で
ある。
FIG. 5 shows a structure in which the device sizes of the upper device 23 and the lower device 24 are the same, and the bonding pads 19 are collected on one side of the short side and one side of the long side.

【0019】図6は本発明に係る樹脂封止半導体装置の
第2実施例を示す概略断面図であり、図7は図6の樹脂
を破断した斜視図である。この第2実施例では、上部デ
バイス25のデバイスサイズに対して、下部デバイスサ
イズ26のデバイスサイズを大きくした場合を示す。
FIG. 6 is a schematic sectional view showing a second embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 7 is a perspective view in which the resin of FIG. 6 is cut away. In the second embodiment, a case where the device size of the lower device size 26 is made larger than the device size of the upper device 25 is shown.

【0020】なお、この第2実施例の製造工程について
は、図1と同様であり、その詳細な説明を省略する。
The manufacturing steps of the second embodiment are the same as those in FIG. 1, and a detailed description thereof will be omitted.

【0021】[0021]

【発明の効果】以上詳細に説明したように、本発明によ
れば、上部デバイスと下部デバイスとが、互いの端部が
平面的に異なるように、かつ互いの電極が形成された面
が略同一方向に向くように配置された上で、上部デバイ
ス及び下部デバイスのそれぞれの複数の電極が共に複数
のリードの一方の面に対して接続されているという構成
としたので、1つのパッケージに対する集積度が向上す
る効果がある。
As described in detail above, according to the present invention ,
If the upper device and the lower device are
Surfaces that are different from each other in plane and on which electrodes are formed
Are placed so that they face in substantially the same direction.
Multiple electrodes for each of the
Is connected to one surface of the lead of the package, so that the degree of integration in one package is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る樹脂封止半導体装置の第1実施例
を示す断面図である。
FIG. 1 is a sectional view showing a first embodiment of a resin-sealed semiconductor device according to the present invention.

【図2】図1における樹脂を破断した斜視図である。FIG. 2 is a perspective view in which the resin in FIG. 1 is cut away.

【図3】図2の一部詳細な斜視図である。FIG. 3 is a partially detailed perspective view of FIG. 2;

【図4】図1におけるボンディングパッドをデバイスの
短辺に設けた場合の斜視図である。
FIG. 4 is a perspective view when the bonding pad in FIG. 1 is provided on a short side of the device.

【図5】図1におけるボンディングパッドをデバイスの
短辺および長辺の一辺ずつに設けた場合の斜視図であ
る。
FIG. 5 is a perspective view in a case where bonding pads in FIG. 1 are provided on each of a short side and a long side of the device.

【図6】本発明に係る樹脂封止半導体装置の第2実施例
を示す断面図である。
FIG. 6 is a sectional view showing a second embodiment of the resin-sealed semiconductor device according to the present invention.

【図7】図6の樹脂を一部破断した斜視図である。FIG. 7 is a perspective view in which the resin of FIG. 6 is partially broken.

【図8】従来の樹脂封止半導体装置を示す断面図であ
る。
FIG. 8 is a sectional view showing a conventional resin-sealed semiconductor device.

【図9】従来の他の樹脂封止半導体装置を示す断面図で
ある。
FIG. 9 is a sectional view showing another conventional resin-sealed semiconductor device.

【符号の説明】[Explanation of symbols]

12,21,23,25 上部デバイス 13,22,24,26 下部デバイス 14 第1内部リード 15 第1絶縁性電着樹脂層 16 第2絶縁性電着樹脂層 17 第2内部リード 12, 21, 23, 25 Upper device 13, 22, 24, 26 Lower device 14 First internal lead 15 First insulating electrodeposition resin layer 16 Second insulating electrodeposition resin layer 17 Second internal lead

Claims (10)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 複数の電極を有する下部デバイスと、A lower device having a plurality of electrodes; 前記下部デバイス上に配置された複数のリードと、A plurality of leads arranged on the lower device; 前記複数のリード上に配置された上部デバイスと、An upper device disposed on the plurality of leads; 前記上部デバイスの前記複数の電極と前記複数のリードThe plurality of electrodes and the plurality of leads of the upper device
の主面とを接続する複数の第1ボンディングワイヤと、A plurality of first bonding wires connecting the main surface of 前記下部デバイスの前記複数の電極と前記複数のリードThe plurality of electrodes and the plurality of leads of the lower device
の前記主面とを接続する複数の第2ボンディングワイヤPlurality of second bonding wires connecting to the main surface
と、When, 前記上部及び下部デバイスと、前記第1及び第2ボンデThe upper and lower devices, and the first and second bonds
ィングワイヤとを封止する樹脂とを有しており、And a resin for sealing the 前記上部デバイスと前記下部デバイスとは、前記上部デThe upper device and the lower device are connected to the upper device.
バイスの端部が前記下部デバイスの端部とは平面的に異The end of the vise is planarly different from the end of the lower device.
なるように、かつ前記上部デバイスの複数の電極が形成And a plurality of electrodes of the upper device are formed
された面と前記下部デバイスの複数の電極が形成されたSurface and a plurality of electrodes of the lower device are formed
面とが略同一方向に向くように配置されていることを特It is noted that they are arranged so that
徴とする樹脂封止型半導体装置。A resin-encapsulated semiconductor device.
【請求項2】 請求項1記載の樹脂封止型半導体装置に2. The resin-sealed semiconductor device according to claim 1,
おいて、And 前記上部デバイスは、前記複数のリード上に第1絶縁性The upper device has a first insulating property on the plurality of leads.
接着樹脂層を介して固定されており、It is fixed via an adhesive resin layer, 前記複数のリードは、前記下部デバイス上に第2の絶縁The plurality of leads may have a second insulation on the lower device.
性接着樹脂層を介して固定されていることを特徴とするCharacterized by being fixed via a conductive adhesive resin layer
樹脂封止型半導体装置。Resin-sealed semiconductor device.
【請求項3】 請求項1記載の樹脂封止型半導体装置に3. The resin-sealed semiconductor device according to claim 1,
おいて、And 前記上部デバイスと前記下部デバイスとは互いに異なるThe upper device and the lower device are different from each other
大きさを有することを特徴とする樹脂封止型半導体装Resin-sealed type semiconductor device characterized by having a size
置。Place.
【請求項4】 請求項1〜3のいずれか一つに記載され4. The method according to claim 1, wherein:
た樹脂封止型半導体装置において、Resin-encapsulated semiconductor device, 前記複数のリードの前記主面上の前記第1及び第2ボンThe first and second bonding pads on the main surface of the plurality of leads
ディングワイヤが接続される部分には金属皮膜が設けらThe metal film is provided at the part where the
れていることを特徴とする樹脂封止型半導体装置。A resin-encapsulated semiconductor device, comprising:
【請求項5】 複数の電極を有する下部デバイス上に複5. The method according to claim 5, wherein the lower device has a plurality of electrodes.
数のリードを配置する工程と、Placing a number of leads; 前記複数のリード上に、複数の電極を有する上部デバイAn upper device having a plurality of electrodes on the plurality of leads;
スを配置する工程と、Placing the source, 前記上部デバイスの前記複数の電極と前記複数のリードThe plurality of electrodes and the plurality of leads of the upper device
の主面とを第1ボンディングワイヤによって接続する工For connecting to the main surface of the substrate by a first bonding wire
程と、About 前記下部デバイスの前記複数の電極と前記複数のリードThe plurality of electrodes and the plurality of leads of the lower device
の前記主面とを第2ボンディングワイヤによって接続すIs connected to the main surface by a second bonding wire.
る工程と、Process, 前記上部及び下部デバイスと、前記第1及び第2ボンデThe upper and lower devices, and the first and second bonds
ィングワイヤとを樹脂によって封止する工程とを有するEncapsulating the wiring wire with a resin.
ことを特徴とする樹脂封止型半導体装置の製造方法。A method for manufacturing a resin-encapsulated semiconductor device, comprising:
【請求項6】 請求項5記載の樹脂封止型半導体装置の6. The resin-encapsulated semiconductor device according to claim 5,
製造方法において、In the manufacturing method, 前記上部デバイスと前記下部デバイスとは、前記上部デThe upper device and the lower device are connected to the upper device.
バイスの電極形成面と前記下部デバイスの電極形成面とAn electrode forming surface of the vice and an electrode forming surface of the lower device;
が略同一方向に向くように配置されることを特徴とするAre arranged so as to face in substantially the same direction.
樹脂封止型半導体装置の製造方法。A method for manufacturing a resin-sealed semiconductor device.
【請求項7】 請求項5記載の樹脂封止型半導体装置の7. The resin-encapsulated semiconductor device according to claim 5,
製造方法において、In the manufacturing method, 前記上部デバイスは、前記複数のリード上に第1絶縁性The upper device has a first insulating property on the plurality of leads.
接着樹脂層を介して固定され、Fixed through an adhesive resin layer, 前記複数のリードは、前記下部デバイス上に第2の絶縁The plurality of leads may have a second insulation on the lower device.
性接着樹脂層を介して固定されることを特徴とする樹脂Characterized in that it is fixed via a conductive adhesive resin layer
封止型半導体装置の製造方法。A method for manufacturing a sealed semiconductor device.
【請求項8】 請求項5記載の樹脂封止型半導体装置の8. The resin-encapsulated semiconductor device according to claim 5,
製造方法において、In the manufacturing method, 前記上部デバイスと前記下部デバイスとは互いに異なるThe upper device and the lower device are different from each other
大きさを有することを特徴とする樹脂封止型半導体装置Resin-sealed semiconductor device having a size
の製造方法。Manufacturing method.
【請求項9】 請求項5記載の樹脂封止型半導体装置の9. The resin-encapsulated semiconductor device according to claim 5,
製造方法において、In the manufacturing method, 前記上部デバイスと前記下部デバイスとは、前記上部デThe upper device and the lower device are connected to the upper device.
バイスの端部と前記下部デバイスの端部とが平面的に異The end of the device and the end of the lower device are planarly different.
なるように配置されることを特徴とする樹脂封止型半導Characterized by being arranged so as to be
体装置の製造方法。Manufacturing method of body device.
【請求項10】 請求項5〜9のいずれか一つに記載さ10. The method according to claim 5, wherein
れた樹脂封止型半導体装置の製造方法において、In the method of manufacturing a resin-encapsulated semiconductor device, 前記複数のリードの前記主面上の前記第1及び第2ボンThe first and second bonding pads on the main surface of the plurality of leads
ディングワイヤが接続される部分には金属皮膜が設けらThe metal film is provided at the part where the
れることを特徴とする樹脂封止型半導体装置の製造方Of manufacturing a resin-encapsulated semiconductor device characterized by the following:
法。Law.
JP673193A 1993-01-19 1993-01-19 Resin-sealed semiconductor device and method of manufacturing the same Expired - Fee Related JP3200488B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP673193A JP3200488B2 (en) 1993-01-19 1993-01-19 Resin-sealed semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP673193A JP3200488B2 (en) 1993-01-19 1993-01-19 Resin-sealed semiconductor device and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH06216313A JPH06216313A (en) 1994-08-05
JP3200488B2 true JP3200488B2 (en) 2001-08-20

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ID=11646387

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Country Link
JP (1) JP3200488B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181165A (en) * 1994-12-26 1996-07-12 Nec Kyushu Ltd Semiconductor integrated circuit
JP3768761B2 (en) 2000-01-31 2006-04-19 株式会社日立製作所 Semiconductor device and manufacturing method thereof
JP3953327B2 (en) * 2002-01-21 2007-08-08 Necトーキン株式会社 Batteries and electric double layer capacitors
TWI270194B (en) * 2004-09-09 2007-01-01 United Test And Assembly Ct S Multi-die IC package and manufacturing method

Also Published As

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