JPH0621125A - Manufacture of semiconductor package - Google Patents

Manufacture of semiconductor package

Info

Publication number
JPH0621125A
JPH0621125A JP17536692A JP17536692A JPH0621125A JP H0621125 A JPH0621125 A JP H0621125A JP 17536692 A JP17536692 A JP 17536692A JP 17536692 A JP17536692 A JP 17536692A JP H0621125 A JPH0621125 A JP H0621125A
Authority
JP
Japan
Prior art keywords
die pad
lead frame
chip
bonded
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17536692A
Other languages
Japanese (ja)
Inventor
Satoru Matsuya
悟 松舎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP17536692A priority Critical patent/JPH0621125A/en
Publication of JPH0621125A publication Critical patent/JPH0621125A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Injection Moulding Of Plastics Or The Like (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the occurrence of package cracks at the time of surface mounting by bonding an IC chip, which is bonded on a die pad, and a lead frame, which is formed on a polyimide tape that is stuck to the outer surface of the die pad, and performing resin sealing only on the upper side of the die pad. CONSTITUTION:An IC chip 3 is bonded on a die pad 1 corresponding to the bottom area of a package body comprising metal by using a die bonding agent such as Ag paste. An Al electrode on the IC chip 3 and a lead frame 6 are bonded by using Au wires 7. In the manufacturing method of the lead frame at this time, a polyimide tape 4 is stuck at the outer surface part of the die pad 1, and the lead frame 6 is bonded by using a bonding agent 5. Thus, the separation of the rear surface of the lead frame and the resin, which induces the trouble generated when the entire mounting on the surface is heated, can be removed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体の組立工程にお
ける半導体パッケージの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor package in a semiconductor assembly process.

【０００２】[0002]

【従来の技術】従来の技術としては、図２に示す半導体
パッケージの製造方法が知られていた。これは金属から
成るダイパッド１上にＩＣチップ３をダイボンド剤２を
用いて接着し、ＩＣチップ上のＡｌ電極とリードフレー
ム６とをＡｕワイヤ７を用いてワイヤボンディング接合
した後、エポキシ樹脂８でトランスファーモールドする
と言う広く一般的に知られた方法であった。2. Description of the Related Art As a conventional technique, a method of manufacturing a semiconductor package shown in FIG. 2 has been known. This is because the IC chip 3 is adhered to the die pad 1 made of metal by using the die bonding agent 2, the Al electrode on the IC chip and the lead frame 6 are wire-bonded and joined by using the Au wire 7, and then the epoxy resin 8 is used. It was a widely known method called transfer molding.

【０００３】[0003]

【発明が解決しようとする課題】しかし、前述の従来の
技術では、パッケージ全体がエポキシ樹脂で封止されて
いる為に、ＩＣチップの発熱に対する熱抵抗がある程度
大きくなり、パワーＩＣの動作寿命を低下させると言う
問題と、ＩＲリフローで代表される様なパッケージ全体
加熱方式による表面実装方法では、ダイパッド裏面とエ
ポキシ樹脂が剥離し、Ａｕワイヤの断線しいてはパッケ
ージ外部にまで達するクラックの発生と言う大きな２つ
の問題点を有していた。However, in the above-mentioned conventional technique, since the entire package is sealed with the epoxy resin, the thermal resistance against heat generation of the IC chip is increased to some extent and the operating life of the power IC is extended. In the surface mounting method by the whole package heating method represented by IR reflow, the back surface of the die pad is peeled off from the epoxy resin, and the Au wire is broken and the crack reaches the outside of the package. It had two major problems.

【０００４】そこで本発明の目的とするところは、ＩＣ
チップを搭載したダイパッド外周部にポリイミドテープ
を貼り巡らし、その上に接着させたリードフレームにボ
ンディングすることによって、ダイパッドをパッケージ
の外部に引き出し熱抵抗を最低限に抑えると共に、ダイ
パッド上側のみ樹脂封止することによってパッケージク
ラックを誘発させるダイパッド裏面とエポキシ樹脂の剥
離を構造的に回避し、表面実装時のパッケージクラック
の発生を防ぐものである。Therefore, the object of the present invention is to provide an IC
By sticking a polyimide tape around the periphery of the die pad on which the chip is mounted and bonding it to a lead frame bonded on top of it, the die pad is pulled out of the package to minimize thermal resistance, and only the upper side of the die pad is resin-sealed. By doing so, peeling of the epoxy resin from the back surface of the die pad, which induces package cracks, is structurally avoided, and the occurrence of package cracks during surface mounting is prevented.

【０００５】[0005]

【課題を解決するための手段】本発明の半導体パッケー
ジの製造方法は、半導体の組立工程の中で、金属から成
るダイパッド上にＩＣチップを接着し、ＩＣチップ電極
とリードフレームとをワイヤボンディング接合後、樹脂
封止するものにおいて、ダイパッド上に接着されたＩＣ
チップとダイパッド外周部に貼り巡らされたポリイミド
テープ上に形成されたリードフレームとをボンディング
し、ダイパッド上側のみ樹脂封止することを特徴とす
る。According to a method of manufacturing a semiconductor package of the present invention, an IC chip is adhered to a die pad made of metal during a semiconductor assembling process, and an IC chip electrode and a lead frame are wire-bonded to each other. Later, in the case of resin-sealing, the IC adhered on the die pad
It is characterized in that a chip and a lead frame formed on a polyimide tape attached to the outer peripheral portion of the die pad are bonded and only the upper side of the die pad is resin-sealed.

【０００６】[0006]

【作用】本発明の上記構造によれば、パッケージの熱抵
抗の低減と表面実装時に発生するパッケージクラックを
回避することが出来る。According to the above structure of the present invention, it is possible to reduce the thermal resistance of the package and to avoid package cracks that occur during surface mounting.

【０００７】[0007]

【実施例】以下に本発明の実施例を図面に基づいて説明
する。図１（ａ）は、本発明の半導体パッケージの製造
方法の縦断面図である。金属から成るパッケージボディ
の底面積相当のダイパッド１上にＡｇペースト等のダイ
ボンド剤２を用いてＩＣチップ３を接着し、ＩＣチップ
上のＡｌ電極とリードフレーム６とを、Ａｕワイヤ７を
用いてボンディングしている様子を示している。この
際、リードフレームの作成方法としては、図１（ｂ）の
本発明の半導体パッケージの製造方法の平面図に示す様
に、ダイパッド１の外周部にポリイミドテープ４を貼り
巡らし、その上に接着剤５を用いてリードフレーム６を
接着するものである。この場合に使用する接着剤として
は、高純度タイプのものを使用する事が望ましく、それ
以外の場合には耐湿性の評価において、接着剤が原因と
なって端子間リークを引き起こす危険性がある。また、
ポリイミドテープとリードフレームとの密着性をアップ
する為に、ポリイミドテープ上のリードフレームの上に
更にポリイミドテープを貼り付ける方法、つまりリード
フレームをポリイミドテープではさんでしまう方法も採
用することが出来る。こうして作成されたリードフレー
ムが前述のとおりＡｕワイヤ７を用いてボンディングさ
れる訳であるが、その際のワイヤループ高さとしては、
完成品での薄型化を目指して出来るだけ低く抑える様に
したい。その後ＩＣチップを外部環境から保護する為に
エポキシ樹脂８で封止することになるが、この際前述の
リードフレーム上のＩＣチップ搭載側のみを封止する様
にする。この構造によって、表面実装の全体加熱時に発
生する不具合を誘発させる、リードフレーム裏面と樹脂
の剥離とを取り除くことが出来る。また、樹脂封止する
場合の面積としては、ダイパッドの外周から内側１ｍｍ
程度の範囲が望ましい。こうして樹脂とダイパッドエッ
ジまでの距離を確保する事によって、樹脂封止時にモー
ルドバリ等が発生しても、品質上問題となるパッケージ
外部のリード端子にまで及ぶのを防ぐ事が出来るからで
ある。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a vertical cross-sectional view of the semiconductor package manufacturing method of the present invention. An IC chip 3 is bonded onto a die pad 1 of a metal package body corresponding to the bottom area of the package using a die bonding agent 2 such as Ag paste, and an Al electrode on the IC chip and a lead frame 6 are attached using an Au wire 7. It shows a state of bonding. At this time, as a method for producing the lead frame, as shown in the plan view of the method for manufacturing a semiconductor package of the present invention in FIG. 1B, a polyimide tape 4 is stuck around the outer periphery of the die pad 1 and adhered thereon. The lead frame 6 is bonded by using the agent 5. In this case, it is desirable to use a high-purity type adhesive as the adhesive used. In other cases, there is a risk of causing leakage between terminals due to the adhesive when evaluating moisture resistance. . Also,
In order to improve the adhesion between the polyimide tape and the lead frame, a method of further adhering the polyimide tape on the lead frame on the polyimide tape, that is, a method of sandwiching the lead frame with the polyimide tape can be adopted. The lead frame thus created is bonded by using the Au wire 7 as described above, and the wire loop height at that time is as follows.
I would like to keep it as low as possible in order to make the finished product thinner. After that, the IC chip is sealed with the epoxy resin 8 in order to protect it from the external environment. At this time, only the IC chip mounting side on the lead frame is sealed. With this structure, it is possible to remove the peeling of the resin and the back surface of the lead frame, which causes a defect that occurs when the entire surface mounting is heated. The area for resin sealing is 1 mm inside from the outer periphery of the die pad.
A range of degrees is desirable. By securing the distance between the resin and the edge of the die pad in this way, even if mold burrs or the like occur during resin encapsulation, it is possible to prevent them from reaching the lead terminals outside the package, which is a quality problem.

【０００８】[0008]

【発明の効果】以上述べたように本発明によれば、金属
から成るダイパッド上にＩＣチップを接着し、ＩＣチッ
プ電極とリードフレームとをボンディング接合後、樹脂
封止するものにおいて、ダイパッド上に接着されたＩＣ
チップとダイパッド外周部に貼り巡らされたポリイミド
テープ上に形成されたリードフレームとをボンディング
し、ダイパッド上側のみ樹脂封止することによって、パ
ッケージの熱抵抗低減と表面実装技術によるパッケージ
全体加熱時に発生するパッケージクラックを回避するこ
とが出来る。As described above, according to the present invention, an IC chip is adhered onto a die pad made of metal, an IC chip electrode and a lead frame are bonded and bonded, and then sealed with resin. Bonded IC
This occurs when the chip and the lead frame formed on the polyimide tape attached to the outer periphery of the die pad are bonded and the upper side of the die pad is resin-sealed to reduce the thermal resistance of the package and heat the entire package by surface mounting technology. Package cracks can be avoided.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体パッケージの製造方法の縦断面
図および平面図である。FIG. 1 is a vertical sectional view and a plan view of a method for manufacturing a semiconductor package of the present invention.

【図２】従来の半導体パッケージの製造方法の縦断面図
である。FIG. 2 is a vertical cross-sectional view of a conventional semiconductor package manufacturing method.

【符号の説明】[Explanation of symbols]

１…ダイパッド ２…ダイボンド剤 ３…ＩＣチップ ４…ポリイミドテープ ５…接着剤 ６…リードフレーム ７…Ａｕワイヤ ８…モールド剤 1 ... Die pad 2 ... Die bond agent 3 ... IC chip 4 ... Polyimide tape 5 ... Adhesive agent 6 ... Lead frame 7 ... Au wire 8 ... Molding agent

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体の組立工程の中で、金属から成るダ
イパッド上にＩＣチップを接着し、ＩＣチップ電極とリ
ードフレームとをボンディング接合後、樹脂封止するも
のにおいて、ダイパッド上に接着されたＩＣチップと、
ダイパッド外周部に貼り巡らされたポリイミドテープ上
に形成されたリードフレームとをボンディングし、ダイ
パッド上側のみ樹脂封止することを特徴とする半導体パ
ッケージの製造方法。1. In a semiconductor assembly process, an IC chip is adhered to a die pad made of metal, an IC chip electrode and a lead frame are bonded and bonded, and then resin-sealed. IC chip,
A method of manufacturing a semiconductor package, which comprises bonding a lead frame formed on a polyimide tape attached to an outer peripheral portion of a die pad, and resin-sealing only an upper side of the die pad.
JP17536692A 1992-07-02 1992-07-02 Manufacture of semiconductor package Pending JPH0621125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17536692A JPH0621125A (en) 1992-07-02 1992-07-02 Manufacture of semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17536692A JPH0621125A (en) 1992-07-02 1992-07-02 Manufacture of semiconductor package

Publications (1)

Publication Number Publication Date
JPH0621125A true JPH0621125A (en) 1994-01-28

Family

ID=15994836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17536692A Pending JPH0621125A (en) 1992-07-02 1992-07-02 Manufacture of semiconductor package

Country Status (1)

Country Link
JP (1) JPH0621125A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100981052B1 (en) * 2009-02-25 2010-09-08 카이네틱스 주식회사 Printed circuit board for heat dissipation of led and fabricating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100981052B1 (en) * 2009-02-25 2010-09-08 카이네틱스 주식회사 Printed circuit board for heat dissipation of led and fabricating method thereof

Similar Documents

Publication Publication Date Title
TWI379367B (en) Chip packaging method and structure thereof
JP2972096B2 (en) Resin-sealed semiconductor device
JPH08111491A (en) Semiconductor device
JPH0621317A (en) Manufacture of semiconductor package
JPH05335474A (en) Resin sealed semiconductor device
JPH0777257B2 (en) Lead frame
JPH0621125A (en) Manufacture of semiconductor package
JP2694871B2 (en) Semiconductor device
JP2589520B2 (en) Method for manufacturing resin-encapsulated semiconductor device
JP2634249B2 (en) Semiconductor integrated circuit module
JPH0547988A (en) Semiconductor device
JP3036339B2 (en) Semiconductor device
JPS63293963A (en) Resin-sealed semiconductor device
KR100308899B1 (en) semiconductor package and method for fabricating the same
JPS60113932A (en) Assembling process of resin sealed semiconductor device
US5960261A (en) Method for manufacturing semiconductor package
JP2551354B2 (en) Resin-sealed semiconductor device
JPH0294463A (en) Semiconductor device
JPH08162596A (en) Lead frame and semiconductor device
JP2002246528A (en) Method of manufacturing semiconductor device
JPH05129469A (en) Resin-sealed semiconductor device
JPH07130782A (en) Manufacture of package-type semiconductor device having heatsink
JPH05308088A (en) Semiconductor device and its manufacture
JPS6123347A (en) Semiconductor device
JPS59155160A (en) Resin seal type electronic part utilizing lead frame