JPH05335474A - Resin sealed semiconductor device - Google Patents
Resin sealed semiconductor deviceInfo
- Publication number
- JPH05335474A JPH05335474A JP4141876A JP14187692A JPH05335474A JP H05335474 A JPH05335474 A JP H05335474A JP 4141876 A JP4141876 A JP 4141876A JP 14187692 A JP14187692 A JP 14187692A JP H05335474 A JPH05335474 A JP H05335474A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor device
- resin
- insulating base
- external connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体素子を樹脂封止
する樹脂封止形の半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-encapsulated semiconductor device for encapsulating a semiconductor element with a resin.
【０００２】[0002]
【従来の技術】従来、このような分野の技術としては、
例えば、実開昭５５−４２３４９６号、特開平１−１２
３４２８号、特開昭５９−９２５５６号、特開昭６１−
２３６１３０号公報に開示されるものがあった。図３は
かかる従来の半導体素子の樹脂封止形の装置の構成図で
ある。2. Description of the Related Art Conventionally, as a technique in such a field,
For example, Japanese Utility Model Application Laid-Open No. 55-423496, JP-A 1-12.
3428, JP-A-59-92556, JP-A-61-
Some were disclosed in Japanese Patent No. 236130. FIG. 3 is a block diagram of such a conventional resin-sealed type semiconductor device.
【０００３】この図に示すように、１はアイランド２上
に接合され、その縁部に多数の電極３を有する半導体素
子、４はこの半導体素子１の周囲に設けられ、例えばＡ
ｕ等のワイヤ５によって前記電極３に接続される外部リ
ード、６はこの外部リード４の一部、前記ワイヤ５、前
記アイランド２及び半導体素子１を封止するパッケージ
本体である。As shown in this figure, a semiconductor element 1 is bonded on an island 2 and has a large number of electrodes 3 on its edge, and 4 are provided around the semiconductor element 1.
An external lead connected to the electrode 3 by a wire 5 such as u is a package body that seals a part of the external lead 4, the wire 5, the island 2 and the semiconductor element 1.
【０００４】このように構成された樹脂封止形の半導体
素子においては、半導体素子１の取り付け時のずれを考
慮すると、アイランド２のサイズを半導体素子１より大
きい寸法に設定する必要があり、また、外部リード４の
先端とアイランド２間の距離リード間をリードフレーム
加工、ワイヤリング性を考慮する必要がある。In the resin-encapsulated semiconductor element thus configured, the size of the island 2 must be set larger than the size of the semiconductor element 1 in consideration of the deviation when the semiconductor element 1 is attached. The distance between the tip of the external lead 4 and the island 2 It is necessary to consider the lead frame processing and the wiring property between the leads.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、上記構
成の半導体装置では、半導体素子が高集積化されるにし
たがい、大型化、厚型化されると共にリードの本数が増
大すると、多数のリードを半導体素子周辺に配置する場
合に、該リード先端を一定の余裕を持って配列しなけれ
ばならないため、半導体素子からリードまでの距離が長
くなり、信号処理の遅延が生じることになる。また、パ
ッケージ本体に収納可能な半導体素子サイズ余裕がなく
なるため、パッケージ本体が大型化、厚型化する。However, in the semiconductor device having the above-mentioned structure, as the semiconductor element is highly integrated and the size and thickness of the semiconductor element are increased and the number of leads is increased, a large number of leads are formed in the semiconductor device. In the case of arranging in the periphery of the element, the lead tips must be arranged with a certain margin, so that the distance from the semiconductor element to the lead becomes long and the signal processing is delayed. In addition, the size of the semiconductor element that can be accommodated in the package body is reduced, so that the package body becomes larger and thicker.
【０００６】本発明は、以上述べた半導体装置の信号処
理速度遅延とパッケージ本体の大型化、厚型化を解決す
るために、パッケージ本体の幅方向寸法と厚さ方向寸法
を小さくし、信号処理速度の向上とパッケージの小型化
・薄型化を図ることができる樹脂封止半導体装置を提供
することを目的とする。In order to solve the signal processing speed delay of the semiconductor device and the increase in size and thickness of the package body described above, the present invention reduces the width direction dimension and the thickness direction dimension of the package body to perform signal processing. An object of the present invention is to provide a resin-encapsulated semiconductor device capable of improving speed and reducing the size and thickness of a package.
【０００７】[0007]
【課題を解決するための手段】本発明は、上記目的を達
成するために、樹脂封止半導体装置において、多数の突
起電極を有する半導体素子と、その半導体素子の周縁部
に形成される絶縁基材と、その絶縁基材上に位置し、そ
の絶縁基材内部の前記突起電極に直接接続される外部接
続リードを設けるようにしたものである。In order to achieve the above object, the present invention provides a resin-encapsulated semiconductor device having a semiconductor element having a large number of protruding electrodes and an insulating substrate formed on the peripheral portion of the semiconductor element. A material and an external connection lead located on the insulating base material and directly connected to the protruding electrode inside the insulating base material are provided.
【０００８】[0008]
【作用】本発明によれば、上記したように、突起電極が
半導体素子のどの位置にでも設けられるため、外部接続
リードとの接続に自由度が大きく、外部接続リードとの
接続が突起電極とワイヤを用いないで直接接続できる。
したがって、半導体装置の高機能、高集積化に伴い半導
体素子が大きくなっても、パッケージ本体の幅方向の寸
法も、厚さ方向の寸法も大きい寸法に設定する必要がな
くなり、小型化・薄型化を図ることができる。According to the present invention, as described above, since the protruding electrode is provided at any position of the semiconductor element, there is a high degree of freedom in connection with the external connection lead, and the connection with the external connection lead can be achieved with the protruding electrode. It can be connected directly without using wires.
Therefore, even if the size of the semiconductor element becomes larger due to the higher functionality and higher integration of the semiconductor device, it is not necessary to set the size in the width direction and the size in the thickness direction of the package body to be large, and the size and thickness can be reduced. Can be planned.
【０００９】[0009]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示す樹
脂封止半導体装置の平面図、図２は図１のＡ−Ａ線断面
図である。これらの図において、１１は半導体素子であ
り、表面に厚さ１μｍ〜３μｍの厚さを有するポリイミ
ド系あるいはプラズマ窒化膜等の保護膜１３と、半田、
Ａｕ等の突起電極１２を有している。１４はポリイミド
系あるいはエポキシ系等の絶縁基材であり、半導体素子
１１上面にある外部接続リード１５の突起電極１２と接
続される領域以外のインナーリード下面に位置し、イン
ナーリードの振動防止と、インナーリードと半導体素子
１１が接続される時のメカニカル応力保護を兼ねてい
る。外部接続リード１５のインナーリードと突起電極１
２は、リフローあるいは熱圧着で接続し、その後、樹脂
封止成形により完成する。なお、１６はパッケージ本体
である。Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is a plan view of a resin-encapsulated semiconductor device showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line AA of FIG. In these figures, 11 is a semiconductor element, and a protective film 13 such as a polyimide-based or plasma nitride film having a thickness of 1 μm to 3 μm on the surface, solder,
It has a protruding electrode 12 made of Au or the like. Reference numeral 14 denotes an insulating base material such as a polyimide-based or epoxy-based material, which is located on the lower surface of the inner lead other than the area of the external connection lead 15 on the upper surface of the semiconductor element 11 connected to the protruding electrode 12, and prevents the inner lead from vibrating. It also serves as mechanical stress protection when the inner lead and the semiconductor element 11 are connected. Inner lead of external connection lead 15 and protruding electrode 1
2 is connected by reflow or thermocompression bonding, and then completed by resin sealing molding. In addition, 16 is a package main body.
【００１０】この実施例においては、アイランドが省略
されている。次に、図４は本発明の他の実施例を示す樹
脂封止半導体装置の平面図、図５は図４のＢ−Ｂ線断面
図である。なお、上記実施例と同様の部分については、
同じ番号を付し、その説明は省略する。これらの図に示
すように、この実施例においては、アイランド１７が付
加され、半導体素子１１の突起電極１２と外部接続リー
ド１５を接続する前にアイランド１７に半導体素子１１
をＡｕ，Ａｇ，絶縁ペースト等のダイスボンド材１９で
ダイスボンディングし、アイランド１７と共通電位（接
地電位を含む）を有する外部接続リード１５ａとを、そ
の外部接続リード１５ａの部分１５ｂにおいて、重ね合
わせて配置し、その後、樹脂封止成形を行い完成する。
なお、１８はアイランド１７のサポートである。In this embodiment, islands are omitted. Next, FIG. 4 is a plan view of a resin-sealed semiconductor device showing another embodiment of the present invention, and FIG. 5 is a sectional view taken along line BB of FIG. In addition, about the same part as the above embodiment,
The same numbers are assigned and the description thereof is omitted. As shown in these figures, in this embodiment, an island 17 is added, and the semiconductor element 11 is added to the island 17 before connecting the protruding electrode 12 of the semiconductor element 11 and the external connection lead 15.
Is die-bonded with a die bond material 19 such as Au, Ag or an insulating paste, and the island 17 and the external connection lead 15a having a common potential (including ground potential) are superposed on each other at a portion 15b of the external connection lead 15a. Then, resin encapsulation molding is performed to complete the process.
Reference numeral 18 is a support for the island 17.
【００１１】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of the present invention, and these modifications are not excluded from the scope of the present invention.
【００１２】[0012]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、次のような効果を奏することができる。 （１）突起電極が半導体素子のどの位置にでも設けられ
るため、外部接続リードとの接続に自由度が大きく、外
部接続リードとの接続が突起電極とワイヤを用いないで
直接接続できるため、半導体装置の高機能、高集積化に
伴い半導体素子が大きくなっても、パッケージ本体の幅
方向の寸法も、厚さ方向の寸法も大きい寸法に設定する
必要がなくなり、小型化・薄型化を図ることができる。As described above in detail, according to the present invention, the following effects can be obtained. (1) Since the protruding electrode is provided at any position of the semiconductor element, there is a high degree of freedom in connection with the external connection lead, and the external connection lead can be connected directly without using the protruding electrode and the wire. Even if the semiconductor element grows in size due to the high functionality and high integration of the device, it is not necessary to set the size of the package body in the width direction and the size in the thickness direction to be large, and the size and thickness can be reduced. You can
【００１３】（２）このように、パッケージ本体の幅方
向の寸法も、厚さ方向の寸法も大きい寸法に設定する必
要がなくなり、小型化・薄型化により、同時に信号処理
速度の向上を図ることができる。 （３）半導体素子上で突起電極と接続される領域外のイ
ンナーリードに絶縁基材を貼り付けたことにより、イン
ナーリードの振動を防止することができるようになり、
接続部の接合安定性と信頼性が得られる。(2) As described above, it is not necessary to set the size of the package body in the width direction and the size in the thickness direction to be large, and the signal processing speed can be improved at the same time by downsizing and thinning. You can (3) By virtue of attaching the insulating base material to the inner lead outside the region connected to the bump electrode on the semiconductor element, it is possible to prevent the inner lead from vibrating.
The joint stability and reliability of the connection portion can be obtained.
【００１４】（４）同時にインナーリード接続時のメカ
ニカル応力ダメージを絶縁基材が吸収することにより、
半導体素子の損傷を防止することができる。 （５）半導体素子の回路で電源、ＧＨＤパターンの突起
電極を半導体素子上に複数設け、外部接続リードを半導
体素子の中央に通る１本と接続することによって、電
源、ＧＨＤパターンの長さが短くなり、その上容易にな
る。したがって、電源、ＧＨＤ抵抗増によるノイズ余裕
が増し、同時に半導体素子を小さくでき、高集積化を図
ることができる。(4) At the same time, the insulating base material absorbs mechanical stress damage at the time of connecting the inner leads,
It is possible to prevent damage to the semiconductor element. (5) The length of the power supply and the GHD pattern is shortened by providing a plurality of power source and GHD pattern projecting electrodes on the semiconductor element in the circuit of the semiconductor element and connecting the external connection lead with one passing through the center of the semiconductor element. It will be easier as well. Therefore, the noise margin is increased due to the increase in the power source and the GHD resistance, and at the same time, the semiconductor element can be downsized and high integration can be achieved.
【００１５】（６）大電流が必要なパワー半導体素子に
おいても複数のＧＨＤを設けることにより、電流の分流
が容易になり、動作時に発生する熱量を低下させること
ができ、直接リードを伝わって熱を逃すことができるの
で、極めて熱抵抗の小さい、放熱性に優れた樹脂封止半
導体装置を得ることができる。 （７）アイランド付きのリードフレームにおいては、半
導体素子をダイスボンド材によってボンディングし、ア
イランドと外部接続リードフレームとを重ね合わせるよ
うに配置して、半導体素子の突起電極と接続し封止樹脂
で成形する場合、封止樹脂成形時の樹脂圧力に対して上
下のバタツキ強度が増し、パッケージ本体中の半導体素
子の位置が安定した最適化構造が得られる。(6) By providing a plurality of GHDs even in a power semiconductor device that requires a large current, the shunting of the current can be facilitated, the amount of heat generated during operation can be reduced, and the heat can be directly transmitted through the leads. Therefore, it is possible to obtain a resin-sealed semiconductor device having extremely low heat resistance and excellent heat dissipation. (7) In a lead frame with an island, the semiconductor element is bonded with a die bond material, the island and the external connection lead frame are arranged so as to overlap with each other, connected to the protruding electrode of the semiconductor element, and molded with the sealing resin. In this case, the upper and lower flapping strength is increased with respect to the resin pressure at the time of molding the sealing resin, and an optimized structure in which the position of the semiconductor element in the package body is stable is obtained.
【図１】本発明の実施例を示す樹脂封止半導体装置の平
面図である。FIG. 1 is a plan view of a resin-sealed semiconductor device showing an embodiment of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】従来の半導体素子の樹脂封止形の装置の構成図
である。FIG. 3 is a configuration diagram of a conventional resin-sealed type semiconductor device.
【図４】本発明の他の実施例を示す樹脂封止半導体装置
の平面図である。FIG. 4 is a plan view of a resin-encapsulated semiconductor device showing another embodiment of the present invention.
【図５】図４のＢ−Ｂ線断面図である。5 is a cross-sectional view taken along the line BB of FIG.
１１ 半導体素子 １２ 突起電極 １３ 保護膜 １４ 絶縁基材 １５ 外部接続リード １５ａ 共通電位を有する外部接続リード １７ アイランド １８ アイランドのサポート １９ ダイスボンド材 11 Semiconductor Element 12 Projection Electrode 13 Protective Film 14 Insulating Base Material 15 External Connection Lead 15a External Connection Lead with Common Potential 17 Island 18 Island Support 19 Dice Bonding Material
Claims (3)
と、 （ｂ）該半導体素子の周縁部に形成される絶縁基材と、 （ｃ）該絶縁基材上に位置し、該絶縁基材内部の前記突
起電極に直接接続される外部接続リードを具備する樹脂
封止半導体装置。1. A semiconductor element having a large number of protruding electrodes; (b) an insulating base material formed on a peripheral portion of the semiconductor element; (c) an insulating base material located on the insulating base material; A resin-encapsulated semiconductor device comprising an external connection lead that is directly connected to the protruding electrode inside a substrate.
アイランドを固定してなる請求項１記載の樹脂封止半導
体装置。2. The resin-encapsulated semiconductor device according to claim 1, wherein an island is fixed on the side of the semiconductor element opposite to the side of the protruding electrode.
接続リードを重ね合わせたことを特徴とする請求項２記
載の樹脂封止半導体装置。3. The resin-sealed semiconductor device according to claim 2, wherein the island and the external connection lead having a common potential are overlapped with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4141876A JPH05335474A (en) | 1992-06-03 | 1992-06-03 | Resin sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4141876A JPH05335474A (en) | 1992-06-03 | 1992-06-03 | Resin sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05335474A true JPH05335474A (en) | 1993-12-17 |
Family
ID=15302222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4141876A Pending JPH05335474A (en) | 1992-06-03 | 1992-06-03 | Resin sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05335474A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19525388A1 (en) * | 1994-07-12 | 1996-01-25 | Mitsubishi Electric Corp | Semiconductor chip electronic component with current input and output conductor |
| JPH1065089A (en) * | 1996-08-13 | 1998-03-06 | Hitachi Ltd | Lead frame and its manufacturing method and semiconductor device using the same |
| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
| US6268646B1 (en) * | 1996-08-27 | 2001-07-31 | Hitachi Cable, Ltd. | Lead frame for lead on chip |
| US6858919B2 (en) * | 2000-03-25 | 2005-02-22 | Amkor Technology, Inc. | Semiconductor package |
| DE19549750B4 (en) * | 1994-07-12 | 2005-07-14 | Mitsubishi Denki K.K. | Electronic component with anodisch gebontetem lead frame |
| US7755199B2 (en) * | 2001-01-08 | 2010-07-13 | Jiahn-Chang Wu | Flexible lead surface-mount semiconductor package |
| US7880313B2 (en) * | 2004-11-17 | 2011-02-01 | Chippac, Inc. | Semiconductor flip chip package having substantially non-collapsible spacer |
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| JP2017204660A (en) * | 2017-08-29 | 2017-11-16 | スミダコーポレーション株式会社 | Manufacturing method of electronic component |
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-
1992
- 1992-06-03 JP JP4141876A patent/JPH05335474A/en active Pending
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| US5900671A (en) * | 1994-07-12 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Electronic component including conductor connected to electrode and anodically bonded to insulating coating |
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| US6181009B1 (en) | 1994-07-12 | 2001-01-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with a lead frame and insulating coating |
| DE19525388A1 (en) * | 1994-07-12 | 1996-01-25 | Mitsubishi Electric Corp | Semiconductor chip electronic component with current input and output conductor |
| US6310395B1 (en) | 1994-07-12 | 2001-10-30 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with anodically bonded contact |
| US6268647B1 (en) | 1994-07-12 | 2001-07-31 | Mitsubishi Denki Kabushiki Kaisha | Electronic component with an insulating coating |
| DE19549750B4 (en) * | 1994-07-12 | 2005-07-14 | Mitsubishi Denki K.K. | Electronic component with anodisch gebontetem lead frame |
| JPH1065089A (en) * | 1996-08-13 | 1998-03-06 | Hitachi Ltd | Lead frame and its manufacturing method and semiconductor device using the same |
| US6268646B1 (en) * | 1996-08-27 | 2001-07-31 | Hitachi Cable, Ltd. | Lead frame for lead on chip |
| US6858919B2 (en) * | 2000-03-25 | 2005-02-22 | Amkor Technology, Inc. | Semiconductor package |
| KR100583494B1 (en) * | 2000-03-25 | 2006-05-24 | 앰코 테크놀로지 코리아 주식회사 | Semiconductor package |
| US7755199B2 (en) * | 2001-01-08 | 2010-07-13 | Jiahn-Chang Wu | Flexible lead surface-mount semiconductor package |
| US7880313B2 (en) * | 2004-11-17 | 2011-02-01 | Chippac, Inc. | Semiconductor flip chip package having substantially non-collapsible spacer |
| US8405230B2 (en) | 2004-11-17 | 2013-03-26 | Stats Chippac Ltd. | Semiconductor flip chip package having substantially non-collapsible spacer and method of manufacture thereof |
| US7989931B2 (en) | 2007-09-26 | 2011-08-02 | Stats Chippac Ltd. | Integrated circuit package system with under paddle leadfingers |
| US8153478B2 (en) | 2007-09-26 | 2012-04-10 | Stats Chippac Ltd. | Method for manufacturing integrated circuit package system with under paddle leadfingers |
| JP2017204660A (en) * | 2017-08-29 | 2017-11-16 | スミダコーポレーション株式会社 | Manufacturing method of electronic component |
| JP2019071488A (en) * | 2019-02-06 | 2019-05-09 | ローム株式会社 | Semiconductor device |
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