JPH06188744A - Method for generating error verification and correction code incorporated bit array - Google Patents
Method for generating error verification and correction code incorporated bit arrayInfo
- Publication number
- JPH06188744A JPH06188744A JP4137512A JP13751292A JPH06188744A JP H06188744 A JPH06188744 A JP H06188744A JP 4137512 A JP4137512 A JP 4137512A JP 13751292 A JP13751292 A JP 13751292A JP H06188744 A JPH06188744 A JP H06188744A
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- Prior art keywords
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- bit string
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- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】電子計算機や通信システムに於け
るビット列の送受信に於いて発生するビット誤りの検証
と訂正。[Industrial application] Verification and correction of bit errors that occur during transmission and reception of bit strings in electronic computers and communication systems.
【0002】[0002]
【従来の技術】送受信に於けるビット列のビット誤りを
検証訂正する簡易な符号を組込む簡易な方法がない。2. Description of the Related Art There is no simple method for incorporating a simple code for verifying and correcting a bit error in a bit string in transmission and reception.
【0003】[0003]
【発明が解決しようとする課題】電子計算機や通信シス
テムに於けるビット列の送受信に於いて発生する1個の
ビット誤りを検証訂正できる簡易な符号を論理演算を主
とする簡易な方法で組込んだビット列を生成する方法。SUMMARY OF THE INVENTION A simple code capable of verifying and correcting one bit error occurring in transmission / reception of a bit string in an electronic computer or a communication system is incorporated by a simple method mainly composed of logical operations. How to generate a bit string.
【0004】[0004]
【課題を解決するための手段】図1に於いてまず、基幹
ビット列(1)の位置符号(2)から配列符号(3)を
作りその配列符号からビット列特性正符号(4)を作
り、そのビット列特性正符号からビット列特性補符号
(5)を作る。次に、基幹ビット列(1)にビット列特
性補符号(5)を連結したビット列(6)を作り、その
(6)に奇数、又は偶数パリティを設定し、そのパリテ
ィビット(7)を付して誤り検証訂正組込ビット列
(8)を作る。In FIG. 1, first, an array code (3) is created from a position code (2) of a basic bit string (1), and a bit string characteristic positive code (4) is created from the array code. A bit string characteristic complementary code (5) is created from the bit string characteristic positive code. Next, a bit string (6) is formed by concatenating the bit string characteristic complementary code (5) to the basic bit string (1), and odd or even parity is set in the bit string (6), and the parity bit (7) is added. An error verification / correction built-in bit string (8) is created.
【0005】[0005]
【作用】まず、誤り検証訂正組込ビット列は、 1)(2のn乗)の長さの基幹ビット列に対して(2の
n乗+n+2)で、基幹ビット列の長さが大きくなるほ
ど誤り検証訂正組込ビット列の基幹ビット列に対する長
さの比率が小さくなる。その関係を表1で示す。 2)その始点のビット位置から(2のn乗+1)個目の
ビット位置まで、即ち基幹ビット列とビット列特性補符
号の最高位の桁まで(主ビット列と呼ぶ)はビット符号
1が常に奇数個であり、次のビット位置の(2のn乗+
2)個目のビット位置から(2のn乗+n+2)個目の
終点のビット位置まで、即ちビット列特性補符号の最高
位の桁を除いた部分とパリティビット(副ビット列と呼
ぶ)はビット符号1は、誤り検証訂正符号組込ビット列
のパリティが奇数パリティならば偶数個になり、偶数パ
リティならば奇数個になる。次に、送受信に於ける1ビ
ット誤りの検証は、 3)まず、誤り検証訂正符号組込ビット列がパリティ誤
りになり更に受信した主ビット列でビット符号1が偶数
個になった場合は主ビット列に於いてビット誤りが発生
していることを検証し、副ビット列でビット符号1が奇
数パリティのとき奇数個、偶数パリティのとき偶数個で
あった場合は副ビット列に於いてビット誤りが発生して
いることを検証する。受信した主ビット列に於いて1ビ
ット誤りがある場合の訂正は、 4)まず、受信したビット列特性補符号の最高位の桁の
符号を補の2進数に変換した符号を作り(符号Aと呼
ぶ)、次に受信した主ビット列の基幹ビット列に相当す
る部分からビット列特性正符号を作る(符号Bと呼
ぶ)。次に、符号Aと符号Bとで桁の位取りを同順にし
てEORの符号を作り、更にその符号の各桁を補の2進
数に変換した2進符号を作る(符号Cと呼ぶ)。そし
て、符号Cのすべての桁が0になったときは符号Aを受
信したビット列特性補符号の部分にすることによってビ
ット誤りを訂正する。 5)もし符号Cのすべての桁が0でなければ主ビット列
の基幹ビット列に相当する部分からビット列特性正符号
を作る(符号Dと呼ぶ)。そして、符号Dと受信したビ
ット列特性補符号の部分とで桁の位取りを同順にしてE
ORの符号を作り、更にその符号の各桁を補の2進数に
変換した2進符号を作る(符号Eと呼ぶ)。そうすれば
符号Eは主ビット列の基幹ビット列に相当する部分に於
けるビット誤りのビット位置を示すビット位置符号にな
り、その示す基幹ビット列に相当する部分のビット位置
のビット符号を補の2進数に変換することによってビッ
ト誤りを訂正する。次に、受信した副ビット列に於い
て、1ビット誤りがある場合の訂正は、 6)受信した主ビット列の基幹ビット列に相当する部分
からビット列特性補符号を作りそれを受信したビット列
特性補符号の部分と交換することによってビット誤りを
訂正する。First, the error-verification-correction built-in bit string is (1) (2 n + n + 2) with respect to the basic bit string having a length of (2 n-th power), and the error-verification correction is performed as the length of the basic bit string increases. The length ratio of the embedded bit string to the basic bit string becomes small. The relationship is shown in Table 1. 2) Bit code 1 is always an odd number from the start bit position to the (nth power of 2 + 1) th bit position, that is, up to the most significant digit of the basic bit string and the bit string characteristic complementary code (called the main bit string). And the next bit position is (2 to the nth power +
2) From the 2nd bit position to the bit position of the (nth power of 2 + n + 2) th end point, that is, the part excluding the highest digit of the bit string characteristic complementary code and the parity bit (called a sub bit string) are bit codes. 1 is an even number if the parity of the error verification and correction code embedded bit string is an odd parity, and an odd number if the parity is an even parity. Next, 1-bit error verification in transmission / reception is as follows. 3) First, if the error verification / correction code embedded bit string has a parity error and the received main bit string has an even number of bit codes 1, It is verified that a bit error has occurred in the sub-bit string. If the bit code 1 in the sub-bit string is odd-numbered parity and odd-numbered, and even-numbered parity is even number, a bit error occurs in the sub-bit string. Verify that The correction when there is a 1-bit error in the received main bit string is 4) First, the code of the highest digit of the received bit string characteristic complementary code is converted into a complementary binary number (called code A). ), And a bit string characteristic positive code is created from a portion corresponding to the basic bit string of the received main bit string (referred to as code B). Next, the code A and the code B are digitized in the same order to form an EOR code, and a binary code in which each digit of the code is converted into a complementary binary number (called a code C). Then, when all the digits of the code C have become 0, the code A is made a part of the received bit string characteristic complementary code to correct the bit error. 5) If all the digits of the code C are not 0, a bit string characteristic positive code is created from the part corresponding to the basic bit string of the main bit string (referred to as code D). Then, the digit D and the received bit string characteristic complementary code are arranged in the same order of the digits, and E
An OR code is created, and each digit of the code is converted into a complementary binary number to create a binary code (referred to as code E). Then, the code E becomes a bit position code indicating the bit position of the bit error in the part corresponding to the backbone bit string of the main bit string, and the bit code at the bit position of the part corresponding to the backbone bit string shown is the complementary binary number. Correct the bit error by converting to. Next, if there is a 1-bit error in the received sub-bit string, the correction is as follows: 6) A bit string characteristic complementary code is created from the part corresponding to the basic bit string of the received main bit string Correct the bit error by exchanging the part.
【0006】[0006]
【実施例】図2に於いて、まず、基幹ビット列(9)か
ら奇数パリティの誤り検証訂正符号組込ビット列(1
0)を作り送信する。そして、送信路に於いて1ビット
誤りが発生し受信したときそれが(11)になった場合
の検証と訂正を示す。まず、(11)が偶数パリティで
あるからビット誤りが発生していることが検証され、更
に(11)から主ビット列(12)、副ビット列(1
3)、基幹ビット列に相当するの部分(14)、及びビ
ット列特性補符号の部分(15)を作れば(12)のビ
ット符号1が偶数個であるから主ビット列にビット誤り
が発生していることを検証する。そこで、符号A(1
6)と符号B(17)を作り、それらのEORの符号
(18)から符号C(19)を作る。そして、(19)
のすべての桁が0であるから(16)を受信したビット
列特性補符号符号の部分にした(20)が訂正された誤
り検証訂正符号組込ビット列になる。次に、基幹ビット
列(21)から奇数パリティの誤り検証訂正符号組込ビ
ット列(22)を作り送信する。そして、送信路に於い
て1ビット誤りが発生し受信したときそれが(23)に
なった場合の検証と訂正を示す。まず、(23)が偶数
パリティであるからビット誤りが発生しており、更に
(23)の主ビット列(24)のビット符号1が偶数個
であるから主ビット列にビット誤りが発生していること
を検証する。そこで、上記のようにして符号C(25)
を作る。そうすれば(25)のすべての桁が0でないか
ら(24)の基幹ビット列に相当する部分(26)から
符号D(27)を作り、(27)と(23)のビット列
特性補符号の部分(28)とのEORの符号(29)を
作る。そして、更に(29)から符号E(30)を作
り、その示す(26)のビット位置のビット符号を補の
2進数に変換した(31)が訂正された誤り検証訂正符
号組込ビット列となる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 2, first, from a basic bit string (9) to an odd parity error verification correction code embedded bit string (1
0) is created and transmitted. Then, the verification and correction in the case where a 1-bit error occurs in the transmission path and it becomes (11) when received is shown. First, it is verified that a bit error has occurred because (11) is an even parity, and further, from (11) to the main bit string (12) and the sub bit string (1).
3), if the part (14) corresponding to the basic bit string and the part (15) of the bit string characteristic complementary code are created, since the bit code 1 of (12) is an even number, a bit error has occurred in the main bit string. Verify that. Therefore, the code A (1
6) and the code B (17) are created, and the code C (19) is created from the EOR code (18). And (19)
Since all the digits of 0 are 0, (20) which is a part of the bit string characteristic complementary code received from (16) becomes a corrected error verification correction code embedded bit string. Next, an odd-parity error-verification-correction-code-embedded bit string (22) is created from the basic bit string (21) and transmitted. Then, the verification and correction in the case where a 1-bit error occurs in the transmission path and it becomes (23) when received is shown. First, since (23) has an even parity, a bit error has occurred, and since the bit code 1 of the main bit string (24) of (23) is an even number, a bit error has occurred in the main bit string. To verify. Therefore, the code C (25) is set as described above.
make. Then, since all the digits of (25) are not 0, the code D (27) is created from the part (26) corresponding to the basic bit string of (24), and the part of the bit string characteristic complementary code of (27) and (23). Create a sign (29) of EOR with (28). Then, a code E (30) is further created from (29), and the bit code at the bit position of (26) shown therein is converted into a complementary binary number, and (31) becomes a corrected error verification correction code embedded bit string. .
【0007】[0007]
【発明の効果】電子計算機や通信システムに於けるビッ
ト列の送受信に於いて発生する1ビット誤りの検証と訂
正を行うことができる簡易な符号を組込んだビット列を
論理演算を主とする簡易な回路構成により高速で作成す
ることができる。EFFECT OF THE INVENTION A bit string incorporating a simple code capable of verifying and correcting a 1-bit error that occurs during transmission / reception of a bit string in an electronic computer or a communication system is a simple one mainly composed of logical operations. It can be created at high speed depending on the circuit configuration.
【図1】本方法の構成を示すブロック図で上方の部分が
その構成の各要素を示すブロック図、下方の部分が8ビ
ットのビット列の例でそれを示すブロック図である。FIG. 1 is a block diagram showing a configuration of the present method, an upper portion is a block diagram showing each element of the configuration, and a lower portion is a block diagram showing an example of an 8-bit bit string.
【図2】本方法により生成した誤り検証訂正符号組込ビ
ット列を使用した実施例を8ビットのビット列の例で示
すブロック図である。FIG. 2 is a block diagram showing an embodiment using an error verification / correction code embedded bit string generated by this method as an example of an 8-bit bit string.
(1)は基幹ビット列 (2)は位置符号 (3)は配列符号 (4)はビット列特性正符号 (5)はビット列特性補符号 (6)は基幹ビット列にビット列特性補符号を連結した
ビット列 (7)はパリティビット (8)は誤り検証訂正符号組込ビット列 (9)は基幹ビット列 (10)はビット誤り前の誤り検証訂正符号組込ビット
列 (11)は1ビット誤り後の誤り検証訂正符号組込ビッ
ト列 (12)は主ビット列 (13)は副ビット列 (14)は基幹ビット列に相当する部分 (15)はビット列特性補符号の部分 (16)は符号A (17)は符号B (18)はEOR結果の符号 (19)は符号C (20)はビット誤りが訂正された誤り検証訂正符号組
込ビット列 (21)は基幹ビット列 (22)はビット誤り前の誤り検証訂正符号組込ビット
列 (23)は1ビット誤り後の誤り検証訂正符号組込ビッ
ト列 (24)は主ビット列 (25)は符号C (26)は基幹ビット列に相当する部分 (27)は符号D (28)はビット列特性補符号の部分 (29)はEOR結果の符号 (30)は符号E (31)ビット誤りが訂正された誤り検証訂正符号組込
ビット列(1) is a basic bit string (2) is a position code (3) is an array code (4) is a bit string characteristic positive code (5) is a bit string characteristic complementary code (6) is a bit string in which the bit string characteristic complementary code is connected to the basic bit string ( 7) is a parity bit (8) is an error verification correction code embedded bit string (9) is a basic bit string (10) is an error verification correction code embedded bit string before bit error (11) is an error verification correction code after 1-bit error The built-in bit string (12) is the main bit string (13) is the sub bit string (14) corresponds to the backbone bit string (15) is the bit string characteristic complementary code (16) is the code A (17) is the code B (18) Is the code of the EOR result (19) is the code C (20) is the error verification and correction code in which the bit error is corrected (21) is the basic bit string (22) is the error verification and correction code before the bit error The embedded bit string (23) is an error verification correction code after a 1-bit error. The embedded bit string (24) is the main bit string (25) the code C (26) corresponds to the basic bit string (27) is the code D (28). Bit string characteristics Complementary code part (29) is the code of the EOR result (30) is the code E (31) Error verification correction code embedded bit string in which the bit error is corrected
─────────────────────────────────────────────────────
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【手続補正書】[Procedure amendment]
【提出日】平成4年5月11日[Submission date] May 11, 1992
【手続補正1】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】0004[Correction target item name] 0004
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【0004】[0004]
【課題を解決するための手段】図1に於いてまず、基幹
ビット列(1)の位置符号(2)から配列符号(3)を
作りその配列符号からビット列特性正符号(4)を作
り、そのビット列特性正符号からビット列特性補符号
(5)を作る。次に、基幹ビット列(1)にビット列特
性補符号(5)を連結したビット列(6)を作り、その
(6)に奇数、又は偶数パリティを設定し、そのパリテ
ィビット(7)を付したものを誤り検証訂正符号組込ビ
ント列(8)とする。In FIG. 1, first, an array code (3) is created from a position code (2) of a basic bit string (1), and a bit string characteristic positive code (4) is created from the array code. A bit string characteristic complementary code (5) is created from the bit string characteristic positive code. Next, a bit string (6) is formed by concatenating the bit string characteristic complementary code (5) to the basic bit string (1), and odd or even parity is set in the (6) and the parity bit (7) is added. Is an error verification / correction code built-in bin string (8).
Claims (1)
符号 1)まず、対象とする長さが2のn乗のビット列(基幹
ビット列と呼ぶ)に対してそのビット位置に一定の方向
に順序を定め、始点のビット位置から順次、各々のビッ
ト位置に対応する同一桁数で最高位の桁が1で、あとの
桁は2進法ですべて0の2進数の1000のように表示
する桁数がn+1桁の2進数からビット位置の順序で順
次、2進法の加算によって1づつ大きくなる2進数の1
001、1010のように表示する同一桁数でn+1桁
の2進数(位置符号と呼ぶ)を作り、その位置符号にそ
のビット位置のビット符号の0、又は1を2進法の乗算
によって0000、1010のように表示する、位置符
号と同一桁数でn+1桁の2進数を作る(配列符号と呼
ぶ)。 2)その配列符号の桁の位取りを同順にして排他的論理
和(EOR)のn+1桁の2進数を作る(ビット列特性
正符号と呼ぶ)。 3)そのビット列特性正符号の各桁の2進数を補の2進
数に変換したものを作る(ビット列特性補符号と呼
ぶ)。 誤り検証訂正符号組込ビット列 4)そして、基幹ビット列にビット列特性補符号を連結
した(2のn乗+n+1)個のビット位置のビット列を
作り、そのビット列に奇数パリティ、又は偶数パリティ
のパリティビットを設定し、それを付した(2のn乗+
n+2)個のビット位置のビット列を作る(誤り検証訂
正符号組込ビット列と呼ぶ)。 このようにして始点のビット位置からビット列特性補符
号の最高位の桁のビット位置までの部分はビット符号1
が常に奇数個で、次のビット位置から終点のビット位置
までのビット列のビット符号1は奇数パリティ、又は偶
数パリティに応じてそれぞれ偶数個、又は奇数個になる
ようにする。このビット列特性補符号を基幹ビット列に
連結することを特徴とする誤り検証訂正符号組込ビット
列の生成方法。1. A bit-sequence characteristic positive code and a bit-sequence characteristic complementary code 1) First, a target bit sequence whose length is 2 raised to the n-th power (referred to as a backbone bit sequence) is arranged in a certain direction at its bit position. The number of digits to be displayed, starting from the bit position of the starting point, the highest digit of the same number of digits corresponding to each bit position is 1, and the remaining digits are binary numbers such as 1000, which are all 0 in binary. Is a binary number 1 that increases sequentially by 1 from the binary number of n + 1 digits in the order of the bit position by the addition of the binary system.
A binary number of n + 1 digits (called a position code) with the same number of digits to be displayed as 001, 1010 is created, and the position code is multiplied by a binary code of 0 or 1 of the bit code of the bit position to obtain 0000, Displayed as 1010, a binary number of n + 1 digits is created with the same number of digits as the position code (called an array code). 2) The digits of the array code are arranged in the same order to form an n + 1 digit binary number of the exclusive OR (EOR) (called a bit string characteristic positive code). 3) A binary number of each digit of the bit string characteristic positive code is converted into a complementary binary number (called a bit string characteristic complementary code). Error verification / correction code embedded bit string 4) Then, a bit string of (2 to the power of n + n + 1) bit positions in which the bit string characteristic complementary code is concatenated to the basic bit string is created, and parity bits of odd parity or even parity are added to the bit string. Set and attach it (2 to the nth power +
A bit string of (n + 2) bit positions is created (referred to as an error verification / correction code embedded bit string). In this way, the portion from the bit position of the starting point to the bit position of the highest digit of the bit string characteristic complementary code is bit code 1
Is always an odd number, and the bit code 1 of the bit string from the next bit position to the end bit position is an even number or an odd number depending on the odd parity or the even parity, respectively. A method for generating an error-verification-correction-code-embedded bit string, characterized in that this bit string characteristic complementary code is concatenated to a basic bit string.
Priority Applications (1)
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---|---|---|---|
JP4137512A JPH06188744A (en) | 1992-04-14 | 1992-04-14 | Method for generating error verification and correction code incorporated bit array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4137512A JPH06188744A (en) | 1992-04-14 | 1992-04-14 | Method for generating error verification and correction code incorporated bit array |
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Publication Number | Publication Date |
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JPH06188744A true JPH06188744A (en) | 1994-07-08 |
Family
ID=15200404
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JP4137512A Pending JPH06188744A (en) | 1992-04-14 | 1992-04-14 | Method for generating error verification and correction code incorporated bit array |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996011515A1 (en) * | 1994-10-07 | 1996-04-18 | Robert Bosch Gmbh | Commutator |
-
1992
- 1992-04-14 JP JP4137512A patent/JPH06188744A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996011515A1 (en) * | 1994-10-07 | 1996-04-18 | Robert Bosch Gmbh | Commutator |
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