JPH06188242A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH06188242A JPH06188242A JP33918092A JP33918092A JPH06188242A JP H06188242 A JPH06188242 A JP H06188242A JP 33918092 A JP33918092 A JP 33918092A JP 33918092 A JP33918092 A JP 33918092A JP H06188242 A JPH06188242 A JP H06188242A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- interlayer insulating
- metal wiring
- film
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に多層配線を含む半導体装置とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including multi-layer wiring and a method of manufacturing the same.
【０００２】高度情報社会の進展と共に、半導体集積回
路は、いわゆるスケーリング則に沿って約３年で４倍の
速度で高集積化している。集積化技術は絶え間なく進歩
を続け、回路素子の微細化、高集積化に対応している。
配線の線幅は、Ｕ−ＬＳＩにおいて、サブミクロンサイ
ズからクォータミクロンサイズへと研究が進められてい
る。With the progress of the advanced information society, semiconductor integrated circuits have been highly integrated at a speed four times higher in about three years according to the so-called scaling law. The integration technology is constantly advancing, and is responding to miniaturization and high integration of circuit elements.
In the U-LSI, the line width of wiring is being researched from submicron size to quarter micron size.
【０００３】ＬＳＩの集積度向上に伴って、内部配線も
複雑化し、その占有面積が素子面積を凌ぐようになって
いる。そこで、半導体基板上における配線面積を減少さ
せ、かつ配線の自由度を増すため、多層配線化が推進さ
れている。たとえば、多層化はキロビットＤＲＡＭ時代
の２層からメガビットＤＲＡＭでは３〜４層配線へとな
ってきた。With the improvement in the degree of integration of LSIs, the internal wiring has become complicated, and the occupied area thereof exceeds the element area. Therefore, in order to reduce the wiring area on the semiconductor substrate and increase the degree of freedom of wiring, multilayer wiring has been promoted. For example, the number of layers has changed from two layers in the era of the kilobit DRAM to three to four layers of wiring in the megabit DRAM.
【０００４】[0004]
【従来の技術】多層配線技術は、導電性配線と層間絶縁
膜の交互積層、層間接続、各層の平坦化、低抵抗化等、
多くの個別技術が集大成されたものである。2. Description of the Related Art Multi-layer wiring technology includes alternating wiring of conductive wiring and interlayer insulating film, interlayer connection, flattening of each layer, reduction of resistance, etc.
It is the compilation of many individual technologies.
【０００５】図２は、従来の技術による代表的な多層配
線工程の例を示す断面図である。簡単のために２層配線
としたが、より多層化した場合も基本的には同じと考え
てよい。FIG. 2 is a sectional view showing an example of a typical multi-layer wiring process according to the prior art. Although two-layer wiring is used for the sake of simplicity, it can be basically considered to be the same even when the number of layers is increased.
【０００６】図２（Ａ）は、回路素子形成済の半導体基
板１１に下層金属配線１２を形成した状態を示す。たと
えば、厚い熱酸化膜（素子間分離膜）１８を形成した半
導体基板１１の能動領域にＭＯＳトランジスタを形成
し、絶縁膜１９を介して下層金属配線１２を形成してい
る。FIG. 2A shows a state in which the lower layer metal wiring 12 is formed on the semiconductor substrate 11 on which circuit elements have been formed. For example, a MOS transistor is formed in the active region of the semiconductor substrate 11 on which a thick thermal oxide film (element isolation film) 18 is formed, and a lower metal wiring 12 is formed via an insulating film 19.
【０００７】図２（Ｂ）は、上下の金属配線に対する層
間絶縁膜の形成とその平坦化プロセスを示す図である。
通常、層間絶縁膜１３には融点の低い酸化膜、たとえば
燐を含むＳｉＯ2 であるＰＳＧ、ボロンと燐を含むＳｉ
Ｏ2 であるＢＰＳＧ、ボロンを含むＳｉＯ2 であるＢＳ
Ｇ等が用いられる。FIG. 2B is a diagram showing the formation of an interlayer insulating film for the upper and lower metal wirings and the planarization process thereof.
Usually, the interlayer insulating film 13 is an oxide film having a low melting point, for example, PSG, which is SiO 2 containing phosphorus, or Si containing boron and phosphorus.
O 2 BPSG, boron-containing SiO 2 BS
G or the like is used.
【０００８】図２（Ａ）で示すように、下層金属配線を
終えたチップ表面には回路配線によって多数の凹凸が形
成されている。このまま層間絶縁膜の形成、さらに上層
の配線を行なうと、凹凸が一層増幅されてリソグラフィ
工程で段差による焦点ボケによってパターニング不良を
生じたり、段差によって堆積膜の被覆率、いわゆるステ
ップカバレージが低下し、配線歩留まりや信頼性が低下
する等の問題を生じる。As shown in FIG. 2A, a large number of irregularities are formed by circuit wiring on the surface of the chip where the lower metal wiring is finished. If the interlayer insulating film is formed as it is and wiring is further performed on the upper layer, the unevenness is further amplified to cause patterning failure due to defocusing due to a step in the lithography process, or the step reduces the coverage of the deposited film, so-called step coverage, This causes problems such as reduction in wiring yield and reliability.
【０００９】そこで、図２（Ｂ）に示すように、層間絶
縁膜１３を堆積した後、加熱することによって低融点ガ
ラスを軟化させ、流動化による平坦化（いわゆるグラス
リフロー）を行なう。たとえば、実線で示す表面が破線
で示す表面のように変化する。Therefore, as shown in FIG. 2B, after the interlayer insulating film 13 is deposited, the low melting glass is softened by heating and flattened by fluidization (so-called glass reflow). For example, the surface indicated by the solid line changes to the surface indicated by the broken line.
【００１０】この他の平坦化方法として、比較的よく用
いられる技術には、液状ガラスを塗布する法、いわゆる
スピンオングラス（ＳＯＧ）や、一旦凹凸のある層間絶
縁膜を形成した後、その上にホトレジスト層等を塗布し
て平坦面を形成し、その後、表面から必要量をエッチす
るエッチバック法等がある。As another flattening method, a relatively frequently used technique is a method of applying liquid glass, so-called spin-on-glass (SOG), or an interlayer insulating film having irregularities once formed and then formed thereon. There is an etch-back method in which a photoresist layer or the like is applied to form a flat surface, and then a necessary amount is etched from the surface.
【００１１】図２（Ｃ）は、平坦化した層間絶縁膜１３
上に上層金属配線１４を行なった状態を示す。層間絶縁
膜１３の所定位置に、下層金属配線１２の表面に達する
コンタクトホール１７を形成し、金属配線層を堆積し、
パターニングして上層金属配線１４を形成する。FIG. 2C shows a planarized interlayer insulating film 13
The state where the upper layer metal wiring 14 is provided is shown above. A contact hole 17 reaching the surface of the lower layer metal wiring 12 is formed at a predetermined position of the interlayer insulating film 13, and a metal wiring layer is deposited,
The upper metal wiring 14 is formed by patterning.
【００１２】図２は、例としてＭＯＳトランジスタに対
する２層配線についての説明であったが、集積回路素子
はその他にも多岐に亘る。たとえば、代表的な超ＬＳＩ
であるＤＲＡＭは、１メモリセルが１ケのＭＯＳトラン
ジスタと１ケのキャパシタからなる。Although FIG. 2 has been described with respect to the two-layer wiring for the MOS transistor as an example, there are various other integrated circuit elements. For example, a typical VLSI
In the DRAM, one memory cell consists of one MOS transistor and one capacitor.
【００１３】集積度が向上してメガビット時代に入る
と、素子微小化による利用可能表面積の減少で、キャパ
シタの蓄積電荷量を確保することが困難となり、３次元
キャパシタが実用化されている。When the degree of integration is improved and the megabit era is entered, it becomes difficult to secure the amount of accumulated charge of the capacitor due to the decrease in usable surface area due to the miniaturization of elements, and the three-dimensional capacitor has been put into practical use.
【００１４】このために、層間絶縁膜表面の凹凸は一段
と激しくなり、より一層の平坦化技術が求められてい
る。すなわち、図２で示したようなグラスリフローやＳ
ＯＧ等では対応しきれなくなっている。For this reason, the unevenness on the surface of the interlayer insulating film becomes more severe, and a further flattening technique is required. That is, the glass reflow or S as shown in FIG.
OG etc. can no longer handle it.
【００１５】[0015]
【発明が解決しようとする課題】新たな平坦化技術の１
つとして、グラスリフロー後に堆積膜を機械的研磨する
方法が提案されている。しかし、ステップカバレージの
良い減圧ＣＶＤ、たとえばプラズマＣＶＤで酸化膜を堆
積後、研磨すると、クラックが生じる危険がある。One of the new flattening techniques
As one, a method of mechanically polishing the deposited film after glass reflow has been proposed. However, if an oxide film is deposited by low pressure CVD with good step coverage, for example, plasma CVD, and then polished, there is a risk of cracking.
【００１６】本発明の目的は、平坦性と絶縁性に優れた
多層配線用の層間絶縁膜を備えた半導体装置およびその
製造方法を提供することである。An object of the present invention is to provide a semiconductor device provided with an interlayer insulating film for multi-layer wiring, which is excellent in flatness and insulation, and a manufacturing method thereof.
【００１７】[0017]
【課題を解決するための手段】本発明の層間絶縁膜は、
基本的に２層からなる。すなわち、本発明の半導体装置
は、回路素子を形成した半導体基板と、前記半導体基板
上に形成された下層金属配線と、該下層金属配線を被覆
し、平坦化した表面を有する引張り応力性ＳｉＯ2 系の
第１の層間絶縁膜と、該第１の層間絶縁膜を被覆する圧
縮応力性ＳｉＯ 2 系の第２の層間絶縁膜と、該第２の層
間絶縁膜上に形成された上層金属配線とを有する。The interlayer insulating film of the present invention comprises:
It basically consists of two layers. That is, the semiconductor device of the present invention
Is a semiconductor substrate on which circuit elements are formed, and the semiconductor substrate
Covering the lower layer metal wiring formed above and the lower layer metal wiring
And tensile stressed SiO having a flattened surface2System
A first interlayer insulating film and a pressure for covering the first interlayer insulating film.
Shrink stress SiO 2System second interlayer insulating film and the second layer
And an upper metal wiring formed on the inter-insulating film.
【００１８】[0018]
【作用】一般的に、プラズマＣＶＤで形成した酸化シリ
コン膜は、下地半導体基板に対して圧縮性応力を及ぼ
す。もし、プラズマＣＶＤで形成した圧縮応力性堆積膜
表面を研磨して平坦化すると、圧縮性応力は下地凹凸に
沿って局所的に不均一に残存する。このため、酸化膜に
マイクロクラックが生じ易いと考えられる。クラックは
絶縁不良の発生等につながる。In general, the silicon oxide film formed by plasma CVD exerts compressive stress on the underlying semiconductor substrate. If the surface of the compressive stress deposited film formed by plasma CVD is polished and flattened, the compressive stress locally remains uneven along the unevenness of the base. Therefore, it is considered that microcracks are likely to occur in the oxide film. Cracks lead to defective insulation.
【００１９】半導体基板に対して、引張り応力を及ぼす
第１の層間絶縁膜は、研磨してもクラックを生じること
が少ない。さらに、圧縮応力を及ぼす第２の層間絶縁膜
を直接重ねて堆積すると、応力歪が相殺される。The first interlayer insulating film exerting tensile stress on the semiconductor substrate is less likely to be cracked even if it is polished. Further, if the second interlayer insulating film that exerts compressive stress is directly overlaid and deposited, the stress strain is offset.
【００２０】第１の層間絶縁膜堆積後に、機械的技術を
行なって表面を平坦化し、その上に第２の層間絶縁膜を
堆積するので、上層金属配線は平坦な面上に行なうこと
ができる。After depositing the first interlayer insulating film, a mechanical technique is applied to planarize the surface and the second interlayer insulating film is deposited thereon, so that the upper metal wiring can be formed on the flat surface. .
【００２１】以下、本発明を実施例に基づいてより詳し
くのべる。Hereinafter, the present invention will be described in more detail based on examples.
【００２２】[0022]
【実施例】図１は、実施例による２層配線の主要工程を
示す断面図である。図示してあるのは集積回路の一部で
あり、半導体基板１に形成された回路素子は、図２と同
様のＭＯＳトランジスタである。EXAMPLE FIG. 1 is a sectional view showing the main steps of a two-layer wiring according to an example. A part of the integrated circuit is shown, and the circuit element formed on the semiconductor substrate 1 is a MOS transistor similar to that shown in FIG.
【００２３】本実施例では、常圧ＣＶＤとプラズマＣＶ
ＤとのＰＳＧ膜を用いるが、そのプロセス条件は概ね以
下のようなものである。In this embodiment, atmospheric pressure CVD and plasma CV are used.
The PSG film with D is used, and the process conditions are generally as follows.
【００２４】[0024]
【表１】 [Table 1]
【００２５】図１（Ａ）に示すように、厚いフィールド
絶縁膜、すなわち、熱酸化膜８で素子形成領域を分離し
たＳｉ単結晶ウエハからなる半導体基板１に、酸化膜形
成、多結晶Ｓｉ層堆積、ホトリソグラフィと選択エッチ
ングおよびイオン注入技術を利用して、ポリＳｉゲート
Ｇ、ソースＳ、ドレインＤ領域を形成する。さらに、電
極間絶縁膜９の形成、コンタクトホール６の形成を行な
い、下層金属配線２を形成する。As shown in FIG. 1A, a thick field insulating film, that is, a semiconductor substrate 1 made of a Si single crystal wafer in which element formation regions are separated by a thermal oxide film 8 is formed with an oxide film and a polycrystalline Si layer. A poly-Si gate G, a source S, and a drain D region are formed by using deposition, photolithography, selective etching, and ion implantation technique. Further, the interelectrode insulating film 9 and the contact hole 6 are formed to form the lower layer metal wiring 2.
【００２６】図１（Ａ）は、下層金属配線２上へ第１の
層間絶縁膜３を堆積した状態を示す。第１の層間絶縁膜
３は、引張り応力性ＳｉＯ2 系膜からなる。たとえば、
高融点金属等の下層金属配線２を行なった試料を、ＣＶ
Ｄ装置内に導入し、以下に述べるような常圧ＣＶＤによ
って第１の層間絶縁膜３を堆積する。FIG. 1A shows a state in which the first interlayer insulating film 3 is deposited on the lower metal wiring 2. The first interlayer insulating film 3 is made of a tensile stress SiO 2 based film. For example,
CV was applied to the sample on which the lower metal wiring 2 such as high melting point metal was formed.
Then, the first interlayer insulating film 3 is deposited by atmospheric pressure CVD as described below.
【００２７】試料を４００℃に保持し、この上に常圧で
ＳｉＨ4 、ＰＨ3 およびＯ2 を流すと、 ＳｉＨ4 ＋２Ｏ2 →ＳｉＯ2 ＋２Ｈ2 Ｏ ＳｉＨ4 ＋２Ｈ2 Ｏ→ＳｉＯ2 ＋４Ｈ2 ４ＰＨ3 ＋２Ｏ2 →２Ｐ2 Ｏ2 ＋６Ｈ2 等の反応が生じて試料上にＰＳＧ膜３が堆積する。この
ＰＳＧ膜３は代表的には１．０×１０-9ｄｙｎ／ｃｍ2
の応力を内蔵する。When the sample was kept at 400 ° C. and SiH 4 , PH 3 and O 2 were flown over it at normal pressure, SiH 4 + 2O 2 → SiO 2 + 2H 2 O SiH 4 + 2H 2 O → SiO 2 + 4H 2 4PH A reaction such as 3 + 2O 2 → 2P 2 O 2 + 6H 2 occurs and the PSG film 3 is deposited on the sample. The PSG film 3 is typically 1.0 × 10 −9 dyn / cm 2
Built-in stress.
【００２８】図１（Ａ）で示した下層金属配線２の下地
表面からの高さが約０．８μｍ（最大値）の場合、ＰＳ
Ｇ膜３の膜厚は、たとえば約２μｍとする。図１（Ｂ）
に示すように、次に、第１の層間絶縁膜３の研磨を行な
う。研磨は、いわゆるメカノケミカル方式であり、たと
えばロデール社製の研磨布ＩＣ６０と研磨剤ＷＳ１００
１（２倍希釈）を用いて１５０ｇ／ｃｍ2 の加圧下で行
なうことができる。この研磨工程によって厚さ約１μｍ
分のＰＳＧ膜を除去し、表面を平坦化する。When the height of the lower metal wiring 2 shown in FIG. 1 (A) from the underlying surface is about 0.8 μm (maximum value), PS
The film thickness of the G film 3 is, eg, about 2 μm. Figure 1 (B)
Then, the first interlayer insulating film 3 is polished as shown in FIG. Polishing is a so-called mechanochemical method, for example, polishing cloth IC60 and polishing agent WS100 manufactured by Rodel Co.
1 (2-fold dilution) can be performed under a pressure of 150 g / cm 2 . This polishing process results in a thickness of approximately 1 μm
Then, the PSG film is removed to flatten the surface.
【００２９】次に、研磨で平坦化した第１の層間絶縁膜
３上に、以下に述べるようなプラズマＣＶＤによって圧
縮応力性の第２の層間絶縁膜４を堆積する。まず、研磨
工程後、第１の層間絶縁膜３表面を軽く化学エッチング
する。ＮＨ 4 ＯＨ１：Ｈ2 Ｏ2 ４：Ｈ2 Ｏ２０の容積比
でエッチング液を作り、８０℃に加熱して試料を５分間
浸漬する。この処理でＳｉＯ2 系膜表面層が除去され、
研磨歪が緩和される。Next, the first interlayer insulating film flattened by polishing
3 on top of the substrate by plasma CVD as described below.
A second interlayer insulating film 4 having a contractive stress property is deposited. First, polishing
After the process, the surface of the first interlayer insulating film 3 is lightly chemically etched.
To do. NH FourOH1: H2O24: H2O20 volume ratio
Make an etching solution with and heat to 80 ℃ for 5 minutes.
Soak. This process makes SiO2The system membrane surface layer is removed,
Polishing strain is alleviated.
【００３０】次に、試料をプラズマＣＶＤ装置内に導入
する。試料温度を３８０℃に保持し、ＳｉＨ4 、ＰＨ3
およびＮ2 Ｏガスを全圧にして約１．０Ｔｏｒｒ流しな
がら減圧状態で放電させ、ガスプラズマを発生させる。
プラズマ内でガス分子は活性化される。Next, the sample is introduced into the plasma CVD apparatus. The sample temperature is maintained at 380 ° C, and SiH 4 , PH 3
And N 2 O gas at a total pressure of about 1.0 Torr and discharged under reduced pressure to generate gas plasma.
Gas molecules are activated in the plasma.
【００３１】この結果、ＳｉＨ4 とＮ2 Ｏの反応が生じ
てＰドープＳｉＯ2 、すなわちＰＳＧ膜が試料上に堆積
する。これが第２の層間絶縁膜４である。このプラズマ
ＣＶＤによるＰＳＧ膜は、Ｓｉ基板との間に代表的には
−１．０×１０-9ｄｙｎ／ｃｍ2 の圧縮性応力を発生さ
せる。As a result, a reaction between SiH 4 and N 2 O occurs, and P-doped SiO 2 , that is, a PSG film is deposited on the sample. This is the second interlayer insulating film 4. The PSG film formed by the plasma CVD typically generates compressive stress of −1.0 × 10 −9 dyn / cm 2 with the Si substrate.
【００３２】第２の層間絶縁膜４の厚さは約１μｍとす
る。下地表面が平坦化されているので、第２の層間絶縁
膜４の表面はほぼ平坦である。ＰＳＧ膜３とＰＳＧ膜４
は、大きさがほぼ等しく、符号が逆の応力を発生させ
る。このために、約１μｍの厚さをそれぞれ有する両Ｐ
ＳＧ膜間では、応力歪は相当程度相殺される。The thickness of the second interlayer insulating film 4 is about 1 μm. Since the underlying surface is flattened, the surface of the second interlayer insulating film 4 is almost flat. PSG film 3 and PSG film 4
Generate stresses of approximately equal magnitude but opposite signs. To this end, both Ps each having a thickness of about 1 μm
Between the SG films, the stress strain is canceled out to a large extent.
【００３３】図１（Ｃ）は、上層配線の形成工程を示
す。ホトリソグラフィと選択エッチングの技術を用い
て、所定の位置に第１の層間絶縁膜３および第２の層間
絶縁膜４を貫通するコンタクトホール（ビア孔）６を設
ける。FIG. 1C shows a step of forming an upper layer wiring. A contact hole (via hole) 6 penetrating the first interlayer insulating film 3 and the second interlayer insulating film 4 is provided at a predetermined position by using a technique of photolithography and selective etching.
【００３４】次に、Ａｌ等の上層金属配線を形成し、再
びホトリソグラフィの技術を用いてパターニングした上
層金属配線５を形成する。たとえば、Ａｌのスパッタリ
ングを用い、コンタクトホール６内にもＡｌを充填する
ようにすれば、上層、下層金属配線の接続が行なわれ
る。なお、コンタクトホール内の充填をポリＳｉや高融
点金属で前もって行なってもよい。Next, an upper layer metal wiring 5 of Al or the like is formed, and an upper layer metal wiring 5 is formed by patterning again using the photolithography technique. For example, if the contact holes 6 are also filled with Al by using Al sputtering, the upper and lower metal wirings are connected. The contact holes may be filled with poly-Si or a refractory metal in advance.
【００３５】図１は、簡単のために２層配線の例を示し
たが、３層、４層配線の場合は同様の工程を繰り返して
行なえばよい。金属配線の材料は、加熱処理等との関係
で適当に選択すればよい。Although FIG. 1 shows an example of two-layer wiring for simplification, the same process may be repeated in the case of three-layer and four-layer wiring. The material of the metal wiring may be appropriately selected in consideration of heat treatment or the like.
【００３６】上述の実施例では、第１の層間絶縁膜３と
してシランの常圧ＣＶＤによって堆積したＰＳＧ膜を用
いたが、他の方法で第１の層間絶縁膜を形成することも
できる。たとえば、テトラエチルオルソシリケートＳｉ
（ＯＣ2 Ｈ5 ）4 （ＴＥＯＳ）の分解反応を利用するこ
とも可能である。Although the PSG film deposited by atmospheric pressure CVD of silane is used as the first interlayer insulating film 3 in the above-mentioned embodiment, the first interlayer insulating film can be formed by another method. For example, tetraethyl orthosilicate Si
It is also possible to utilize the decomposition reaction of (OC 2 H 5 ) 4 (TEOS).
【００３７】下層金属配線した試料をＣＶＤ装置内に導
入し、試料温度を約４００℃程度としてＴＥＯＳを流入
させると、 Ｓｉ（ＯＣ2 Ｈ5 ）4 →ＳｉＯ2 ＋気体生成物 の形で熱分解反応が起き、ＳｉＯ2 膜が堆積する。この
時ＰＨ3 も同時に導入すれば、ＰＳＧ膜が生成する。When the sample with the lower metal wiring is introduced into the CVD apparatus and TEOS is introduced at a sample temperature of about 400 ° C., thermal decomposition takes place in the form of Si (OC 2 H 5 ) 4 → SiO 2 + gas product. A reaction occurs and a SiO 2 film is deposited. At this time, if PH 3 is also introduced at the same time, a PSG film is formed.
【００３８】ＴＥＯＳを用いたＣＶＤは、堆積膜の均一
性に優れており、また熱分解反応のため、ステップカバ
レージに優れている。さらに、凹部を埋めるリフロー作
用と類似の効果があり、平坦性はシランを用いた常圧Ｃ
ＶＤ法のＳｉＯ2 系膜より優れている。なお、この結
果、生じたＳｉＯ2 （ＰＳＧ）膜も引張り応力性を有し
ている。The CVD using TEOS is excellent in the uniformity of the deposited film and is excellent in the step coverage because of the thermal decomposition reaction. Further, it has an effect similar to the reflow action of filling the recess, and the flatness is normal pressure C using silane.
It is superior to the VD method SiO 2 film. The resulting SiO 2 (PSG) film also has tensile stress properties.
【００３９】なお、第１の層間絶縁膜３に圧縮応力性Ｓ
ｉＯ2 膜を用いて、研磨後、引張り応力性のＳｉＯ2 膜
からなる第２の層間絶縁膜４を堆積させても、応力歪相
殺は可能で、経時変化によるクラックの発生防止には効
果がある。しかし、Ｓｉ基板上に堆積させた圧縮応力性
ＳｉＯ2 膜を前記実施例のようにして研磨すると、Ｓｉ
Ｏ2 膜にクラックが生じることがある。The compressive stress property S is applied to the first interlayer insulating film 3.
Even if the second interlayer insulating film 4 made of a tensile stressed SiO 2 film is deposited after polishing using the iO 2 film, the stress strain can be canceled out, and it is effective in preventing the generation of cracks due to aging. is there. However, when the compressive stress SiO 2 film deposited on the Si substrate is polished as in the above embodiment, Si
A crack may occur in the O 2 film.
【００４０】前記実施例では、第１の層間絶縁膜３が引
張り応力性ＳｉＯ2 系膜からなる。この膜に研磨工程で
クラックが入る危険性は少ない。この上に圧縮応力性Ｓ
ｉＯ 2 系膜を形成することにより、クラックを生じる危
険性少なく、応力の相殺が行なえる。In the above-mentioned embodiment, the first interlayer insulating film 3 is not drawn.
Tensile stress SiO2It consists of a system membrane. In this film polishing process
There is little risk of cracking. Compressive stress S
iO 2By forming a system film, there is a risk of cracking.
It is less rugged and can cancel the stress.
【００４１】引張り応力性ＳｉＯ2 系膜と圧縮応力性Ｓ
ｉＯ2 系膜としては、図３に示すようなものを用いるこ
とができる。以上実施例に沿って本発明を説明したが、
本発明はこれらに制限されるものではない。たとえば、
種々の変更、改良、組み合わせ等が可能なことは当業者
に自明であろう。Tensile stress SiO 2 film and compressive stress S
As the iO 2 -based film, a film as shown in FIG. 3 can be used. The present invention has been described above with reference to the embodiments,
The present invention is not limited to these. For example,
It will be apparent to those skilled in the art that various changes, improvements, combinations and the like can be made.
【００４２】[0042]
【発明の効果】以上説明したように、本発明によれば、
多層配線における平坦性が改善される。上層配線のステ
ップカバレージ特性が向上する。また、層間絶縁膜に内
蔵される応力歪が相殺して経時劣化を低減することがで
きる。As described above, according to the present invention,
The flatness in the multilayer wiring is improved. The step coverage characteristic of the upper layer wiring is improved. In addition, the stress strains built in the interlayer insulating film can be offset to reduce deterioration over time.
【００４３】この結果、高集積化半導体装置の信頼性向
上に資することができると考えられる。As a result, it is considered that the reliability of the highly integrated semiconductor device can be improved.
【図面の簡単な説明】[Brief description of drawings]
【図１】実施例による２層配線工程の主要部を示す断面
図である。FIG. 1 is a sectional view showing a main part of a two-layer wiring process according to an example.
【図２】従来例による２層配線工程の主要部を示す断面
図である。FIG. 2 is a sectional view showing a main part of a two-layer wiring process according to a conventional example.
【図３】各種ガラス膜の室温における応力を示すグラフ
である。FIG. 3 is a graph showing stress at room temperature of various glass films.
１、１１ 半導体基板 ２、１２ 下層金属配線 ３ 第１の層間絶縁膜 ４ 第２の層間絶縁膜 ５、１４ 上層金属配線 ６、１７ コンタクトホール ８、１８ 熱酸化膜 ９、１９ 絶縁膜 １３ 層間絶縁膜 1, 11 Semiconductor substrate 2, 12 Lower layer metal wiring 3 First interlayer insulating film 4 Second interlayer insulating film 5, 14 Upper layer metal wiring 6, 17 Contact hole 8, 18 Thermal oxide film 9, 19 Insulating film 13 Interlayer insulation film
Claims (3)
と、 前記半導体基板（１）上に形成された下層金属配線
（２）と、 該下層金属配線（２）を被覆し、研磨されてできる平坦
化した表面を有する引張り応力性ＳｉＯ2 系の第１の層
間絶縁膜（３）と、 該第１の層間絶縁膜（３）を被覆する圧縮応力性ＳｉＯ
2 系の第２の層間絶縁膜（４）と、 該第２の層間絶縁膜（４）上に形成された上層金属配線
（５）とを有する半導体装置。1. A semiconductor substrate (1) on which a circuit element is formed.
A lower-layer metal wiring (2) formed on the semiconductor substrate (1), and a tensile-stressing SiO 2 -based first metal wiring (2) having a flattened surface formed by polishing and polishing the lower-layer metal wiring (2). First interlayer insulating film (3) and compressive stress SiO that covers the first interlayer insulating film (3)
A semiconductor device having a 2- system second interlayer insulating film (4) and an upper layer metal wiring (5) formed on the second interlayer insulating film (4).
前記第１の層間絶縁膜と第２の層間絶縁膜と同様の第３
の層間絶縁膜と第４の層間絶縁膜とを有する請求項１記
載の半導体装置。2. Further, on the upper metal wiring (5),
The same third interlayer insulating film as the first interlayer insulating film and the second interlayer insulating film
2. The semiconductor device according to claim 1, further comprising: the interlayer insulating film and the fourth interlayer insulating film.
に、下層金属配線（２）を形成する工程と、 該下層金属配線（２）上に、引張り応力を内蔵するＳｉ
Ｏ2 系膜を堆積する工程と、 前記引張り応力を内蔵するＳｉＯ2 系膜を平坦化研磨し
て平坦化された表面を有する第１の層間絶縁膜（３）と
する工程と、 該第１の層間絶縁膜（３）上に、圧縮応力を内蔵するＳ
ｉＯ2 系膜を堆積して第２の層間絶縁膜（４）を形成す
る工程と、 該第１および第２の層間絶縁膜（３、４）を貫通して前
記下層金属配線（２）に達するコンタクトホール（６）
を設けた後、表面上に上層金属配線（５）を形成する工
程とを含む半導体装置の製造方法。3. A step of forming a lower layer metal wiring (2) on a semiconductor substrate (1) on which a circuit element is formed, and Si having a tensile stress built in on the lower layer metal wiring (2).
A step of depositing an O 2 -based film; a step of flattening and polishing the SiO 2 -based film containing a tensile stress to form a first interlayer insulating film (3) having a flattened surface; S containing a compressive stress on the interlayer insulating film (3) of
a step of depositing an iO 2 -based film to form a second interlayer insulating film (4); and a step of penetrating the first and second interlayer insulating films (3, 4) to form the lower metal wiring (2). Contact hole reached (6)
And a step of forming an upper layer metal wiring (5) on the surface thereof after the formation of the semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33918092A JPH06188242A (en) | 1992-12-18 | 1992-12-18 | Semiconductor device and its manufacture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33918092A JPH06188242A (en) | 1992-12-18 | 1992-12-18 | Semiconductor device and its manufacture |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06188242A true JPH06188242A (en) | 1994-07-08 |
Family
ID=18324999
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33918092A Withdrawn JPH06188242A (en) | 1992-12-18 | 1992-12-18 | Semiconductor device and its manufacture |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06188242A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5912185A (en) * | 1995-12-30 | 1999-06-15 | Samsung Electronics Co., Ltd. | Methods for forming contact holes having improved sidewall profiles |
| US6004729A (en) * | 1996-11-02 | 1999-12-21 | Samsung Electronics Co., Ltd. | Methods of improving photoresist adhesion for integrated circuit fabrication |
-
1992
- 1992-12-18 JP JP33918092A patent/JPH06188242A/en not_active Withdrawn
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5912185A (en) * | 1995-12-30 | 1999-06-15 | Samsung Electronics Co., Ltd. | Methods for forming contact holes having improved sidewall profiles |
| US6004729A (en) * | 1996-11-02 | 1999-12-21 | Samsung Electronics Co., Ltd. | Methods of improving photoresist adhesion for integrated circuit fabrication |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2820187B2 (en) | Method for manufacturing semiconductor device | |
| JPH11307633A (en) | Semiconductor device having film of low permittivity and manufacture thereof | |
| JP2600600B2 (en) | Abrasive, method for manufacturing the same, and method for manufacturing semiconductor device using the same | |
| JPH1022473A (en) | Manufacture of semiconductor device | |
| JPH11204645A (en) | Interlayer insulating film of semiconductor device and manufacture thereof | |
| JPH11312679A (en) | Manufacture of wide and flattened semiconductor device | |
| JPH09116009A (en) | Forming method for connecting hole | |
| KR960001339B1 (en) | Semiconductor memory device and the manufacturing | |
| US5963837A (en) | Method of planarizing the semiconductor structure | |
| JPH06188242A (en) | Semiconductor device and its manufacture | |
| US6054360A (en) | Method of manufacturing a semiconductor memory device with a stacked capacitor wherein an electrode of the capacitor is shaped using a high melting point metal film | |
| JP3127983B2 (en) | Method for manufacturing semiconductor device | |
| JPH09167765A (en) | Insulation layer and method of forming it | |
| JPH07273182A (en) | Fabrication of semiconductor device | |
| JPH1187511A (en) | Method of forming contact plug of semiconductor device and planarization of insulation film | |
| JP3203720B2 (en) | Method of forming trench | |
| JPH10340952A (en) | Method for forming multilayer wiring in integrated circuit | |
| KR20060058583A (en) | Conductive structure, method of manufacturing the conductive structure, semiconductor device including the conductive structure and method of manufacturing the semiconductor device | |
| KR100224788B1 (en) | Process for fabricating semicondcutor device | |
| US6054397A (en) | BPSG planarization method having improved planarity and reduced chatter mark defects | |
| JP2003273237A (en) | Method of manufacturing semiconductor device | |
| JP2611744B2 (en) | Method for manufacturing semiconductor device | |
| JP3287326B2 (en) | Method for manufacturing semiconductor device | |
| US6472313B2 (en) | Device formation method for preventing pattern shift caused by glass layer reflow | |
| JPH0684902A (en) | Method of flattening insulation film |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000307 |