JPH06180460A - Substrate structure for connecting semiconductor chip - Google Patents
Substrate structure for connecting semiconductor chipInfo
- Publication number
- JPH06180460A JPH06180460A JP43A JP33459492A JPH06180460A JP H06180460 A JPH06180460 A JP H06180460A JP 43 A JP43 A JP 43A JP 33459492 A JP33459492 A JP 33459492A JP H06180460 A JPH06180460 A JP H06180460A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor chip
- electrodes
- terminal
- liquid crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶表示装置などの電
子機器における半導体チップ接続用基板構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip connecting substrate structure in an electronic device such as a liquid crystal display device.
【０００２】[0002]
【従来の技術】パーソナルコンピュータやワードプロセ
ッサなどの表示装置として用いられる液晶表示装置に対
する駆動用ＬＳＩ（大規模集積回路）チップの接続法に
は、異方性導電膜（ＡＣＦ）を介してガラス基板上の端
子電極と駆動用ＬＳＩを実装したＴＡＢの出力端子部と
を接続する方法が一般的に用いられている。この接続法
はＡＣＦ中に含まれる粒子の凝集やＴＡＢの銅箔のパタ
ーン精度から接続ピッチに限界がある事、また、ＴＡＢ
やＡＣＦなどの部品コストがかかるという課題を有して
いる。2. Description of the Related Art A driving LSI (Large Scale Integrated Circuit) chip is connected to a liquid crystal display device used as a display device such as a personal computer or a word processor by using an anisotropic conductive film (ACF) on a glass substrate. The method of connecting the terminal electrode of (4) and the output terminal portion of the TAB on which the driving LSI is mounted is generally used. This connection method has a limit in the connection pitch due to the agglomeration of particles contained in the ACF and the pattern accuracy of the TAB copper foil.
There is a problem that the cost of parts such as ACF and ACF is high.
【０００３】そこで、接続の微細化及び低コスト化に対
応する技術として、液晶表示装置用のガラス基板の端子
電極と駆動用ＬＳＩを直接接続させるＣＯＧ方式が用い
られている。このＣＯＧ方式では、（１）駆動用ＬＳＩ
側に接続信頼性を上げるためのバンプを形成する場合
と、逆に（２）このバンプをガラス基板の端子電極上に
バンプ形成する場合と、（３）駆動用ＬＳＩとガラス基
板の端子電極上の両側にバンプ形成する場合がある。こ
の３方式の中で駆動用ＬＳＩにバンプ形成する（１），
（３）の方式は、ＬＳＩのコストを上げてしまう事から
液晶表示装置のガラス基板の端子電極上にバンプが形成
できる事が望ましい。このガラス基板の端子電極上にバ
ンプを形成する場合、従来は液晶表示装置組立後、金属
コートしたプラスチックボールを樹脂中に混合して印刷
法やフォト法により、端子電極上に選択的に形成する方
法が用いられていた。Therefore, as a technique for coping with finer connection and lower cost, a COG method is used in which a terminal electrode of a glass substrate for a liquid crystal display device and a driving LSI are directly connected. In this COG method, (1) driving LSI
On the other hand, in the case of forming a bump for improving the connection reliability, (2) when forming the bump on the terminal electrode of the glass substrate, and (3) on the driving LSI and the terminal electrode of the glass substrate. Bumps may be formed on both sides. Among these three methods, bumps are formed on the driving LSI (1),
Since the method (3) increases the cost of the LSI, it is desirable that bumps can be formed on the terminal electrodes of the glass substrate of the liquid crystal display device. When forming bumps on the terminal electrodes of this glass substrate, conventionally, after assembling the liquid crystal display device, metal-coated plastic balls are mixed with resin and selectively formed on the terminal electrodes by a printing method or a photo method. The method was used.
【０００４】[0004]
【発明が解決しようとする課題】液晶表示装置における
ガラス基板の端子電極上へのバンプ形成に対し、従来用
いられていた金属コートしたプラスチックボールを樹脂
中に混入した構造は接続する端子電極と金属コートプラ
スチックボール及び駆動用ＬＳＩチップ端子部と金属コ
ートプラスチックボールとの間にバインダーとして使用
する樹脂が入り込むため、導通の信頼性が取れないとい
う欠点を有していた。In contrast to the bump formation on the terminal electrode of the glass substrate in the liquid crystal display device, the structure in which the metal-coated plastic ball is mixed in the resin, which has been conventionally used, is connected to the terminal electrode to be connected to the metal. Since the resin used as the binder enters between the coated plastic balls and the driving LSI chip terminal portion and the metal coated plastic balls, there is a drawback that the reliability of conduction cannot be obtained.
【０００５】そこで、本発明は上記欠点を解決するため
に、基板上に端子電極が形成されるべき場所に予めバン
プ形状を形成し、その上に配線パターン電極形成と同時
に端子電極を形成する事により、端子電極とバンプを兼
ねる構造をとる事を特徴とし、その目的は基板の端子電
極と駆動用ＬＳＩの端子部をダイレクトにコンタクトさ
せる事により接続の信頼性を高める事である。Therefore, in order to solve the above-mentioned drawbacks, the present invention forms a bump shape in advance on a substrate at a place where a terminal electrode is to be formed, and forms a wiring pattern electrode and a terminal electrode at the same time. Therefore, a structure which doubles as a terminal electrode and a bump is adopted, and the purpose thereof is to improve the reliability of the connection by directly contacting the terminal electrode of the substrate and the terminal portion of the driving LSI.
【０００６】[0006]
【課題を解決するための手段】本発明の半導体チップ接
続用基板構造は、複数の電極より構成される半導体チッ
プの端子部を、基板表面に形成された端子電極上にフェ
イスダウンによってダイレクトボンディングする半導体
チップ接続用基板構造において、半導体との接続部の基
板上に予め突起部を形成した上に配線パターン電極と端
子電極を一括形成することにより、基板表面の端子電極
上にバンプを形成した事を特徴とする。According to the semiconductor chip connecting substrate structure of the present invention, the terminal portion of the semiconductor chip composed of a plurality of electrodes is directly bonded face down on the terminal electrode formed on the substrate surface. In the substrate structure for semiconductor chip connection, bumps are formed on the terminal electrodes on the surface of the substrate by collectively forming the wiring pattern electrodes and the terminal electrodes on the protrusions previously formed on the substrate at the connection portion with the semiconductor. Is characterized by.
【０００７】[0007]
〔実施例１〕以下本発明の一実施例を図１から図４を用
いて説明する。図１（ａ）のガラス基板１０１上に、ネ
ガ型感光性レジスト１０２を塗布し、次に図１（ｂ）の
ようにフォトマスク１０３を用い、所定の場所にのみ紫
外光を照射させる事により、図１（ｃ）の１０５のよう
に現像工程経過後所定の場所にバンプを形成する。さら
に図１（ｄ）のようにその基板表面に透明導電膜１０６
を形成し、その透明導電膜をレジスト塗布、パターン露
光、現像、透明導電膜エッチング、レジスト剥離の一連
の工程よりなるフォトプロセスにより、パターン部と同
時に端子部にも電極を形成する。この様にして、図１
（ｅ）に示すように基板上の端子電極部にバンプ１０５
が形成される。図２（ａ）は、図１において形成された
バンプ１０５により駆動用ＬＳＩ２０１をＡｌのパッド
部２０２を介して基板１０１上に実装した際の断面図で
あり、半導体チップは紫外線硬化樹脂２０３により基板
に固定されている。図２（ｂ）は上記構造の平面図であ
り、バンプ１０５がＡｌパッド２０２と接続している様
子を表している。さらに、図３（ａ）は実際の液晶表示
装置上での実装構造を表しており、駆動用ＬＳＩの出力
側の接続（２０２と１０５）の他に入力側（３０２，３
０１）にも同様な構造をとり、透明導電膜１０６と同じ
ように端子電極３０３を形成し、ＦＰＣ（フレキシブル
プリント基板）３０４への接続にＡＣＦ（異方性導電
膜）３０５を用いた構造を示している。また、図３
（ｂ）はその接続の平面図を示している。[Embodiment 1] An embodiment of the present invention will be described below with reference to FIGS. By coating a negative type photosensitive resist 102 on the glass substrate 101 of FIG. 1A, and then using a photomask 103 as shown in FIG. As shown by 105 in FIG. 1C, bumps are formed at predetermined places after the development process. Further, as shown in FIG. 1D, the transparent conductive film 106 is formed on the surface of the substrate.
Then, an electrode is formed not only on the pattern part but also on the terminal part by a photo process including a series of steps of resist coating, pattern exposure, development, transparent conductive film etching, and resist stripping of the transparent conductive film. In this way, FIG.
As shown in (e), the bump 105 is formed on the terminal electrode portion on the substrate.
Is formed. FIG. 2A is a cross-sectional view when the driving LSI 201 is mounted on the substrate 101 via the Al pad portion 202 by the bump 105 formed in FIG. It is fixed to. FIG. 2B is a plan view of the above structure, showing that the bump 105 is connected to the Al pad 202. Further, FIG. 3A shows an actual mounting structure on the liquid crystal display device, and includes the input side (302, 3) in addition to the output side connection (202 and 105) of the driving LSI.
01), the same structure is used, the terminal electrode 303 is formed in the same manner as the transparent conductive film 106, and the ACF (anisotropic conductive film) 305 is used for connection to the FPC (flexible printed circuit board) 304. Shows. Also, FIG.
(B) shows a plan view of the connection.
【０００８】図４は、バンプ形成に用いるネガ型感光性
レジストがカラーフィルター層４０１の平坦化膜４０２
と兼ね、平坦化膜の上に形成される透明電極４０３とバ
ンプ１０５上に形成された透明導電膜１０６が兼ねられ
た構造を示すものであり、液晶表示装置のカラーフィル
ター形成と端子電極のバンプ形成が一括して形成された
構造を示している。この時、バンプ１０５の形成はカラ
ーフィルター層４０１の形成の際に同時に作られる事
も、また、カラーフィルター層４０１と平坦化層４０２
の両方の膜を形成する事もできる。図５は、液晶表示装
置の配線パターン電極の低抵抗化に用いられるＡｌやＡ
ｕ等の金属補助配線部５０１をバンプ形成用電極とし引
き廻した場合の構造であり、表示用電極部５０２と導通
接続部５０３を通じて電気的に接続されている。この場
合、ＦＰＣからＬＳＩの入力端子までの配線抵抗は透明
電極に用いられるＩＴＯ（インジウム・スズ酸化物）に
比べ、一桁以上の低抵抗化が計れ、図３（ａ）３０３の
ような入力部引き廻しに対し抵抗面での自由度を持たせ
る事ができる。In FIG. 4, a negative type photosensitive resist used for bump formation is a flattening film 402 of a color filter layer 401.
It also shows a structure in which the transparent electrode 403 formed on the flattening film and the transparent conductive film 106 formed on the bump 105 also serve as the color filter formation of the liquid crystal display device and the bump of the terminal electrode. It shows a structure in which formation is collectively performed. At this time, the bumps 105 may be formed simultaneously with the formation of the color filter layer 401, and the color filter layer 401 and the planarization layer 402 may be formed.
It is also possible to form both films. FIG. 5 shows Al and A used for lowering the resistance of the wiring pattern electrode of the liquid crystal display device.
This is a structure in which a metal auxiliary wiring portion 501 such as u is laid around as a bump forming electrode, and is electrically connected to the display electrode portion 502 and the conduction connecting portion 503. In this case, the wiring resistance from the FPC to the input terminal of the LSI is lower than that of ITO (indium tin oxide) used for the transparent electrode by one digit or more, and the input as shown in FIG. It is possible to give a degree of freedom in terms of resistance to drawing around.
【０００９】バンプ１０５の材質はアクリル系ネガ型感
光性レジストか、アクリル・エポキシ系ネガ型感光性レ
ジストを用いたが、エポキシ，ポリイミド，ポリアミ
ド，ポリウレタンやそれらの混合物でも同様な効果が期
待できる。図２のバンプ１０５の高さに関しては、液晶
表示装置に応用する場合、後工程での基板の貼り合わせ
の際の液晶層厚の均一性を確保するために１０μｍ以下
が望ましく、また、Ａｌパッド部２０２との接続安定性
から０．１μｍ以上が望ましい。さらに、図４，図５の
ように平坦化膜やカラーフィルターとバンプ１０５を一
括形成する場合は、カラーフィルターの膜厚や平坦化膜
の膜厚ないしは、それを加えた層厚より薄い膜厚が望ま
しい。As the material of the bump 105, an acrylic negative photosensitive resist or an acrylic / epoxy negative photosensitive resist was used, but similar effects can be expected with epoxy, polyimide, polyamide, polyurethane or a mixture thereof. Regarding the height of the bump 105 of FIG. 2, when applied to a liquid crystal display device, it is desirable that the height is 10 μm or less in order to ensure the uniformity of the liquid crystal layer thickness at the time of bonding substrates in a later step. 0.1 μm or more is desirable from the viewpoint of connection stability with the portion 202. Further, in the case where the flattening film or the color filter and the bump 105 are collectively formed as shown in FIGS. 4 and 5, the thickness of the color filter, the thickness of the flattening film, or the film thickness smaller than the layer thickness including the flattening film Is desirable.
【００１０】[0010]
【発明の効果】以上述べたように、基板表面上にバンプ
を形成し直接ＬＳＩの端子部とコンタクトした事によ
り、信頼性の高い半導体チップ接続用基板構造が得られ
た。As described above, by forming the bumps on the surface of the substrate and directly contacting the terminals of the LSI, a highly reliable semiconductor chip connecting substrate structure can be obtained.
【図１】本発明におけるバンプ形成法の説明図。FIG. 1 is an explanatory view of a bump forming method according to the present invention.
【図２】本発明におけるバンプとＬＳＩとの接続の様子
を示す図。FIG. 2 is a diagram showing how bumps and LSIs are connected in the present invention.
【図３】本発明を利用した液晶表示装置の実装例を示す
図。FIG. 3 is a diagram showing a mounting example of a liquid crystal display device using the present invention.
【図４】本発明を利用したカラーフィルター基板の断面
図。FIG. 4 is a sectional view of a color filter substrate using the present invention.
【図５】本発明を利用した金属補助配線付き基板の断面
図。FIG. 5 is a sectional view of a substrate with metal auxiliary wiring using the present invention.
１０１． ガラス基板 １０５． バンプ １０６． 透明導電膜 ２０１． 駆動用ＬＳＩ ２０２． パッド部 ２０３． 紫外線硬化樹脂 101. Glass substrate 105. Bump 106. Transparent conductive film 201. Drive LSI 202. Pad portion 203. UV curable resin
Claims (3)
端子部を、基板表面に形成された端子電極上にフェイス
ダウンによってダイレクトボンディングする半導体チッ
プ接続用基板構造において、半導体との接続部の基板上
に予め突起部を形成した上に配線パターン電極と端子電
極を一括形成することにより、基板表面の端子電極上に
バンプを形成した事を特徴とする半導体チップ接続用基
板構造。1. A semiconductor chip connecting substrate structure in which a terminal portion of a semiconductor chip composed of a plurality of electrodes is directly face-down bonded onto a terminal electrode formed on a surface of the substrate. A substrate structure for connecting a semiconductor chip, characterized in that bumps are formed on the terminal electrodes on the surface of the substrate by collectively forming wiring pattern electrodes and terminal electrodes on previously formed protrusions.
ると同時に前記突起部が所定の位置に選択的に形成され
た事を特徴とする請求項１記載の半導体チップ接続用基
板構造。2. The substrate structure for connecting a semiconductor chip according to claim 1, wherein an organic film or an inorganic film is formed on the substrate, and at the same time, the protrusions are selectively formed at predetermined positions.
基板であり、かつ、基板上の突起部の高さｄが、０．１
μｍ＜ｄ＜１０μｍの範囲である事を特徴とする請求項
１記載の半導体チップ接続用基板構造。3. The substrate is a transparent substrate used in a liquid crystal display device, and the height d of the protrusions on the substrate is 0.1.
2. The semiconductor chip connecting substrate structure according to claim 1, wherein the range is μm <d <10 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06180460A (en) | 1992-12-15 | 1992-12-15 | Substrate structure for connecting semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP43A JPH06180460A (en) | 1992-12-15 | 1992-12-15 | Substrate structure for connecting semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06180460A true JPH06180460A (en) | 1994-06-28 |
Family
ID=18279143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP43A Pending JPH06180460A (en) | 1992-12-15 | 1992-12-15 | Substrate structure for connecting semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06180460A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787924B2 (en) * | 2001-02-13 | 2004-09-07 | Nec Corporation | Semiconductor device capable of preventing solder balls from being removed in reinforcing pad |
| EP1577699A2 (en) | 2004-03-17 | 2005-09-21 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| EP1662300A1 (en) | 2004-11-24 | 2006-05-31 | Sanyo Electric Co., Ltd | Active matrix display device and method for manufacturing the same |
| US7599038B2 (en) | 2005-04-28 | 2009-10-06 | Epson Imaging Devices Corp. | Display apparatus and manufacturing method of display apparatus |
| US7639338B2 (en) | 2004-05-11 | 2009-12-29 | Nec Lcd Technologies, Ltd. | LCD device having external terminals |
| US8975905B2 (en) | 2012-04-10 | 2015-03-10 | Samsung Display Co., Ltd. | Display apparatus with reduced number of test lines for array test process and method of testing the same |
-
1992
- 1992-12-15 JP JP43A patent/JPH06180460A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6787924B2 (en) * | 2001-02-13 | 2004-09-07 | Nec Corporation | Semiconductor device capable of preventing solder balls from being removed in reinforcing pad |
| EP1577699A2 (en) | 2004-03-17 | 2005-09-21 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| EP1577699A3 (en) * | 2004-03-17 | 2006-04-26 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| KR100699641B1 (en) * | 2004-03-17 | 2007-03-23 | 세이코 엡슨 가부시키가이샤 | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| US7482541B2 (en) | 2004-03-17 | 2009-01-27 | Seiko Epson Corporation | Panel for electro-optical apparatus, method of manufacture thereof, electro-optical apparatus and electronic apparatus |
| US7639338B2 (en) | 2004-05-11 | 2009-12-29 | Nec Lcd Technologies, Ltd. | LCD device having external terminals |
| EP1662300A1 (en) | 2004-11-24 | 2006-05-31 | Sanyo Electric Co., Ltd | Active matrix display device and method for manufacturing the same |
| US7599038B2 (en) | 2005-04-28 | 2009-10-06 | Epson Imaging Devices Corp. | Display apparatus and manufacturing method of display apparatus |
| US8975905B2 (en) | 2012-04-10 | 2015-03-10 | Samsung Display Co., Ltd. | Display apparatus with reduced number of test lines for array test process and method of testing the same |
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