JPH06176954A - Laminated grain insulating type semiconductor ceramic capacitor - Google Patents
Laminated grain insulating type semiconductor ceramic capacitorInfo
- Publication number
- JPH06176954A JPH06176954A JP32392492A JP32392492A JPH06176954A JP H06176954 A JPH06176954 A JP H06176954A JP 32392492 A JP32392492 A JP 32392492A JP 32392492 A JP32392492 A JP 32392492A JP H06176954 A JPH06176954 A JP H06176954A
- Authority
- JP
- Japan
- Prior art keywords
- ceramic capacitor
- external electrode
- internal electrode
- varistor
- laminated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 48
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 150000001875 compounds Chemical class 0.000 claims abstract description 10
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 9
- 239000003990 capacitor Substances 0.000 claims description 15
- 239000000919 ceramic Substances 0.000 claims description 8
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 238000009413 insulation Methods 0.000 claims description 4
- 239000007858 starting material Substances 0.000 claims description 4
- 239000002003 electrode paste Substances 0.000 abstract description 17
- 230000005611 electricity Effects 0.000 abstract description 16
- 230000003068 static effect Effects 0.000 abstract description 15
- 239000000463 material Substances 0.000 abstract description 9
- 238000002156 mixing Methods 0.000 abstract description 5
- 230000002159 abnormal effect Effects 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 23
- 238000000034 method Methods 0.000 description 11
- 239000000203 mixture Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000010304 firing Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910002367 SrTiO Inorganic materials 0.000 description 5
- 239000000843 powder Substances 0.000 description 5
- 229910010413 TiO 2 Inorganic materials 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 3
- 238000001354 calcination Methods 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007772 electrode material Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 230000001590 oxidative effect Effects 0.000 description 3
- 239000011230 binding agent Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000003638 chemical reducing agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002037 poly(vinyl butyral) polymer Polymers 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 230000004043 responsiveness Effects 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 239000006104 solid solution Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/30—Stacked capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/018—Dielectrics
- H01G4/06—Solid dielectrics
- H01G4/08—Inorganic dielectrics
- H01G4/12—Ceramic dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、通常はコンデンサとし
て電圧の低いノイズや高周波のノイズを吸収する働きを
し、一方パルスや静電気などの高い電圧が侵入した時は
バリスタ機能を発揮することによって、異常電圧から半
導体素子及び電子機器を保護する目的で使用される積層
型粒界絶縁型半導体セラミックコンデンサに関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention normally serves as a capacitor for absorbing low-voltage noise and high-frequency noise, while exhibiting a varistor function when high voltage such as pulse or static electricity enters. The present invention relates to a laminated type grain boundary insulation type semiconductor ceramic capacitor used for the purpose of protecting a semiconductor element and an electronic device from an abnormal voltage.
【０００２】[0002]
【従来の技術】近年、電子機器は多機能、軽薄短小化を
実現するためにＩＣ，ＬＳＩなどの半導体素子が広く用
いられ、それに伴って機器のノイズ耐力は低下しつつあ
る。そこで、このような電子機器のノイズ耐力を確保す
るために、各種ＩＣ，ＬＳＩの電源ラインに、バイパス
コンデンサとしてフィルムコンデンサ、積層セラミック
コンデンサ、半導体セラミックコンデンサなどが使用さ
れている。しかし、これらのコンデンサは、電圧の低い
ノイズや高周波のノイズの吸収に対しては優れた性能を
示すが、これらのコンデンサ自体に高い電圧を持つパル
スや同じく高い電圧を持つ静電気を吸収する機能を持た
ないため、高い電圧を持つパルスや静電気が侵入する
と、機器の誤動作や半導体素子の破壊、さらにはコンデ
ンサの破壊を起こすことが大きな問題となっている。2. Description of the Related Art In recent years, semiconductor devices such as ICs and LSIs have been widely used in electronic equipment in order to realize multi-functionality, lightness, thinness, shortness and size reduction, and the noise resistance of the equipment is decreasing accordingly. Therefore, in order to ensure the noise resistance of such electronic devices, film capacitors, laminated ceramic capacitors, semiconductor ceramic capacitors, etc. are used as bypass capacitors in the power supply lines of various ICs and LSIs. However, although these capacitors have excellent performance in absorbing low-voltage noise and high-frequency noise, these capacitors themselves have the function of absorbing high-voltage pulses and static electricity with the same high voltage. Since it does not have it, when a pulse or static electricity having a high voltage enters, malfunctions of devices, destruction of semiconductor elements, and even destruction of capacitors have become serious problems.
【０００３】そこでこのような用途に、ノイズ吸収性が
良好で温度や周波数に対しても安定していることに加え
て、高いパルス耐力と優れたパルス吸収性を持つ新しい
タイプのコンデンサとして、ＳｒＴｉＯ3系半導体セラ
ミックコンデンサにバリスタ機能を持たせた粒界絶縁型
半導体セラミックコンデンサ（以下、バリスタ機能付セ
ラミックコンデンサという）が開発され、すでに特開昭
５７−２７００１号公報、特開昭５７−３５３０３号公
報などにより公知となっている。For this purpose, SrTiO 3 is used as a new type capacitor having high pulse resistance and excellent pulse absorption in addition to good noise absorption and stable temperature and frequency. A grain boundary insulation type semiconductor ceramic capacitor (hereinafter referred to as a ceramic capacitor with a varistor function) in which a 3- system semiconductor ceramic capacitor has a varistor function has been developed, and it has already been disclosed in JP-A-57-27001 and 57-35303. It is publicly known from the publications.
【０００４】このバリスタ機能付セラミックコンデンサ
は、通常はコンデンサとして電圧の低いノイズや高周波
のノイズを吸収するが、パルスや静電気などの高い電圧
が侵入した時はバリスタとして機能し、異常電圧から半
導体素子及び電子機器を保護するという特徴を有してお
り、その使用はますます拡大されている。The ceramic capacitor with a varistor function normally absorbs low-voltage noise and high-frequency noise as a capacitor, but when a high voltage such as pulse or static electricity enters, it functions as a varistor and the semiconductor element is protected from abnormal voltage. It also has the feature of protecting electronic devices, and its use is expanding more and more.
【０００５】一方、電子部品分野においては、軽薄短小
化、高性能化がますます進み、このバリスタ機能付セラ
ミックコンデンサに至っても、小型化、高性能の要請が
強まっている。しかし、従来のバリスタ機能付セラミッ
クコンデンサは単板型であるため、小型化すると電極面
積が小さくなり、その結果として容量が低下したり、信
頼性が低下するという問題を招くことになる。従って、
その解決策として、電極面積を実質的に大きくすること
ができる積層化への展開が予想される。On the other hand, in the field of electronic parts, lightness, thinness, shortness, miniaturization and high performance have been further advanced, and even with this ceramic capacitor with a varistor function, there is an increasing demand for miniaturization and high performance. However, since the conventional varistor function-equipped ceramic capacitor is a single plate type, miniaturization causes a reduction in the electrode area, resulting in problems such as a decrease in capacitance and a decrease in reliability. Therefore,
As a solution to this, it is expected to develop into a laminated structure that can substantially increase the electrode area.
【０００６】しかし、バリスタ機能付セラミックコンデ
ンサは、通常、ＳｒＴｉＯ3系半導体素子の表面に酸化
物を塗布し、熱拡散により粒界層を絶縁化する工程を有
するため、一般に用いられているＢａＴｉＯ3系積層セ
ラミックコンデンサと比べ、バリスタ機能付セラミック
コンデンサ材料を内部電極材料と同時に焼成して積層型
のバリスタ機能付コンデンサ（以下、バリスタ機能付積
層セラミックコンデンサという）を形成することは非常
に困難であると考えられていた。However, a ceramic capacitor with a varistor function usually has a step of coating an oxide on the surface of a SrTiO 3 type semiconductor element and insulating the grain boundary layer by thermal diffusion, so that it is generally used BaTiO 3 type. It is very difficult to form a multilayer varistor function capacitor (hereinafter referred to as varistor function multilayer ceramic capacitor) by firing the varistor function ceramic capacitor material at the same time as the internal electrode material, as compared with the system type multilayer ceramic capacitor. Was considered.
【０００７】そこで、バリスタ機能付積層セラミックコ
ンデンサ材料と内部電極材料との同時焼成の課題を解決
する手法として、特開昭５４−５３２４８号公報、特開
昭５４−５３２５０号公報などを応用し、内部電極に当
たる部分に有機バインダー量を多くしたセラミックペー
ストを印刷し、この部分に焼結過程で多孔層を形成し、
焼結した後にその多孔層に適当な圧力下で導電性金属を
注入させる方法、またはメッキ法や溶融法によって内部
電極を形成し、バリスタ機能付積層セラミックコンデン
サを形成させる方法が開発、提供されている。しかし、
これらはプロセス的にかなり困難であり、未だに実用化
へのレベルに達していない。Therefore, as a method for solving the problem of simultaneous firing of a multilayer ceramic capacitor material with a varistor function and an internal electrode material, JP-A-54-53248 and JP-A-54-53250 are applied, A ceramic paste with a large amount of organic binder is printed on the part corresponding to the internal electrode, and a porous layer is formed on this part during the sintering process.
A method for injecting a conductive metal into the porous layer under appropriate pressure after sintering or a method for forming an internal electrode by a plating method or a melting method to form a laminated ceramic capacitor with a varistor function has been developed and provided. There is. But,
These are considerably difficult in terms of process, and have not yet reached the level for practical use.
【０００８】また、特開昭５９−２１５７０１号公報
に、非酸化雰囲気中で仮焼した粉末を原料にした生シー
トの上に粒界層を絶縁化することが可能な熱拡散物質を
混入した導電性ペーストを印刷し、酸化性雰囲気中で焼
結させる方法、さらに特開昭６３−２１９１１５号公報
に、予め半導体化させた粉末を主成分とし、この主成分
に絶縁層を形成させるため酸化剤及び／またはガラス成
分を含む拡散剤を混合した生シートと内部電極を交互に
積層した成型体を、空気中または酸化雰囲気中で焼成す
る方法が報告されている。Further, in Japanese Patent Laid-Open No. 59-215701, a heat diffusion material capable of insulating a grain boundary layer is mixed on a green sheet made of powder calcined in a non-oxidizing atmosphere. A method in which a conductive paste is printed and sintered in an oxidizing atmosphere, and further, Japanese Patent Laid-Open No. 63-219115 discloses that a powder which has been made into a semiconductor is used as a main component, and oxidation is performed to form an insulating layer on this main component. A method has been reported in which a green sheet mixed with a diffusing agent containing a coloring agent and / or a glass component and a molded body in which internal electrodes are alternately laminated are fired in air or in an oxidizing atmosphere.
【０００９】しかし、これら２つの方法では焼成温度が
１０００〜１２００℃と比較的低く、セラミックの焼結
が起こりにくいため、結晶粒子は面接触しにくく、でき
上がった素子は完全な焼結体に至っていないために容量
が低く、かつバリスタとしての代表特性である電圧非直
線指数αが小さく、バリスタ電圧が不安定であり、さら
に信頼性が劣るという問題点を有するものである。さら
にまた、後者の特開昭６３−２１９１１５号公報では、
添加剤としてガラス成分を添加した場合、結晶粒界にガ
ラス相が析出し、上記の電気特性が悪化しやすく、信頼
性が劣るものであり、これもまた実用化へのレベルに達
していないものである。However, in these two methods, the firing temperature is relatively low at 1000 to 1200 ° C., and the ceramic is less likely to sinter. Therefore, the crystal grains are less likely to come into surface contact with each other, and the finished element is a completely sintered body. Therefore, there is a problem that the capacitance is low, the voltage non-linear index α which is a typical characteristic of the varistor is small, the varistor voltage is unstable, and the reliability is poor. Furthermore, in the latter Japanese Patent Laid-Open No. 63-219115,
When a glass component is added as an additive, a glass phase is precipitated in a crystal grain boundary, the above electrical characteristics are likely to be deteriorated, and reliability is poor, and this also does not reach a level for practical use. Is.
【００１０】そこで、本発明者らは特願平１−３６７５
７号公報などに記載したように、Ｔｉ過剰のＳｒＴｉＯ
3に半導体成分とＭｎＯ2−ＳｉＯ2系をベース材料とし
たセラミック組成及びその製造方法において、Ａｕ，Ｐ
ｔ，Ｒｈ，ＰｄまたはＮｉを内部電極とするバリスタ機
能付積層セラミックコンデンサの開発を可能なものとし
た。さらにまた、特願平３−１５２９９１号公報に記載
したように、低原子価のＬｉ，Ｎａ，Ｋ原子の内の少な
くとも一種類以上をＮｉまたはＮｉ原子を含む化合物に
固溶させた内部電極組成及びその製造方法において、Ｎ
ｉを内部電極とするバリスタ機能付積層セラミックコン
デンサの開発をより可能なものとした。Therefore, the present inventors have filed Japanese Patent Application No. 1-3675.
As described in Japanese Patent Publication No. 7, etc., Ti-excess SrTiO 3
The ceramic composition based on the semiconductor component and MnO 2 —SiO 2 system as a base material and its manufacturing method are
It has become possible to develop a monolithic ceramic capacitor with varistor function that uses t, Rh, Pd or Ni as internal electrodes. Furthermore, as described in Japanese Patent Application No. 3-152991, an internal electrode composition in which at least one kind of low-valence Li, Na, and K atoms is solid-dissolved in Ni or a compound containing Ni atoms. And its manufacturing method,
The development of a multilayer ceramic capacitor with a varistor function using i as an internal electrode has become possible.
【００１１】また、積層型バリスタに関しては、既に特
公昭５８−２３９２１号公報により、ＺｎＯ，Ｆｅ
2Ｏ3，ＴｉＯ2系を用いた積層型電圧非直線素子が開示
されている。しかし、この素子は容量をほとんど持たな
いため、比較的高い電圧を持つパルスや静電気の吸収に
対しては優れた性能を示すが、バリスタ電圧以下の低い
電圧を持つノイズや高周波のノイズに対しては、ほとん
ど効果を示さないという課題を有したものであった。Regarding the laminated varistor, ZnO, Fe have already been disclosed in Japanese Patent Publication No. 58-23921.
A laminated voltage non-linear element using 2 O 3 and TiO 2 system is disclosed. However, since this element has almost no capacitance, it exhibits excellent performance with respect to pulses with a relatively high voltage and absorption of static electricity, but with respect to noise with a low voltage below the varistor voltage and high frequency noise. Had a problem that it showed almost no effect.
【００１２】[0012]
【発明が解決しようとする課題】上記Ｔｉ過剰のＳｒＴ
ｉＯ3に半導体成分とＭｎＯ2−ＳｉＯ2系をベース材料
としたセラミック組成及び低原子価のＬｉ，Ｎａ，Ｋ原
子の内の少なくとも一種類以上をＮｉまたはＮｉ原子を
含む化合物に固溶させた内部電極組成、そして製造方法
によりＮｉを内部電極とするバリスタ機能付積層セラミ
ックコンデンサの開発をより可能なものとしたが、外部
電極組成については内部電極組成ほど深く検討されてお
らず、外部電極の劣化によりコンデンサとしての機能と
バリスタとしての機能のどちらか一方が劣化したり、直
列等価抵抗値ＥＳＲが大きくなったりすることがある等
の課題を有したものであった。The above-mentioned Ti-excessive SrT
ceramic composition and a low valence in iO 3 the semiconductor component and MnO 2 -SiO 2 system-based materials Li, Na, or more at least one of the K atoms were solid-dissolved in the compound containing Ni or Ni atoms Although it has become possible to develop a multilayer ceramic capacitor with a varistor function in which Ni is used as the internal electrode depending on the internal electrode composition and the manufacturing method, the external electrode composition has not been studied as deeply as the internal electrode composition. There is a problem that one of the function as a capacitor and the function as a varistor may be deteriorated due to deterioration, or the series equivalent resistance value ESR may be increased.
【００１３】本発明は上記課題を解決し、通常はコンデ
ンサとして電圧の低いノイズや高周波のノイズを吸収す
る働きをし、一方パルスや静電気などの高い電圧が侵入
した時はバリスタ機能を発揮するバリスタ機能付積層セ
ラミックコンデンサに関し、Ｎｉを内部電極とし、しか
もプロセス的にはセラミックコンデンサ材料と内部電極
材料との同時焼成を可能にしたＳｒＴｉＯ3を主成分と
する積層型粒界絶縁型半導体セラミックコンデンサを提
供することを目的とするものである。The present invention solves the above-mentioned problems and normally functions as a capacitor to absorb low-voltage noise and high-frequency noise, while exhibiting a varistor function when high voltage such as pulse or static electricity enters. Regarding a laminated ceramic capacitor with a function, a laminated grain boundary insulation type semiconductor ceramic capacitor containing SrTiO 3 as a main component and having Ni as an internal electrode and capable of simultaneously firing a ceramic capacitor material and an internal electrode material in a process It is intended to be provided.
【００１４】[0014]
【課題を解決するための手段】上記課題を解決するため
に本発明は、内部電極は、低原子価のＬｉ，Ｎａ，Ｋ原
子の内の少なくとも一種類以上をＮｉまたはＮｉ原子を
含む化合物に固溶させた内部電極ペーストを出発原料と
するＮｉ内部電極とし、外部電極は、ＴｉをＮｉまたは
Ｎｉ原子を含む化合物に添加混合させた外部電極ペース
トを出発原料とするＮｉ外部電極としたものである。In order to solve the above problems, the present invention provides an internal electrode in which at least one kind of low valence Li, Na and K atoms is Ni or a compound containing Ni atoms. A solid solution of the internal electrode paste was used as the starting material for the Ni internal electrode, and the external electrode was used as the starting material for the external electrode paste obtained by adding and mixing Ti to Ni or a compound containing Ni atoms. is there.
【００１５】[0015]
【作用】この構成により低原子価のＬｉ，Ｎａ，Ｋ原子
の内の少なくとも一種類以上をＮｉまたはＮｉ原子を含
む化合物に固溶させることによって、Ｎｉ内部電極の耐
酸化性を向上させることが出来ると同時に、セラミック
素子の結晶粒界部分の酸化性を向上させることができ
る。また、外部電極としてＴｉをＮｉまたはＮｉ原子を
含む化合物に添加混合させることによって形成すると、
上記Ｎｉ内部電極と外部電極の接触が良好となり、さら
に酸化速度が低減し、外部電極の酸化を極力抑えること
ができ、バリスタ機能付積層セラミックコンデンサを容
易に提供することが可能となる。With this structure, the oxidation resistance of the Ni internal electrode can be improved by dissolving at least one kind of low-valence Li, Na, and K atoms in Ni or a compound containing the Ni atom. At the same time, the oxidizability of the crystal grain boundary portion of the ceramic element can be improved. Further, when Ti is formed as an external electrode by adding and mixing it to Ni or a compound containing Ni atoms,
The contact between the Ni internal electrode and the external electrode is improved, the oxidation rate is further reduced, the oxidation of the external electrode can be suppressed as much as possible, and the multilayer ceramic capacitor with a varistor function can be easily provided.
【００１６】[0016]
【実施例】以下、本発明による第１の実施例について実
施例を挙げて具体的に説明する。EXAMPLES The first example according to the present invention will be specifically described below with reference to examples.
【００１７】（実施例１）まず、図３，図４に示すよう
に、ＳｒＴｉＯ3（Ｓｒ／Ｔｉ＝０．９７）９７ｍｏｌ
％，Ｎｂ2Ｏ5：０．５ｍｏｌ％，Ｔａ2Ｏ5：０．５ｍｏ
ｌ％，ＭｎＯ2：１．０ｍｏｌ％，ＳｉＯ2：１．０ｍｏ
ｌ％の組成でドクター・ブレード法などによって作製さ
れた３０μｍ程度の厚さの生シートを所定の大きさに切
断し、この切断された生シート１の上にＮｉＯ：９９．
５ｍｏｌ％，Ｌｉ2ＣＯ3：０．５ｍｏｌ％の組成の内部
電極ペースト２を所定の大きさに応じてスクリーン印刷
によりパターン印刷した。なお、図４から明らかなよう
に、無効層となる最上層及び最下層の生シート１ａには
Ｎｉを主成分とする内部電極ペースト２は印刷しないも
のとする。また、この時、中間に積層させる生シート１
の上に印刷されたＮｉを主成分とする内部電極ペースト
２は、周知のように交互に対向する（異なる）端縁に至
るように印刷した。その後、上下に生シート１ａを配
し、（通常それぞれ複数層積層される）、その間に上記
内部電極ペースト２の印刷された生シート１を複数層積
層し、加熱しながら加圧、圧着し、図１のごとく成型体
４を得た。Example 1 First, as shown in FIGS. 3 and 4, SrTiO 3 (Sr / Ti = 0.97) 97 mol
%, Nb 2 O 5 : 0.5 mol%, Ta 2 O 5 : 0.5 mo
1%, MnO 2 : 1.0 mol%, SiO 2 : 1.0mo
A raw sheet having a composition of 1% and having a thickness of about 30 μm produced by a doctor blade method or the like was cut into a predetermined size, and NiO: 99.
The internal electrode paste 2 having a composition of 5 mol% and Li 2 CO 3 : 0.5 mol% was pattern-printed by screen printing according to a predetermined size. As is clear from FIG. 4, the internal electrode paste 2 containing Ni as a main component is not printed on the raw sheets 1a of the uppermost layer and the lowermost layer which are ineffective layers. Also, at this time, the raw sheet 1 to be laminated in the middle
The internal electrode paste 2 containing Ni as a main component printed on the above was printed so as to reach opposite (different) edges alternately as is well known. After that, the green sheets 1a are arranged on the upper and lower sides (normally, a plurality of layers are laminated respectively), while a plurality of layers of the green sheets 1 on which the internal electrode paste 2 is printed are laminated, and pressure and pressure are applied while heating, A molded body 4 was obtained as shown in FIG.
【００１８】次に、平均粒径が０．５μｍ以下で純度９
０％以上のＮｉＯに平均粒径が０．５μｍ以下のＴｉＯ
2粉末を添加した粉末を外部電極用出発原料とし、この
粉末をブチラール樹脂などの有機バインダーと共に溶媒
中に分散させ、外部電極ペーストとした。そして図１に
示すごとく成型体の内部電極ペースト２を交互に異なる
端縁に露出させた成型体４の両端面にこのＮｉを主成分
とする外部電極ペーストを塗布し、空気中で１０５０
℃、２時間空気中で脱脂、仮焼を行った。その後、
Ｎ2：Ｈ2＝９９：１の還元雰囲気中で１２５０℃、２時
間で焼成した。この焼成後、空気中で９００℃で再酸化
し、さらにＮ2：Ｈ2＝９９：１の還元雰囲気中で４００
℃、３０分で外部電極３ａを再還元した。この様にして
形成されたバリスタ機能付積層セラミックコンデンサ
は、図１に示すように複数層の内部電極２ａが、それら
の内部電極２ａが交互に異なる端縁に至るように設けら
れ、かつこれらの内部電極２ａは成型体４の両端縁にお
いてＮｉを主成分とする外部電極３ａに電気的に接続さ
れた状態となっている。Next, when the average particle size is 0.5 μm or less and the purity is 9
TiO with an average particle size of 0.5 μm or less in 0% or more of NiO
The powder to which 2 powders were added was used as a starting material for the external electrode, and this powder was dispersed in a solvent together with an organic binder such as butyral resin to obtain an external electrode paste. Then, as shown in FIG. 1, the external electrode paste containing Ni as a main component is applied to both end surfaces of the molded body 4 in which the internal electrode paste 2 of the molded body is exposed at different edges alternately, and the external electrode paste containing Ni as the main component is applied in air at 1050
Degreasing and calcination were performed in the air at ℃ for 2 hours. afterwards,
Firing was performed at 1250 ° C. for 2 hours in a reducing atmosphere of N 2 : H 2 = 99: 1. After this calcination, reoxidation was performed in air at 900 ° C., and further 400 in a reducing atmosphere of N 2 : H 2 = 99: 1.
The external electrode 3a was re-reduced at 30 ° C. for 30 minutes. As shown in FIG. 1, the multilayer ceramic capacitor with a varistor function thus formed is provided with a plurality of layers of internal electrodes 2a so that the internal electrodes 2a alternately reach different edges, and The internal electrodes 2a are electrically connected to the external electrodes 3a containing Ni as a main component at both end edges of the molded body 4.
【００１９】なお、本実施例でのバリスタ機能付積層セ
ラミックコンデンサの形状は図１における横幅Ｌ×縦幅
Ｗ×高さＨが１．６０×３．２０×１．２０mmの１．３
タイプと呼ばれるもので、内部電極２ａの形成されたセ
ラミックシートを３０層積層したものである。The shape of the multilayer ceramic capacitor with a varistor function in this embodiment is 1.3 (width L × height W × height H of 1.60 × 3.20 × 1.20 mm in FIG. 1).
It is called a type and is formed by laminating 30 layers of ceramic sheets on which the internal electrodes 2a are formed.
【００２０】このようにして得られたバリスタ機能付積
層セラミックコンデンサについて、その容量、ｔａｎ
δ、バリスタ電圧、電圧非直線指数α、直列等価抵抗値
ＥＳＲなどの各種電気特性を、下記の（表１）に記載す
る。なお、各種電気特性については以下の測定値を記載
している。Regarding the multilayer ceramic capacitor with varistor function thus obtained, its capacitance, tan
Various electrical characteristics such as δ, varistor voltage, voltage non-linearity index α, and series equivalent resistance value ESR are shown in the following (Table 1). The following measured values are described for various electrical characteristics.
【００２１】◇容量Ｃは測定電圧１．０Ｖ、周波数１．
０ｋHzでの値。 ◇バリスタ電圧Ｖ0.1mAは測定電流０．１ｍＡでの値。◇ Capacity C is measured voltage 1.0V, frequency 1.
Value at 0 kHz. ◇ The varistor voltage V 0.1mA is the value when the measurement current is 0.1mA.
【００２２】◇電圧非直線指数αは、測定電流０．１ｍ
Ａと１．０ｍＡでの値から、 α＝１／ｌｏｇ（Ｖ1mAＶ0.1mA）の式より算出した。Voltage non-linearity index α is measured current 0.1 m
From the value at A and 1.0 mA, it was calculated from the formula of α = 1 / log (V 1mA V 0.1mA ).
【００２３】◇直列等価抵抗値ＥＳＲは、測定電圧１．
０Ｖでの共振点での抵抗値。The series equivalent resistance value ESR is 1.
The resistance value at the resonance point at 0V.
【００２４】[0024]
【表１】 [Table 1]
【００２５】上記（表１）について解説すると、ここで
資料番号に＊印をつけたものは比較例であり、本発明の
請求範囲外である。即ち、これらの焼結体素子では、外
部電極３ａの酸化が激しく起こり、コンデンサとしての
電圧の低いノイズや高周波のノイズを吸収する機能と、
バリスタとしてのパルス、静電気などの高い電圧を吸収
する機能の両方を同時に持ち合わせていないものや、直
列等価抵抗値ＥＳＲが大きく周波数特性がよくないもの
である。従って、これらの試料は電子機器で発生するノ
イズ、パルス、静電気などから、半導体及び電子機器を
保護するバリスタ機能付セラミックコンデンサとして適
さないものである。Explaining the above (Table 1), the material numbers marked with * are comparative examples, and are outside the scope of the claims of the present invention. That is, in these sintered body elements, the oxidation of the external electrode 3a occurs violently, and the function of absorbing low voltage noise and high frequency noise of the capacitor,
A varistor does not have both a pulse and a function of absorbing high voltage such as static electricity at the same time, and a series equivalent resistance value ESR is large and a frequency characteristic is not good. Therefore, these samples are not suitable as ceramic capacitors with a varistor function for protecting semiconductors and electronic devices from noise, pulses, static electricity, etc. generated in electronic devices.
【００２６】これに対し、その他の試料番号で示す本発
明のものでは、容量が大きく、かつ電圧非直線指数αが
大きく、さらに直列等価抵抗値ＥＳＲが小さいため、コ
ンデンサとしての電圧の低いノイズや高周波のノイズを
吸収する機能と、バリスタとしてのパルス、静電気など
の高い電圧を吸収する機能の両方を同時に持ち合わせて
おり、さらに容量温度変化率とバリスタ電圧温度係数が
小さく、信頼性や電気特性が温度に影響を受けにくい特
徴を有している。従って、これらの試料は電子機器で発
生するノイズ、パルス、静電気などから半導体及び電子
機器を保護するためのバリスタ機能付セラミックコンデ
ンサとして適しているものである。On the other hand, in the samples of the present invention indicated by other sample numbers, the capacitance is large, the voltage non-linearity index α is large, and the series equivalent resistance value ESR is small. It has both the function of absorbing high frequency noise and the function of absorbing high voltage such as pulse and static electricity as a varistor at the same time. Furthermore, the capacitance temperature change rate and the varistor voltage temperature coefficient are small, and the reliability and electrical characteristics are It has the characteristic that it is not easily affected by temperature. Therefore, these samples are suitable as ceramic capacitors with a varistor function for protecting semiconductors and electronic devices from noise, pulses, static electricity, etc. generated in electronic devices.
【００２７】また、外部電極３ａの材料としてＮｉＯに
ＴｉＯ2を添加して作製されたバリスタ機能付積層セラ
ミックコンデンサでは、外部電極３ａの酸化が抑制さ
れ、ｔａｎδ、直列等価抵抗値ＥＳＲ値の低下が確認さ
れた。この原因は添加したＴｉが還元剤として作用し、
外部電極３ａの表面層の酸化を抑制し、電極の抵抗値を
下げるためであると考えられる。Further, in the multilayer ceramic capacitor with a varistor function, which is produced by adding TiO 2 to NiO as the material of the external electrode 3a, the external electrode 3a is suppressed from being oxidized, and the tan δ and the series equivalent resistance value ESR value are reduced. confirmed. This is because the added Ti acts as a reducing agent,
It is considered that this is because oxidation of the surface layer of the external electrode 3a is suppressed and the resistance value of the electrode is lowered.
【００２８】（実施例２）次に、図２においては、本発
明の第２の実施例として外部電極３ａの上層部に、新た
にＡｇまたはＡｇ−Ｐｄ系の外部電極３ｂを形成したも
のを示す。(Embodiment 2) Next, referring to FIG. 2, as a second embodiment of the present invention, a new Ag or Ag-Pd based external electrode 3b is formed on the upper layer portion of the external electrode 3a. Show.
【００２９】上記実施例１と同様のセラミック材料組成
で、内部電極組成を用いて得られた積層した成型体４の
両端に、ＮｉＯにＴｉＯ2を添加混合した外部電極ペー
ストを塗布し、空気中で１０５０℃、２時間空気中で脱
脂、仮焼を行った。その後、Ｎ2：Ｈ2＝９９：１の還元
雰囲気中で１２５０℃、２時間で焼成した。焼成後、Ａ
ｇ−Ｐｄ系（Ｐｄ：１０ｗｔ％添加）外部電極ペースト
をＮｉを主成分とする外部電極３ａの上に塗布し、空気
中で９００℃で焼付けた。そしてこれにより得られたも
のは、図２に一部切欠斜視図で示すように複数層の内部
電極２ａを、それらの内部電極２ａが成型体４の交互に
異なる端縁に至るように設けられ、かつこれらの内部電
極２ａと電気的外部電極３ａが接続され、その上にＡｇ
またはＡｇ−Ｐｄ系の外部電極３ｂが設けられたバリス
タ機能付積層セラミックコンデンサ４ａとなる。また、
図５に本実施例の製造工程を示す。An external electrode paste prepared by adding and mixing TiO 2 to NiO was applied to both ends of a laminated molded body 4 having the same ceramic material composition as in Example 1 and obtained by using the internal electrode composition, and the mixture was placed in the air. Degreasing and calcination in air at 1050 ° C. for 2 hours. Then, it was fired at 1250 ° C. for 2 hours in a reducing atmosphere of N 2 : H 2 = 99: 1. After firing, A
A g-Pd-based (Pd: 10 wt% added) external electrode paste was applied onto the external electrode 3a containing Ni as a main component, and baked in air at 900 ° C. The product thus obtained is provided with a plurality of layers of internal electrodes 2a as shown in a partially cutaway perspective view in FIG. 2 so that the internal electrodes 2a reach the different edges of the molded body 4 alternately. , And these internal electrodes 2a and electrical external electrodes 3a are connected, and Ag
Alternatively, it becomes a monolithic ceramic capacitor with a varistor function 4a provided with an Ag-Pd based external electrode 3b. Also,
FIG. 5 shows the manufacturing process of this embodiment.
【００３０】このようにして得られたバリスタ機能付積
層セラミックコンデンサについて、その容量、ｔａｎ
δ、バリスタ電圧、電圧非直線指数α、直列等価抵抗値
ＥＳＲなどの各種電気特性を、下記の（表２），（表
３）に記載する。Regarding the multilayer ceramic capacitor with a varistor function thus obtained, its capacitance, tan
Various electrical characteristics such as δ, varistor voltage, voltage non-linearity index α, and series equivalent resistance value ESR are described in (Table 2) and (Table 3) below.
【００３１】[0031]
【表２】 [Table 2]
【００３２】[0032]
【表３】 [Table 3]
【００３３】上記実施例２について解説すると、（表
２），（表３）で資料番号に＊印が記載されているもの
は比較例であり、本発明の請求範囲外である。（表２）
に示すＡｇ外部電極を形成した方が（表３）に示すＡｇ
−Ｐｄ系外部電極を形成した試料に比べ、直列等価抵抗
値ＥＳＲの値が若干低かった。これはＰｄの非抵抗値が
Ａｇの非抵抗値よりも若干高いためであると考えられ
る。Explaining Example 2 above, those in Table 2 and Table 3 marked with an asterisk * are comparative examples, which are outside the scope of the present invention. (Table 2)
Ag shown in (Table 3) is better when the Ag external electrode shown in is formed.
The series equivalent resistance value ESR was slightly lower than that of the sample in which the -Pd-based external electrode was formed. It is considered that this is because the non-resistance value of Pd is slightly higher than the non-resistance value of Ag.
【００３４】そしてまた、ＮｉＯにＴｉＯ2を添加混合
したバリスタ機能付積層セラミックコンデンサを作製し
た場合、ｔａｎδ、直列等価抵抗値ＥＳＲの低下を確認
した。この時、Ｔｉを添加していない場合では下層部の
外部電極３ａと上層部のＡｇもしくはＡｇ−Ｐｄ系外部
電極３ｂとの境界に比較的抵抗の高い層が形成されるこ
とを観察したが、下層部の外部電極ペーストにＴｉを添
加しておくと境界層が形成されないことを確認した。即
ち、Ｔｉを介してＮｉとＡｇもしくはＡｇ−Ｐｄが合金
を作るためと考えられる。しかし、この現象はＴｉを下
層部の外部電極ペーストに添加する時だけに効果があ
り、上層部の外部電極ペーストにＴｉを添加しても効果
が得られなかった。Further, when a multilayer ceramic capacitor with a varistor function was prepared by adding and mixing TiO 2 to NiO, it was confirmed that tan δ and series equivalent resistance value ESR were lowered. At this time, when Ti was not added, it was observed that a relatively high resistance layer was formed at the boundary between the lower layer external electrode 3a and the upper layer Ag or Ag-Pd based external electrode 3b. It was confirmed that the boundary layer was not formed when Ti was added to the external electrode paste of the lower layer portion. That is, it is considered that Ni and Ag or Ag-Pd form an alloy through Ti. However, this phenomenon is effective only when Ti is added to the external electrode paste of the lower layer portion, and no effect is obtained even when Ti is added to the external electrode paste of the upper layer portion.
【００３５】以上、実施例１及び２に記載してきた構成
により、バリスタ機能付積層セラミックコンデンサを容
易に作製することが可能になり、このようにして得られ
たバリスタ機能付積層セラミックコンデンサは、大容量
で、かつ電圧非直線指数αが大きく、バリスタ電圧、直
列等価抵抗値ＥＳＲが小さく、さらに温度特性、周波数
特性、ノイズ特性が優れているため、通常はコンデンサ
として電圧の低いノイズや高周波のノイズを吸収する働
きをし、一方パルスや静電気などの高い電圧が侵入した
時はバリスタ機能を発揮し、ノイズ、パルス、静電気な
どに対して優れた応答性を示し、従来のフィルムコンデ
ンサ、積層セラミックコンデンサ、半導体セラミックコ
ンデンサに変わるものとして期待されるものである。As described above, the structure described in Examples 1 and 2 makes it possible to easily manufacture a monolithic ceramic capacitor with a varistor function, and the monolithic ceramic capacitor with a varistor function thus obtained has a large size. Capacitance, large voltage nonlinear index α, small varistor voltage and series equivalent resistance ESR, and excellent temperature characteristics, frequency characteristics, and noise characteristics. It has a varistor function when a high voltage such as pulse or static electricity enters, and exhibits excellent responsiveness to noise, pulse, static electricity, etc. , Is expected to replace semiconductor ceramic capacitors.
【００３６】さらに、本発明の内部電極２ａを有するバ
リスタ機能付積層セラミックコンデンサは、従来の単板
型のバリスタ機能付セラミックコンデンサに比べて小型
でありながら大容量であり、かつ高性能であるために、
実装部品としての応用も大いに期待されるものである。
さらにＰｄ，Ａｇなどの貴金属を内部電極とするバリス
タ機能付積層セラミックコンデンサに比べ、低コストの
Ｎｉを内部電極とするために原料コストの低減が期待さ
れるものである。Further, since the monolithic ceramic capacitor with varistor function having the internal electrodes 2a of the present invention is small in size and large in capacity and high in performance as compared with the conventional single plate type ceramic capacitor with varistor function. To
Application as a mounting component is also highly expected.
Further, as compared with a monolithic ceramic capacitor with a varistor function that uses a noble metal such as Pd or Ag as an internal electrode, it is expected that the cost of raw materials will be reduced because Ni is used as an internal electrode at a low cost.
【００３７】[0037]
【発明の効果】以上のように本発明によるバリスタ機能
付セラミックコンデンサは、コンデンサ機能とバリスタ
機能を同時に有し、通常はコンデンサとして電圧の低い
ノイズや高周波のノイズを吸収する働きをし、一方パル
スや静電気などの高い電圧が侵入した時はバリスタ機能
を発揮するため、電子機器で発生するノイズ、パルス、
静電気などから半導体及び電子機器を保護する働きを持
ち、従来の単板型のバリスタ機能付セラミックコンデン
サに比べ小型でありながら大容量であり、かつ高性能で
あるため面実装部分としての応用も大いに期待され、ビ
デオカメラ、通信機器などの高密度実装用素子としても
使用できるものであるなど、その効果は極めて大きいも
のである。As described above, the ceramic capacitor with a varistor function according to the present invention has a capacitor function and a varistor function at the same time, and normally functions as a capacitor to absorb low-voltage noise and high-frequency noise, while a pulse When a high voltage such as electricity or static electricity enters, it exhibits a varistor function, so noise, pulses, and
It has a function to protect semiconductors and electronic devices from static electricity, etc., and it has a large capacity and high performance compared to the conventional single-plate type ceramic capacitor with varistor function. As expected, it can be used as a high-density mounting element for video cameras, communication devices, etc., and its effect is extremely large.
【図１】本発明の第１の実施例により得られたバリスタ
機能付積層セラミックコンデンサを示す一部切欠斜視図FIG. 1 is a partially cutaway perspective view showing a monolithic ceramic capacitor with a varistor function obtained according to a first embodiment of the present invention.
【図２】本発明の第２の実施例により得られたバリスタ
機能付積層セラミックコンデンサを示す一部切欠斜視図FIG. 2 is a partially cutaway perspective view showing a laminated ceramic capacitor with a varistor function obtained according to a second embodiment of the present invention.
【図３】本発明の第１の実施例におけるバリスタ機能付
積層セラミックコンデンサの製造工程図FIG. 3 is a manufacturing process diagram of a multilayer ceramic capacitor with a varistor function according to the first embodiment of the present invention.
【図４】本発明の第２の実施例により得られたバリスタ
機能付積層セラミックコンデンサの分解斜視図FIG. 4 is an exploded perspective view of a multilayer ceramic capacitor with a varistor function obtained according to a second embodiment of the present invention.
【図５】本発明の第２の実施例におけるバリスタ機能付
積層セラミックコンデンサの製造工程図FIG. 5 is a manufacturing process diagram of a multilayer ceramic capacitor with a varistor function according to a second embodiment of the present invention.
１，１ａ 生シート ２ 内部電極ペースト ２ａ 内部電極 ３ａ 下層の外部電極 ３ｂ 上層の外部電極 ４ 成型体 1,1a green sheet 2 internal electrode paste 2a internal electrode 3a lower layer external electrode 3b upper layer external electrode 4 molded body
Claims (2)
ｉ，Ｎａ，Ｋ原子の内の少なくとも一種類以上を固溶さ
せたペーストを出発原料とするＮｉ内部電極を設けたセ
ラミック生シートを、上記Ｎｉ内部電極が交互に対向す
る異なる端面に接するように複数枚積層して成型体を形
成し、この成型体の上記対向する端面に、上記Ｎｉ内部
電極がそれぞれ電気的に接続されるようにＴｉをＮｉま
たはＮｉ原子を含む化合物に添加混合させてなる外部電
極を設けた積層型粒界絶縁型半導体セラミックコンデン
サ。1. L for Ni or a compound containing a Ni atom
A ceramic green sheet provided with a Ni internal electrode using a paste in which at least one of i, Na, and K atoms is solid-dissolved as a starting material is in contact with different end faces where the Ni internal electrodes are alternately opposed to each other. A plurality of sheets are laminated to form a molded body, and Ti is added to and mixed with a compound containing Ni or Ni atoms so that the Ni internal electrodes are electrically connected to the facing end faces of the molded body. Multilayer grain boundary insulation type semiconductor ceramic capacitor with external electrodes.
部外部電極上に、さらにＡｇまたはＡｇ−Ｐｄ系の上層
部外部電極を設けた請求項１記載の積層型粒界絶縁型半
導体セラミックコンデンサ。2. The laminated grain boundary insulating semiconductor ceramic according to claim 1, wherein the external electrode is a lower layer external electrode, and an Ag or Ag-Pd-based upper layer external electrode is further provided on the lower layer external electrode. Capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32392492A JPH06176954A (en) | 1992-12-03 | 1992-12-03 | Laminated grain insulating type semiconductor ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32392492A JPH06176954A (en) | 1992-12-03 | 1992-12-03 | Laminated grain insulating type semiconductor ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06176954A true JPH06176954A (en) | 1994-06-24 |
Family
ID=18160151
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32392492A Pending JPH06176954A (en) | 1992-12-03 | 1992-12-03 | Laminated grain insulating type semiconductor ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06176954A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160472A (en) * | 1995-03-24 | 2000-12-12 | Tdk Corporation | Multilayer varistor |
| WO2001033588A1 (en) * | 1999-11-02 | 2001-05-10 | Tdk Corporation | Multilayer capacitor |
| WO2014120339A1 (en) * | 2013-02-01 | 2014-08-07 | Apple Inc. | Low acoustic noise capacitors |
-
1992
- 1992-12-03 JP JP32392492A patent/JPH06176954A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6160472A (en) * | 1995-03-24 | 2000-12-12 | Tdk Corporation | Multilayer varistor |
| WO2001033588A1 (en) * | 1999-11-02 | 2001-05-10 | Tdk Corporation | Multilayer capacitor |
| US6493207B2 (en) | 1999-11-02 | 2002-12-10 | Tdk Corporation | Multilayer ceramic capacitor |
| WO2014120339A1 (en) * | 2013-02-01 | 2014-08-07 | Apple Inc. | Low acoustic noise capacitors |
| US9287049B2 (en) | 2013-02-01 | 2016-03-15 | Apple Inc. | Low acoustic noise capacitors |
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