JPH0617239U - Assembly board for hybrid IC - Google Patents
Assembly board for hybrid ICInfo
- Publication number
- JPH0617239U JPH0617239U JP407692U JP407692U JPH0617239U JP H0617239 U JPH0617239 U JP H0617239U JP 407692 U JP407692 U JP 407692U JP 407692 U JP407692 U JP 407692U JP H0617239 U JPH0617239 U JP H0617239U
- Authority
- JP
- Japan
- Prior art keywords
- hybrid
- bonding
- substrate
- wire
- test
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】 （修正有）
【目的】 ハイブリッドＩＣ集合基板の周縁部に形成し
た搬送用耳部にワイヤーボンディングテスト用導体ラン
ドを設け、ハイブリッドＩＣの小形化、高密度化をはか
る。
【構成】 ハイブリッドＩＣ集合基板の周縁部に形成し
た搬送用耳部にボンディング条件設定用テストワイヤー
８をボンディングする導体ランド７を複数個設けかつ配
線電極と導体ランドが同じ材料で構成したことを特徴と
する。
(57) [Summary] (Correction) [Purpose] A conductor land for wire bonding test is provided on the carrying ear formed on the peripheral edge of the hybrid IC aggregate substrate to reduce the size and density of the hybrid IC. [Structure] A plurality of conductor lands 7 for bonding a bonding condition setting test wire 8 are provided on a carrying ear formed on a peripheral portion of a hybrid IC aggregate substrate, and the wiring electrodes and the conductor lands are made of the same material. And
Description
【０００１】[0001]
本考案はハイブリッドＩＣ用集合基板に関するものである。 The present invention relates to a hybrid IC assembly substrate.
【０００２】[0002]
従来のハイブリッドＩＣは機械的強度が高く、熱伝導性の良好なアルミナ基板 などの基板に銀ーパラジウム合金からなる電極ペーストをスクリーン印刷し焼成 して形成した配線電極にハイブリッドＩＣを構成するチップ部品の配線部とを、 金やアルミニウムの細線でボンディングするワイヤーボンディング工程において 、ワイヤーボンディング条件を設定するために、予備のテスト用基板を用いたり 、ハイブリッドＩＣ集合基板上に支障の生じない場所を利用してワイヤーのテス トボンディングを行っていた。 Conventional hybrid ICs have a high mechanical strength and have good thermal conductivity. A substrate such as an alumina substrate is screen-printed with an electrode paste made of a silver-palladium alloy and fired to form wiring electrodes. In the wire bonding process of bonding the wiring part with a thin wire of gold or aluminum, use a spare test board or use a place on the hybrid IC collective board that does not cause any problems in order to set the wire bonding conditions. I was doing test bonding of the wire.
【０００３】[0003]
しかしながら、最近電子技術のめざましい進歩により電子機器が小形化され、 これに組み込まれるところのハイブリッドＩＣはさらに小形化、高密度化され、 ハイブリッドＩＣにおいて、上述の支障を生じない場所の確保ができなくなり、 又予備のテスト用基板を用いると条件が安定せず、従って、ワイヤーボンディン グ条件を設定するためのワイヤーのテストボンディングができない課題があった 。 However, due to recent remarkable advances in electronic technology, electronic devices have been downsized, and hybrid ICs to be incorporated therein have been further downsized and densified, and it has become impossible to secure a place where the above-mentioned obstacles do not occur in the hybrid IC. Also, if a preliminary test substrate is used, the conditions are not stable, and therefore there is a problem that the test bonding of the wire for setting the wire bonding condition cannot be performed.
【０００４】[0004]
本考案は上記の課題を解決したハイブリッドＩＣ用集合基板を提供しようとす るものである。 The present invention is intended to provide a collective substrate for a hybrid IC that solves the above problems.
【０００５】 すなわち、本考案はハイブリッドＩＣを構成するチップ部品を基板に設けた配 線電極にワイヤーボンディング接続するハイブリッドＩＣ集合基板において、上 記ハイブリッドＩＣ集合基板の搬送用耳部にボンディング条件設定用テストワイ ヤーをボンディングする導体ランドを複数個設けかつ該導体ランドは上記配線電 極と同じ電極材料で構成したことを特徴とするハイブリッドＩＣ用集合基板であ る。That is, the present invention relates to a hybrid IC aggregate substrate in which chip components constituting the hybrid IC are connected to wiring electrodes provided on the substrate by wire bonding. A hybrid IC aggregate substrate is characterized in that a plurality of conductor lands for bonding a test wire are provided and the conductor lands are made of the same electrode material as that of the wiring electrode.
【０００６】[0006]
本考案は上記したようにハイブリッドＩＣ集合基板の周縁部に形成した搬送用 耳部に配線電極と同一の厚膜材料からなる導体ランドを複数個設けるので、配線 電極と導体ランドを同時に印刷、焼成でき、ハイブリッドＩＣが小型化、高密度 化されても、ワイヤーのボンディングテストが精度良くできる。 According to the present invention, a plurality of conductor lands made of the same thick film material as the wiring electrodes are provided in the carrying ear portion formed on the peripheral portion of the hybrid IC aggregate substrate as described above. Therefore, the wiring electrodes and the conductor lands are simultaneously printed and fired. Even if the hybrid IC is downsized and the density is increased, the wire bonding test can be performed accurately.
【０００７】[0007]
以下、本考案を図１について説明する。 １は機械的強度が高く、熱伝導性の良好なアルミナ基板などからなる絶縁基板 ２上に銀ーパラジウム合金からなる電極ペーストをスクリーン印刷して焼成した 配線電極を配設して回路パターン３を形成したハイブリッドＩＣ集合基板、４は ハイブリッドＩＣを構成する半導体チップ、チップコンデンサなどのチップ部品 、５はチップ部品４の配線部と上記回路パターン３を接続する金、アルミニウム などからなる細いワイヤー、６は回路パターン３を配設しないハイブリッドＩＣ 集合基板１の周縁部の搬送用耳部、７は該搬送用耳部６に複数個設けたボンディ ング条件設定用導体ランドで上記配線電極と同じ電極材料で同時に印刷、焼成し て形成される。そして８はテストワイヤーである。 The present invention will be described below with reference to FIG. Reference numeral 1 denotes a circuit pattern 3 in which an electrode paste made of a silver-palladium alloy is screen-printed and fired on an insulating substrate 2 made of an alumina substrate having high mechanical strength and good thermal conductivity and wiring electrodes are arranged. The hybrid IC collective substrate, 4 is a chip component such as a semiconductor chip or a chip capacitor that constitutes the hybrid IC, 5 is a thin wire made of gold, aluminum or the like for connecting the wiring portion of the chip component 4 and the circuit pattern 3, and 6 is Hybrid IC not having the circuit pattern 3 Arranged on the peripheral edge of the substrate 1 is a carrier ear 7, and a plurality of bonding condition setting conductor lands are provided on the carrier ear 6 and made of the same electrode material as the wiring electrodes. It is formed by printing and firing at the same time. And 8 is a test wire.
【０００８】 ところでハイブリッドＩＣを製造する場合、上記のようにして構成されたハイ ブリッドＩＣ集合基板１の回路パターン３を形成する配線電極にチップ部品４を ワイヤー５を用いてワイヤーボンディング接続する工程において、ワイヤーボン ディング条件を設定するために、ハイブリッドＩＣ集合基板１の周縁部に設けた 搬送用耳部６に設けた複数個のボンディング条件設定用導体ランド７でテストワ イヤー８を用いてワイヤーのボンディングテストを行って、最良のボンディング 条件を設定し、その最良のボンディング条件によって回路パターン３を形成する 配線電極にチップ部品４をワイヤー５を用いてワイヤーボンディング接続する。By the way, when manufacturing a hybrid IC, in the step of wire-bonding the chip component 4 to the wiring electrode forming the circuit pattern 3 of the hybrid IC collective substrate 1 configured as described above using the wire 5. In order to set the wire bonding conditions, a plurality of bonding condition setting conductor lands 7 provided on the carrying ear 6 provided at the peripheral edge of the hybrid IC aggregate substrate 1 are used to bond wires using a test wire 8. A test is conducted to set the best bonding conditions, and the circuit components 3 are formed under the best bonding conditions. The chip component 4 is wire-bonded to the wiring electrodes by using the wires 5.
【０００９】 ハイブリッドＩＣを使用するときには、ハイブリッドＩＣ集合基板１の周縁部 に設けた搬送用耳部６をカットして、小形のハイブリッドＩＣを形成する。When the hybrid IC is used, the carrying ear portion 6 provided on the peripheral portion of the hybrid IC aggregate substrate 1 is cut to form a small hybrid IC.
【００１０】[0010]
本考案は、ハイブリッドＩＣ集合基板の周縁部に設けた搬送用耳部にボンディ ング条件設定用導体ランドでテストワイヤーを用いてボンディングテストを行っ て、最良のボンディング条件を設定し、その最良ボンディング条件によって回路 パターンを形成する配線電極にチップ部品をワイヤーでボンディング接続し、し かもハイブリッドＩＣ使用時に搬送用耳部をカットするので、品質的に向上かつ 安定で、小形化、高密度化できるなどの効果があり、工業的ならびに実用的価値 大である。 The present invention performs a bonding test by using a test wire with a bonding land for setting a bonding condition on a transfer ear portion provided on a peripheral portion of a hybrid IC aggregate substrate to set the best bonding condition and then the best bonding condition. By connecting the chip components to the wiring electrodes that form the circuit pattern with wires and cutting the transfer ears when using the hybrid IC, it is possible to improve quality and stability, and to reduce the size and density. It is effective and has great industrial and practical value.
【図１】本考案に係るハイブリッドＩＣ集合基板の一実
施例の平面図である。FIG. 1 is a plan view of an embodiment of a hybrid IC aggregate substrate according to the present invention.
１ ハイブリッドＩＣ集合基板 ２ 絶縁基板 ３ 回路パターン ４ チップ部品 ５ ワイヤー ６ 搬送用耳部 ７ ボンディング条件設定用導体ランド ８ テストワイヤー 1 Hybrid IC Assembly Board 2 Insulating Board 3 Circuit Pattern 4 Chip Component 5 Wire 6 Transfer Ear 7 Bonding Condition Setting Conductor Land 8 Test Wire
Claims (1)
を基板に設けた配線電極にワイヤーボンディング接続す
るハイブリッドＩＣ集合基板において、上記ハイブリッ
ドＩＣ集合基板の搬送用耳部にボンディング条件設定用
テストワイヤーをボンディングする導体ランドを複数個
設けかつ該導体ランドは上記配線電極と同じ電極材料で
構成したことを特徴とするハイブリッドＩＣ用集合基
板。1. In a hybrid IC aggregate substrate in which chip components constituting the hybrid IC are connected by wire bonding to wiring electrodes provided on the substrate, a bonding condition setting test wire is bonded to a carrying ear portion of the hybrid IC aggregate substrate. A hybrid IC collective substrate, wherein a plurality of conductor lands are provided and the conductor lands are made of the same electrode material as that of the wiring electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP407692U JP2552582Y2 (en) | 1992-01-08 | 1992-01-08 | Assembly board for hybrid IC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP407692U JP2552582Y2 (en) | 1992-01-08 | 1992-01-08 | Assembly board for hybrid IC |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0617239U true JPH0617239U (en) | 1994-03-04 |
| JP2552582Y2 JP2552582Y2 (en) | 1997-10-29 |
Family
ID=11574716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP407692U Expired - Lifetime JP2552582Y2 (en) | 1992-01-08 | 1992-01-08 | Assembly board for hybrid IC |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2552582Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006229161A (en) * | 2005-02-21 | 2006-08-31 | Sumitomo Electric Ind Ltd | Multiple surface mounting board |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11243494B2 (en) | 2002-07-31 | 2022-02-08 | Abs Global, Inc. | Multiple laminar flow-based particle and cellular separation with laser steering |
| US10908066B2 (en) | 2010-11-16 | 2021-02-02 | 1087 Systems, Inc. | Use of vibrational spectroscopy for microfluidic liquid measurement |
| US11796449B2 (en) | 2013-10-30 | 2023-10-24 | Abs Global, Inc. | Microfluidic system and method with focused energy apparatus |
| US11331670B2 (en) | 2018-05-23 | 2022-05-17 | Abs Global, Inc. | Systems and methods for particle focusing in microchannels |
| CN117413819A (en) | 2019-04-18 | 2024-01-19 | 艾步思国际有限责任公司 | System and process for continuous addition of cryoprotectant |
-
1992
- 1992-01-08 JP JP407692U patent/JP2552582Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006229161A (en) * | 2005-02-21 | 2006-08-31 | Sumitomo Electric Ind Ltd | Multiple surface mounting board |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2552582Y2 (en) | 1997-10-29 |
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