JPH06169083A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH06169083A JPH06169083A JP4319624A JP31962492A JPH06169083A JP H06169083 A JPH06169083 A JP H06169083A JP 4319624 A JP4319624 A JP 4319624A JP 31962492 A JP31962492 A JP 31962492A JP H06169083 A JPH06169083 A JP H06169083A
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- Prior art keywords
- insulating film
- gate insulating
- semiconductor device
- impurity
- film
- Prior art date
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- Non-Volatile Memory (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置およびその製
造方法に関し、詳しくは、高いホットキャリア耐性を有
するゲート絶縁膜を具備したＭＯＳ型半導体装置および
その製造方法に関わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS semiconductor device having a gate insulating film having high hot carrier resistance and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図１は従来のＭＯＳトランジスタの要部
の断面構造の概略を示す図である。周知のように、従来
のＭＯＳトランジスタのゲ−ト酸化膜１６は、高温の酸
化性雰囲気中でシリコン基板１の表面を酸化することに
よって形成された。図１において、起動１２は素子分離
用絶縁膜、１３は拡散層、１４は金属配線、１５はゲー
ト電極を、それぞれ表わす。2. Description of the Related Art FIG. 1 is a diagram schematically showing a sectional structure of a main part of a conventional MOS transistor. As is well known, the gate oxide film 16 of the conventional MOS transistor is formed by oxidizing the surface of the silicon substrate 1 in a high temperature oxidizing atmosphere. In FIG. 1, start-up 12 is an insulating film for element isolation, 13 is a diffusion layer, 14 is a metal wiring, and 15 is a gate electrode.
【０００３】ゲート絶縁膜のホットキャリアやトンネル
電流による損傷に対する耐性を向上させるため、上記ゲ
ート絶縁膜を形成した後、ＮＨ3、Ｎ2Ｏ、等を含む雰囲
気中で熱処理して、上記熱酸化によって形成されたシリ
コン酸化膜とシリコン基板の界面近傍に、微量の窒素を
添加する方法が提案されている。また、同じ目的のため
に、イオン注入やＨＦ溶液中への浸積によって、フッ素
を上記界面に添加することも提案されている。In order to improve the resistance of the gate insulating film to damage due to hot carriers or tunnel current, after the gate insulating film is formed, it is heat-treated in an atmosphere containing NH 3 , N 2 O, etc., and the thermal oxidation is performed. A method has been proposed in which a trace amount of nitrogen is added near the interface between the silicon oxide film formed by and the silicon substrate. For the same purpose, it has also been proposed to add fluorine to the above interface by ion implantation or immersion in an HF solution.
【０００４】これら従来の方法は、界面における不飽和
結合に窒素やフッ素を結び付けて、電子や正孔の捕獲準
位を減少させるので、ホットキャリアやトンネル電流の
注入による、ＭＯＳトランジスタの特性変動の防止に有
効であり、アイ・イ−・イ−・イ−、エレクトロン・デ
バイス・レタ−ズ（IEEE Electron Device Letters）第
１０巻第４号第１４１頁（1989)やアイ・イ−・イ−・
イ−、エレクトロン・デバイス・レタ−ズ（IEEE Elect
ron Device Lett.）第１０巻第６４頁(1987)に記載され
ている。In these conventional methods, nitrogen or fluorine is bound to the unsaturated bond at the interface to reduce the trap level of electrons or holes, so that the characteristic variation of the MOS transistor due to the injection of hot carriers or tunnel current may occur. It is effective for prevention, and is eye-eye-eye, electron device letters (IEEE Electron Device Letters) Vol. 10, No. 4, page 141 (1989) and eye-eye.・
E-Electron Device Letter (IEEE Elect
ron Device Lett.) Vol. 10, p. 64 (1987).
【０００５】[0005]
【発明が解決しようとする課題】しかし、上記従来の方
法においては、ゲート酸化膜中にフッ素や窒素を熱的に
拡散させて界面近傍に導入するため、これらの元素が過
度に多量に導入されて界面の整合性が破壊されてしまっ
たり、反対に、導入量が不十分で、不飽和結合を十分に
埋めることが出来ないなど、最適な導入量の制御が困難
であった。However, in the above-mentioned conventional method, since fluorine and nitrogen are thermally diffused into the gate oxide film and introduced near the interface, excessive amounts of these elements are introduced. Therefore, it is difficult to control the optimum amount of introduction, because the integrity of the interface is destroyed and, on the contrary, the amount of introduction is insufficient and the unsaturated bond cannot be sufficiently filled.
【０００６】図２（ａ）は、厚さ８ｎｍのシリコン熱酸
化膜をアンモニアガス雰囲気中で熱処理したときの、シ
リコン熱酸化膜中の窒素の深さ方向の分布を、オ−ジェ
電子分光分析によって測定した結果の一例を示し、図２
（ｂ）は当該窒素を含むシリコン熱酸化膜を８５０℃の
酸素雰囲気中で、再度酸化処理を５分間行った後の窒素
の分布を、オ−ジェ電子分光分析によって測定した一例
でを示す。また、図３は、図２（ａ）（ｂ）で示した２
種類のシリコン酸化膜の上に多結晶シリコン電極を形成
してＭＯＳキャパシタを作成し、電子を０．１ク−ロン
／ｃｍ2注入した時の界面準位の増加量と、フラットバ
ンド電圧の変動量を比較した図である。これらの図から
明らかなように、窒化処理によって窒素はＳｉＯ2／Ｓ
ｉ界面近傍に選択的に固溶し、８原子％程度の窒素が固
溶した場合には、電子注入が起った場合における界面準
位および捕獲電荷の増加量は、窒化処理しない熱酸化シ
リコンの場合よりも大きくなってしまう。再酸化処理を
行うと、固溶窒素量は界面近傍で０．０１〜０．１％に
減少させることが出来、界面準位の増加を熱酸化シリコ
ンの場合よりも少なくすることが可能となる、しかし、
この場合、窒素がＳｉＯ2膜中に拡散し、広く分布され
てしまうため、電子の捕獲準位の数を低減することが出
来ないという欠点がある。FIG. 2A shows the distribution of nitrogen in the silicon thermal oxide film in the depth direction when an 8 nm-thick silicon thermal oxide film was heat-treated in an ammonia gas atmosphere by Auger electron spectroscopy analysis. 2 shows an example of the result measured by
(B) shows an example in which the nitrogen distribution after the oxidation treatment of the silicon thermal oxide film containing nitrogen in the oxygen atmosphere at 850 ° C. was performed again for 5 minutes was measured by Auger electron spectroscopy. In addition, FIG. 3 shows the 2 shown in FIGS.
Variation in flat band voltage and increase in interface state when electron is injected at 0.1 kl / cm 2 by forming polycrystalline silicon electrode on various kinds of silicon oxide film and forming MOS capacitor It is the figure which compared the quantity. As is clear from these figures, nitrogen is converted into SiO 2 / S by the nitriding treatment.
In the case where nitrogen is selectively dissolved in the vicinity of the i interface and about 8 atom% of nitrogen is dissolved, the increase in the interface state and the trapped charge when electron injection occurs is determined by the thermal oxidation of the non-nitrided silicon oxide. It will be bigger than the case. When the reoxidation treatment is performed, the amount of solute nitrogen can be reduced to 0.01 to 0.1% in the vicinity of the interface, and the increase in the interface state can be made smaller than that in the case of thermally oxidized silicon. ,However,
In this case, nitrogen diffuses into the SiO 2 film and is widely distributed, so that the number of electron trap levels cannot be reduced.
【０００７】一方、これと同様に、シリコン酸化膜をゲ
−ト絶縁膜として用いるフラッシュメモリは、当該ゲー
ト絶縁膜に高い電界を印加して浮遊電極中に電荷を注入
し、蓄積して情報の書き込みと消去を行なう不揮発性メ
モリである。図４は、フラッシュメモリの断面構造の概
略を示した図である。高電界で絶縁膜中に注入された電
子は、電界で加速されて高エネルギ−状態となり、Ｓｉ
Ｏ2膜中に電荷単体の捕獲中心が形成される。この捕獲
中心に電子あるいは正孔が捕獲されて、ＭＯＳトランジ
スタ内部の電位分布状態が変化する。On the other hand, similarly, in a flash memory using a silicon oxide film as a gate insulating film, a high electric field is applied to the gate insulating film to inject a charge into the floating electrode and store the information. It is a non-volatile memory that performs writing and erasing. FIG. 4 is a diagram showing an outline of a sectional structure of the flash memory. The electrons injected into the insulating film at a high electric field are accelerated by the electric field to be in a high energy state,
A trap center of a charge unit is formed in the O 2 film. Electrons or holes are trapped in the trap centers, and the potential distribution state inside the MOS transistor changes.
【０００８】このため、ＭＯＳトランジスタにおけるホ
ットキャリアやトンネル電流の注入による閾値電圧の変
動、および移動度の低下の両者を改善できるゲ−ト絶縁
膜を提供することが困難であった。Therefore, it is difficult to provide a gate insulating film capable of improving both the fluctuation of the threshold voltage due to the injection of hot carriers and tunnel current in the MOS transistor and the decrease of the mobility.
【０００９】本発明の目的は、上記従来の問題を解決
し、ホットキャリアやトンネル電流の注入による、閾値
電圧の変動や移動度の低下を防止することの出来る、半
導体装置およびその製造方法を提供することである、An object of the present invention is to solve the above-mentioned conventional problems and to provide a semiconductor device and a method of manufacturing the same capable of preventing fluctuations in threshold voltage and reduction in mobility due to injection of hot carriers or tunnel current. It is to be,
【００１０】[0010]
【課題を解決するための手段】上記目的を達成するた
め、本発明は、ＭＯＳトランジスタのゲ−ト絶縁膜の膜
厚方向に、濃度が周期的に変化するように不純物を添加
するものである。In order to achieve the above object, the present invention is to add an impurity in the thickness direction of the gate insulating film of a MOS transistor so that the concentration thereof changes periodically. .
【００１１】すなわち、図５に窒素添加した場合を例に
して示したように、ＭＯＳトランジスタの導電チャネル
が形成されるＳｉ基板上に形成されたＳｉＯ2からなる
ゲ−ト絶縁膜において、ＳｉＯ2膜とＳｉ基板の界面か
らゲ−ト電極とＳｉＯ2との界面に向かって、窒素、フ
ッ素、塩素、りん、砒素、硼素、アルミニウム、炭素、
ガリウム、ゲルマニウム等の不純物を、その濃度が周期
的に変化するように添加することにより、上記目的は達
成することが出来る。[0011] That is, as shown in the case of adding nitrogen in Figure 5, gate made of SiO 2 in which the conductive channel of the MOS transistor is formed on a Si substrate formed - in gate insulating film, SiO 2 From the interface between the film and the Si substrate toward the interface between the gate electrode and SiO 2 , nitrogen, fluorine, chlorine, phosphorus, arsenic, boron, aluminum, carbon,
The above object can be achieved by adding impurities such as gallium and germanium so that the concentration thereof changes periodically.
【００１２】[0012]
【作用】絶縁膜中に注入された電子または正孔は、絶縁
膜内部の電界によって加速されて運動エネルギが増加す
る。その結果、高エネルギの電荷坦体が、ＳｉＯ2膜お
よび界面に損傷を与える。しかし、本発明のように絶縁
膜中に不純物を添加すると、電荷坦体の加速が抑制さ
れ、結果として上記損傷が低減される。The electrons or holes injected into the insulating film are accelerated by the electric field inside the insulating film and the kinetic energy increases. As a result, the high energy charge carriers damage the SiO 2 film and the interface. However, when impurities are added to the insulating film as in the present invention, acceleration of the charge carrier is suppressed, and as a result, the damage is reduced.
【００１３】また他の効果として、非晶質ＳｉＯ2膜の
内部に存在する化学結合の歪が、絶縁膜の厚さ方向に周
期的に添加された不純物によって緩和されるため、上記
化学結合を切断するための活性化エネルギ−を大きくで
きる。これにより、注入された電荷単体によって損傷を
受けにくい絶縁膜を形成することができ、ホットキャリ
アやトンネル電流に対する耐性の高いＭＯＳトランジス
タや不揮発性メモリが形成される。As another effect, the strain of the chemical bond existing inside the amorphous SiO 2 film is relaxed by the impurities periodically added in the thickness direction of the insulating film. The activation energy for cutting can be increased. This makes it possible to form an insulating film that is less likely to be damaged by the injected electric charge alone, thereby forming a MOS transistor or a non-volatile memory having high resistance to hot carriers and tunnel current.
【００１４】なお、図５は、絶縁膜内に不純物濃度のピ
ークが５個形成された場合を示したが、イオン打込みの
際の加速電圧を適宜変えることによって、所望の数のピ
ークを絶縁膜内に形成できることはいうまでもない。Although FIG. 5 shows the case where five impurity concentration peaks are formed in the insulating film, a desired number of peaks can be formed in the insulating film by appropriately changing the acceleration voltage at the time of ion implantation. It goes without saying that it can be formed inside.
【００１５】[0015]
〈実施例１〉本実施例では、図１に示したと同じ断面構
造を有するＭＯＳトランジスタに本発明を適用した例を
示す。<Embodiment 1> In this embodiment, an example in which the present invention is applied to a MOS transistor having the same sectional structure as shown in FIG. 1 is shown.
【００１６】ゲート絶縁膜１６は、低圧ＣＶＤ法によっ
て形成し、各種ガスは図６に示したように供給した。す
なわち、図６に示すように、ＳｉＨ4ガスとＮ2Ｏガスを
１対１０の流量比で反応容器内に導入してＳｉＯ2層を
形成する際に、適当な時間間隔をおいてＮＨ3ガスを上
記反応容器内に間歇的に混入した。図６においてｔ0は
厚さ１ｎｍの絶縁膜が成長するに要する時間を表わす。
本実施例ではＳｉＨ4：Ｎ2Ｏ：ＮＨ3の流量比を１：１
０：０．１とした。この程度のＮＨ3を混入しても、膜
の成長速度は大きくは変らないので、ＮＨ3を混入する
時間と、混入しない時間は等しく設定した。The gate insulating film 16 was formed by the low pressure CVD method, and various gases were supplied as shown in FIG. That is, as shown in FIG. 6, when an SiH 4 gas and an N 2 O gas are introduced into the reaction vessel at a flow rate ratio of 1:10 to form a SiO 2 layer, an NH 3 gas is provided at an appropriate time interval. The gas was intermittently mixed in the reaction vessel. In FIG. 6, t 0 represents the time required for growing an insulating film having a thickness of 1 nm.
In this embodiment, the flow ratio of SiH 4 : N 2 O: NH 3 is 1: 1.
It was set to 0: 0.1. Even if NH 3 of this amount is mixed, the growth rate of the film does not greatly change, so the time for mixing NH 3 and the time for not mixing NH 3 were set equal.
【００１７】形成された絶縁膜中の窒素の膜厚方向の分
布を、オ−ジェ電子分光法を用いて分析し、得られた結
果を図７に示した。図７から明らかなように、絶縁膜中
の窒素濃度は、１０ｎｍおきに周期的に２個のピーク
（左端のピークは電極との界面に形成されたピーク）を
示しており、その最大値は約１原子％であった。The distribution of nitrogen in the film thickness direction in the formed insulating film was analyzed by Auger electron spectroscopy, and the obtained results are shown in FIG. As is clear from FIG. 7, the nitrogen concentration in the insulating film periodically shows two peaks at intervals of 10 nm (the peak at the left end is the peak formed at the interface with the electrode), and the maximum value thereof is It was about 1 atomic%.
【００１８】Ｎ2ＯとＮＨ3の流量比を適当に変えること
により、上記絶縁膜中の窒素の含有量を、Ｓｉ3Ｎ4から
ＳｉＯ2までの間で自由に設定することが出来た。By appropriately changing the flow rate ratio of N 2 O and NH 3 , the nitrogen content in the insulating film can be freely set between Si 3 N 4 and SiO 2 .
【００１９】本実施例で得られたＭＯＳトランジスタに
ついて、ホットキャリア効果による閾値電圧の変動およ
び伝達コンダクタンスの変動を調べた結果、従来の熱酸
化膜をゲート絶縁膜として使用したＭＯＳトランジスタ
にくらべて、いずれも約１０倍耐性向上が認められた。With respect to the MOS transistor obtained in this example, the variation of the threshold voltage and the variation of the transfer conductance due to the hot carrier effect were examined. As a result, as compared with the conventional MOS transistor using the thermal oxide film as the gate insulating film, In each case, the resistance was improved about 10 times.
【００２０】〈実施例２〉実施例１において用いたＮＨ
3に代えて、ＣＨ4，ＮＦ3，Ｃｌ2，ＨＣｌ，ＣｌＦ3，
ＨＦ，ＰＨ3，ＡｓＨ3，Ｂ2Ｈ6，ＧｅＨ4を用い、実施
例１と同様な方法でゲート絶縁膜を形成したところ、
Ｃ，Ｆ，Ｃｌ，Ｐ，Ａｓ，Ｂ，Ｇｅが、実施例１におけ
るＮと同様の濃度分布で、ゲート絶縁膜中に含有されて
いることが確認された。<Example 2> NH used in Example 1
Instead of 3 , CH 4 , NF 3 , Cl 2 , HCl, ClF 3 ,
When HF, PH 3 , AsH 3 , B 2 H 6 , and GeH 4 were used to form a gate insulating film in the same manner as in Example 1,
It was confirmed that C, F, Cl, P, As, B and Ge had the same concentration distribution as N in Example 1 and were contained in the gate insulating film.
【００２１】また、ジメチルアルミハイドライド（（Ｃ
Ｈ3）2ＡｌＨ），トリイソブチルアルミニュウム（（Ｃ
4Ｈ9）3Ａｌ），トリメチルガリュウム（（ＣＨ3）3Ｇ
ａ）を使用すれば、Ａｌ，Ｇａも同じように添加出来る
ことが確認された。Dimethyl aluminum hydride ((C
H 3) 2 AlH), triisobutyl aluminum Niu arm ((C
4 H 9 ) 3 Al), trimethylgallium ((CH 3 ) 3 G
It was confirmed that Al and Ga can be added in the same manner by using a).
【００２２】本実施例で得られた絶縁膜を用いて形成さ
れた、図１に示す構造のＭＯＳトランジスタは、実施例
１の場合と同様に、ホットキャリア耐性が、従来よりも
５倍から１０倍向上していることが認められた。The MOS transistor of the structure shown in FIG. 1 formed by using the insulating film obtained in this embodiment has a hot carrier resistance of 5 to 10 times that of the conventional one, as in the case of the first embodiment. It was confirmed that it was doubled.
【００２３】〈実施例３〉実施例１において、ＮＨ3を
混入する時間間隔ｔ´を変化させで、絶縁膜中への窒素
の添加を行ない、ゲート絶縁膜を形成した。すなわち、
ｔ´を変えることにより、ゲート絶縁膜中における窒素
添加層の数、厚さおよび窒素の平均濃度をそれぞれ変え
ることが可能である。<Example 3> In Example 1, nitrogen was added to the insulating film by changing the time interval t'for mixing NH 3 to form a gate insulating film. That is,
By changing t ′, it is possible to change the number and thickness of the nitrogen-added layers in the gate insulating film and the average nitrogen concentration.
【００２４】ゲート絶縁膜中の上記窒素添加層を０層、
１層、５層、８層とし、各ゲート絶縁膜に対し、それぞ
れ１ク−ロン／ｃｍ2のトンネル電流注入を行った際に
おける界面準位の増加量と、経時的絶縁破壊（ＴＤＤ
Ｂ）を生ずる臨界電荷量を比較し、得られた結果を図８
に示した。図８から明らかなように、いずれの特性も、
窒素添加層が５層および８層のである絶縁膜が優れてお
り、対トンネル電流損傷性に優れていることが認められ
た。窒素添加層の数をさらに増加させて１０層とした場
合も、同様に従来の熱酸化膜に比べて対トンネル電流損
傷性が優れていることが確認された。The nitrogen-containing layer in the gate insulating film is 0 layer,
One layer, five layers, and eight layers, and the amount of increase in the interface state and the time-dependent dielectric breakdown (TDD) when each tunnel insulating film was injected with a tunnel current of 1 cron / cm 2.
The results obtained by comparing the critical charge amounts causing B) are shown in FIG.
It was shown to. As is clear from FIG. 8, both characteristics are
It was confirmed that the insulating film having 5 and 8 nitrogen-added layers was excellent, and was excellent in tunnel current damage resistance. It was confirmed that even when the number of nitrogen-added layers was further increased to 10 layers, the tunnel current damage resistance was similarly superior to that of the conventional thermal oxide film.
【００２５】〈実施例４〉上記実施例３と同様にして、
窒素添加層とＳｉＯ2層を積層して形成する際に、各ガ
スの流量を変化させるとともに、Ｓｉ基板の温度を、図
９に示すように変化させて絶縁膜を形成した。この際、
最高温度は８００℃以上とし、弱い酸化性雰囲気（例え
ば酸素分圧１００ｐｐｍ以上１％以下）中で熱処理を行
なった。<Embodiment 4> In the same manner as in Embodiment 3,
When the nitrogen-added layer and the SiO 2 layer were laminated and formed, the flow rate of each gas was changed and the temperature of the Si substrate was changed as shown in FIG. 9 to form the insulating film. On this occasion,
The maximum temperature was 800 ° C. or higher, and the heat treatment was performed in a weak oxidizing atmosphere (for example, oxygen partial pressure of 100 ppm or more and 1% or less).
【００２６】このような熱処理を加えた膜形成工程によ
って形成されたゲ−ト絶縁膜の耐トンネル電流損傷性
は、上記熱処理を行なわない場合に比べ、３〜５倍優れ
ていることが認められた。It is recognized that the gate insulating film formed by the film forming process to which the heat treatment is applied has a tunnel current damage resistance which is 3 to 5 times better than the case where the heat treatment is not performed. It was
【００２７】得られたゲ−ト絶縁膜を用いてＭＯＳトラ
ンジスタを形成し、ホットキャリアに対する耐性を測定
したところ、前記耐トンネル電流損傷性とほぼ同様の改
善が認められた。When a MOS transistor was formed using the obtained gate insulating film and the resistance to hot carriers was measured, an improvement similar to the tunnel current damage resistance was recognized.
【００２８】さらに、多結晶シリコン上に形成された、
いわゆるポリシリコンＭＯＳＦＥＴに本実施例で得られ
たゲ−ト絶縁膜を使用したところ、連続動作における特
性の変動が著しく改善された。Further, formed on polycrystalline silicon,
When the gate insulating film obtained in this example was used for a so-called polysilicon MOSFET, fluctuations in characteristics during continuous operation were remarkably improved.
【００２９】〈実施例５〉本実施例は、図４に示した断
面構造を有するフラッシュ型メモリに、本発明を適用し
た例である。図４において、ゲート絶縁膜２６として上
記実施例１および２において使用されたと同じ絶縁膜を
用いた。上記メモリでは、書込みに際し、制御ゲ−ト電
極２５に１０Ｖ、ドレイン１３に２．７Ｖ、ソ−スに０
Ｖ、をそれぞれ印加して、いわゆるチャネルホットキャ
リアを発生させ、これを浮遊ゲ−トに注入させた。消去
に際しては、制御ゲ−ト２５に０Ｖ、ソ−スに１２Ｖを
印加して、いわゆるファウラ−ノルトハイム型のトンネ
ル電流によって浮遊ゲ−トから蓄積されていた電子を引
き抜いた。これらの動作にともない、ＭＯＳトランジス
タの伝達コンダクタンスの低下、書き込み時間の増大、
消去時間の増大など、ゲ−ト絶縁膜２６の損傷増加に起
因する特性の劣化が認められた。<Embodiment 5> This embodiment is an example in which the present invention is applied to a flash type memory having the sectional structure shown in FIG. In FIG. 4, the same insulating film as used in Examples 1 and 2 was used as the gate insulating film 26. In the above memory, at the time of writing, 10V is applied to the control gate electrode 25, 2.7V is applied to the drain 13, and 0 is applied to the source.
V was applied to generate so-called channel hot carriers, which were injected into the floating gate. At the time of erasing, 0 V was applied to the control gate 25 and 12 V was applied to the source, so that electrons accumulated from the floating gate were extracted by a so-called Fowler-Nordheim tunnel current. With these operations, the transfer conductance of the MOS transistor is lowered, the writing time is increased,
Deterioration of characteristics due to increased damage of the gate insulating film 26 such as an increase in erase time was observed.
【００３０】しかし、この特性劣化を、通常の熱酸化膜
をゲ−ト絶縁膜として用いたフラッシュ型不揮発性メモ
リの場合と比較したところ、伝達コンダクタンスの低下
は約１／１０、書き込み時間の増大は約１／５、消去時
間の増大は約１／１０であって、窒素が層状に添加され
たゲ−ト絶縁膜を用いた場合は、従来の熱酸化膜を用い
た場合に比べ著しく改善されているのが認められた。However, when this characteristic deterioration is compared with the case of a flash type nonvolatile memory using a normal thermal oxide film as a gate insulating film, the transfer conductance is reduced by about 1/10 and the write time is increased. Is about 1/5, and the increase in erasing time is about 1/10. When the gate insulating film with nitrogen added in layers is used, it is remarkably improved as compared with the conventional thermal oxide film. It was recognized that it was being done.
【００３１】さらに、窒素の添加に加えて、フッ素およ
び塩素を、窒素の場合とは異なる濃度分布で添加したと
ころ、Ｎ2のみの場合よりさらに最大２倍程度の効果が
得られた。また、Ｃ，Ｐ，Ａｓ，Ｂ，Ａｌ，Ｇｅ，Ｇａ
を用いても、同様な効果が得られることが確かめられ
た。Further, in addition to the addition of nitrogen, when fluorine and chlorine were added in a concentration distribution different from that of nitrogen, an effect up to about twice as much as that of N 2 alone was obtained. Also, C, P, As, B, Al, Ge, Ga
It was confirmed that the same effect can be obtained by using.
【００３２】〈実施例６〉本実施例は、本発明を、絶縁
膜上に形成された多結晶シリコン膜を伝導路とする、い
わゆるｐｏｌｙ−ＳｉＭＯＳＦＥＴに適用した例であ
る。<Embodiment 6> This embodiment is an example in which the present invention is applied to a so-called poly-Si MOSFET in which a polycrystalline silicon film formed on an insulating film is used as a conduction path.
【００３３】図１０において、シリコン基板３０の上に
形成された第１の絶縁膜３１の上にｎ型多結晶シリコン
からなるゲート電極３９を形成し、さらに、その上に、
実施例１に示した方法を用いてゲート絶縁膜３８を形成
した。次に、多結晶シリコン膜３４を形成し、その両端
にソースおよびドレインとなるｐ型拡散相３３、３５を
形成し、金属配線３６、３７と接続した。In FIG. 10, a gate electrode 39 made of n-type polycrystalline silicon is formed on the first insulating film 31 formed on the silicon substrate 30, and further thereon,
The gate insulating film 38 was formed using the method shown in the first embodiment. Next, a polycrystalline silicon film 34 was formed, p-type diffusion phases 33 and 35 serving as a source and a drain were formed on both ends thereof, and connected to metal wirings 36 and 37.
【００３４】本実施例で形成されたｐｏｌｙ−ＳｉＭＯ
ＳＦＥＴを動作させ、従来の熱酸化膜あるいはＣＶＤ−
ＳｉＯ2膜を用いた場合にくらべて、閾値電圧の変動は
約１／２になった。Poly-SiMO formed in this example
Operate the SFET to operate the conventional thermal oxide film or CVD-
Compared with the case where the SiO 2 film was used, the fluctuation of the threshold voltage became about 1/2.
【００３５】[0035]
【発明の効果】上記説明から明らかなように、本発明に
よれば、ホットキャリアによるＭＯＳトランジスタの特
性劣化を低減することが出来る。さらに、フラッシュ型
不揮発性メモリの、書き込みと消去の繰返しによる特性
劣化を低減することが出来るので、半導体装置の特性お
よび信頼性の向上に極めて有用である。As is apparent from the above description, according to the present invention, it is possible to reduce the characteristic deterioration of the MOS transistor due to hot carriers. Further, since the characteristic deterioration of the flash type nonvolatile memory due to the repetition of writing and erasing can be reduced, it is extremely useful for improving the characteristics and reliability of the semiconductor device.
【図１】従来のＭＯＳトランジスタの断面構造の概略を
示す図。FIG. 1 is a diagram schematically showing a cross-sectional structure of a conventional MOS transistor.
【図２】従来の酸化膜中における窒素の深さ方向分布を
示す図。FIG. 2 is a view showing a distribution of nitrogen in a depth direction in a conventional oxide film.
【図３】界面準位密度およびフラットバンド電圧の変動
量を比較した図。FIG. 3 is a diagram comparing the fluctuation amounts of the interface state density and the flat band voltage.
【図４】フラッシュ型不揮発性メモリセルの要部の断面
構造を示す図。FIG. 4 is a diagram showing a cross-sectional structure of a main part of a flash nonvolatile memory cell.
【図５】本発明におけるゲ−ト絶縁膜中の窒素の膜厚方
向の濃度分布を示す図。FIG. 5 is a diagram showing the concentration distribution of nitrogen in the gate insulating film in the thickness direction of the present invention.
【図６】ゲ−ト絶縁膜を形成する際の、各種ガスの添加
の１例を示す流れ図。FIG. 6 is a flowchart showing an example of addition of various gases when forming a gate insulating film.
【図７】ゲ−ト絶縁膜中の窒素濃度分布の測定例を示す
図。FIG. 7 is a view showing an example of measurement of nitrogen concentration distribution in a gate insulating film.
【図８】ゲート絶縁膜中における窒素添加層の数と特性
の関係を示す図。FIG. 8 is a diagram showing a relationship between the number of nitrogen-added layers in a gate insulating film and characteristics.
【図９】ゲ−ト絶縁膜を形成する際の、各種ガスの添加
の１例を示す流れ図。FIG. 9 is a flow chart showing an example of adding various gases when forming a gate insulating film.
【図１０】ｐｏｌｙ−ＳｉＭＯＳＦＥＴの断面構造を示
す図。FIG. 10 is a diagram showing a cross-sectional structure of a poly-Si MOSFET.
１１……シリコン基板 １２……素子分離絶縁膜 １３……拡散層 １４……金属配線 １５……ゲ−ト電極 １６……ゲ−ト絶縁膜 ２４……浮遊ゲ−ト電極 ２５……制御ゲ−ト電極 ２６……本発明による絶縁膜 ３４……多結晶シリコン膜 ３８……ゲート絶縁膜 ３９……ゲート電極。 11 ... Silicon substrate 12 ... Element isolation insulating film 13 ... Diffusion layer 14 ... Metal wiring 15 ... Gate electrode 16 ... Gate insulating film 24 ... Floating gate electrode 25 ... Control gate -G electrode 26 ... Insulating film 34 according to the present invention ... Polycrystalline silicon film 38 ... Gate insulating film 39 ... Gate electrode
Claims (11)
内に所定の間隔を介して配置された上記第１導電型とは
逆の第２導電型を有するソース領域およびドレイン領域
と、当該ソース領域およびドレイン領域の間に介在する
領域上の上記半導体基板の主表面上に形成されたゲート
絶縁膜および当該ゲート絶縁膜上に形成された電極を少
なくとも具備し、上記ゲ−ト絶縁膜には不純物が添加さ
れており、当該不純物の濃度は、上記ゲ−ト絶縁膜の厚
さ方向に周期的に変化していることを特徴とする半導体
装置。1. A source region and a drain region having a second conductivity type opposite to the first conductivity type arranged at a predetermined distance in a surface region of a semiconductor substrate having the first conductivity type, and The gate insulating film includes at least a gate insulating film formed on the main surface of the semiconductor substrate on a region interposed between the source region and the drain region, and an electrode formed on the gate insulating film. Is added with an impurity, and the concentration of the impurity is periodically changed in the thickness direction of the gate insulating film.
ることを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the gate insulating film is a silicon oxide film.
ん、砒素、硼素、アルミニウム、炭素、ガリウムおよび
ゲルマニウムからなる群から選択された少なくとも１種
であることを特徴とする請求項１若しくは２記載の半導
体装置。3. The impurity according to claim 1, wherein the impurities are at least one selected from the group consisting of nitrogen, fluorine, chlorine, phosphorus, arsenic, boron, aluminum, carbon, gallium and germanium. The semiconductor device described.
の厚さ方向に、上記不純物の濃度のピークが複数個形成
され、当該ピークの数は２以上１０以下であることを特
徴とする請求項１から３のいずれかに記載の半導体装
置。4. A plurality of peaks of the concentration of the impurity are formed in the gate insulating film in the thickness direction of the gate insulating film, and the number of the peaks is 2 or more and 10 or less. The semiconductor device according to claim 1.
ほぼ１原子パーセントであることを特徴とする請求項４
記載の半導体装置。5. The concentration of the impurities in the peak is
5. An amount of approximately 1 atomic percent.
The semiconductor device described.
の電極が形成されていることを特徴とする請求項１から
５のいずれかに記載の半導体装置。6. A second electrode is formed on the upper surface of the electrode via an insulating film.
6. The semiconductor device according to claim 1, wherein the electrode is formed.
を介して形成された所定の形状を有するゲート電極と、
当該ゲート電極の上に形成されたゲート絶縁膜と、当該
ゲート絶縁膜上に形成された多結晶シリコン膜と、当該
多結晶シリコン膜の両端とそれぞれ接続されたソース・
ドレイン領域を具備し、上記ゲ−ト絶縁膜には不純物が
添加されており、当該不純物の濃度は、上記ゲ−ト絶縁
膜の厚さ方向に周期的に変化していることを特徴とする
半導体装置。7. A semiconductor substrate, and a gate electrode formed on the semiconductor substrate via an insulating film and having a predetermined shape,
A gate insulating film formed on the gate electrode, a polycrystalline silicon film formed on the gate insulating film, and a source connected to both ends of the polycrystalline silicon film.
An impurity is added to the gate insulating film, which has a drain region, and a concentration of the impurity is periodically changed in a thickness direction of the gate insulating film. Semiconductor device.
スを間歇的に添加しながら、シリコンを成分元素として
含有する原料ガスと酸化性ガスを接触させることによ
り、濃度のピークが厚さ方向に周期的に分布された上記
不純物を含有する酸化シリコン膜を形成する工程を含む
ことを特徴とする半導体装置の製造方法。8. A concentration peak in the thickness direction is obtained by bringing a source gas containing silicon as a component element into contact with an oxidizing gas while intermittently adding a gas containing a predetermined impurity as a component element. A method of manufacturing a semiconductor device, comprising the step of forming a silicon oxide film containing the above impurities distributed periodically.
ｌ2であり、上記酸化性ガスはＮ2Ｏであることを特徴と
する請求項８記載の半導体装置の製造方法。9. The source gas is SiH 4 or SiH 2 C
9. The method for manufacturing a semiconductor device according to claim 8, wherein the oxidizing gas is L 2 and the oxidizing gas is N 2 O.
スは、ＮＨ3、ＣＨ4，ＮＦ3，Ｃｌ2，ＨＣｌ，Ｃｌ
Ｆ3，ＨＦ，ＰＨ3，ＡｓＨ3，Ｂ2Ｈ6，ＧｅＨ4、ジメチ
ルアルミハイドライド（（ＣＨ3）2ＡｌＨ），トリイソ
ブチルアルミニウム（（Ｃ4Ｈ9）3Ａｌ）およびトリメ
チルガリウム（（ＣＨ3）3Ｇａ）からなる群から選択さ
れた少なくとも１種であることを特徴とする請求項８若
しくは９記載の半導体装置の製造方法。10. The gas containing the impurities as component elements is NH 3 , CH 4 , NF 3 , Cl 2 , HCl, Cl.
F 3, HF, PH 3, AsH 3, B 2 H 6, GeH 4, dimethyl aluminum hydride ((CH 3) 2 AlH) , triisobutylaluminum ((C 4 H 9) 3 Al) and trimethyl gallium ((CH 3 ) The method for manufacturing a semiconductor device according to claim 8 or 9, wherein the method is at least one selected from the group consisting of 3 Ga 3 ).
スを間歇的に添加し、各添加の後ごとに、上記原料ガス
および酸化性ガスの温度をそれぞれ上昇させることを特
徴とする請求項８から１０のいずれかに記載の半導体装
置の製造方法。11. The method according to claim 8, wherein a gas containing the impurity as a constituent element is intermittently added, and the temperature of the raw material gas and the temperature of the oxidizing gas are raised after each addition. 11. The method for manufacturing a semiconductor device according to any one of 10.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4319624A JPH06169083A (en) | 1992-11-30 | 1992-11-30 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4319624A JPH06169083A (en) | 1992-11-30 | 1992-11-30 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06169083A true JPH06169083A (en) | 1994-06-14 |
Family
ID=18112362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4319624A Pending JPH06169083A (en) | 1992-11-30 | 1992-11-30 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06169083A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6693324B2 (en) | 1996-04-26 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a thin film transistor and manufacturing method thereof |
| JP2005505920A (en) * | 2001-10-02 | 2005-02-24 | エーエスエム アメリカ インコーポレイテッド | Nitrogen incorporation into high-k dielectric films |
| US6906391B2 (en) | 2002-06-12 | 2005-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device having silicon oxide film |
| JP2010062387A (en) * | 2008-09-04 | 2010-03-18 | Toshiba Corp | Nonvolatile semiconductor storage device |
| JP2010098322A (en) * | 2004-02-10 | 2010-04-30 | Seiko Epson Corp | Insulating film, semiconductor element, electronic device and electronic apparatus |
| JP2010239120A (en) * | 2009-03-09 | 2010-10-21 | Semiconductor Energy Lab Co Ltd | Thin film transistor |
-
1992
- 1992-11-30 JP JP4319624A patent/JPH06169083A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6693324B2 (en) | 1996-04-26 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a thin film transistor and manufacturing method thereof |
| JP2005505920A (en) * | 2001-10-02 | 2005-02-24 | エーエスエム アメリカ インコーポレイテッド | Nitrogen incorporation into high-k dielectric films |
| US6906391B2 (en) | 2002-06-12 | 2005-06-14 | Sanyo Electric Co., Ltd. | Semiconductor device having silicon oxide film |
| JP2010098322A (en) * | 2004-02-10 | 2010-04-30 | Seiko Epson Corp | Insulating film, semiconductor element, electronic device and electronic apparatus |
| JP2010062387A (en) * | 2008-09-04 | 2010-03-18 | Toshiba Corp | Nonvolatile semiconductor storage device |
| JP2010239120A (en) * | 2009-03-09 | 2010-10-21 | Semiconductor Energy Lab Co Ltd | Thin film transistor |
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