JPH06169031A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH06169031A JPH06169031A JP5213738A JP21373893A JPH06169031A JP H06169031 A JPH06169031 A JP H06169031A JP 5213738 A JP5213738 A JP 5213738A JP 21373893 A JP21373893 A JP 21373893A JP H06169031 A JPH06169031 A JP H06169031A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- opening
- chip
- board
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＳｉ基板上に多数のＳｉ
半導体のＬＳＩ（大規模集積回路）を搭載した半導体装
置及びその製造方法に関する。BACKGROUND OF THE INVENTION The present invention relates to a large number of Sis on a Si substrate.
The present invention relates to a semiconductor device mounted with a semiconductor LSI (Large Scale Integrated Circuit) and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来ＩＣ（集積回路）チップは一個ずつ
パッケージングしてＤＩＬ（Dual inLine）のピンをと
り出し、エポキシのプリント基板に搭載する方式がとら
れてきた。この方法ではＩＣチップの面積に比べパッケ
ージングの占める面積が大きくＩＣ実装の高密度化に限
界があった。最近この問題を回避してＩＣチップ実装の
高密度化をはかるためにセラミックの多層基板にＩＣチ
ップを直接接続する方式が用いられるようになってきて
いる。このセラミック基板実装法においては、ＩＣチッ
プとセラミック基板との電気的接続には通常はんだの小
球を用いるＣＣＢ（Controlｌed Collapse Bonding）法
が用いられている。2. Description of the Related Art Conventionally, IC (integrated circuit) chips have been packaged one by one to take out DIL (Dual in Line) pins and mount them on an epoxy printed circuit board. In this method, the area occupied by the packaging is larger than the area of the IC chip, and there is a limit to the high density of the IC packaging. Recently, in order to avoid this problem and increase the density of IC chip mounting, a method of directly connecting the IC chip to a ceramic multilayer substrate has been used. In this ceramic substrate mounting method, a CCB (Controlled Collapse Bonding) method using solder balls is usually used for electrical connection between the IC chip and the ceramic substrate.
【０００３】[0003]
【発明が解決しようとする課題】上記従来のはんだ接続
技術においてはチップに用いるＳｉと基板に用いるアル
ミナと熱膨張係数の差のために接続はんだ小球に大きな
応力が働き、接続部が破断しやすいという問題がある。
この傾向はチップの面積を大きくしたり、はんだ小球の
直径を小さくすると激しくなり、チップの大面積化およ
び接続ピンの多ピン化を妨げ、ひいてはチップの高集積
化を妨げる要因となっていた。さらに、基板の反りが問
題となっていた。In the above-mentioned conventional solder connection technique, a large stress is exerted on the connection solder globules due to the difference in thermal expansion coefficient between Si used for the chip and alumina used for the substrate, and the connection portion is broken. There is a problem that it is easy.
This tendency became more serious as the area of the chip was increased or the diameter of the solder balls was decreased, which hindered the increase in the area of the chip and the increase in the number of connection pins, which in turn impeded the high integration of the chip. . Further, the warp of the substrate has been a problem.
【０００４】本発明の目的は上記欠点のない半導体装置
及びその製造方法を提供することにある。An object of the present invention is to provide a semiconductor device and a method of manufacturing the same which do not have the above-mentioned drawbacks.
【０００５】[0005]
【課題を解決するための手段】上記目的は、基板材料と
してチップと同じＳｉを用い、Ｓｉ基板の表裏両面にほ
ぼ同一の膜厚を有する絶縁膜を形成し、さらに多層配線
を実現させるための絶縁膜としてポリイミド等の比較的
軟かいポリマーを用い、前記配線とチップとをＣＣＢ接
続することによって達成される。The above object is to realize the multilayer wiring by using the same Si as the chip as the substrate material and forming the insulating films having substantially the same film thickness on both the front and back surfaces of the Si substrate. This is achieved by using a relatively soft polymer such as polyimide as the insulating film and connecting the wiring and the chip by CCB.
【０００６】[0006]
【作用】基板材料としてチップと同じＳｉを用いること
により、ＩＣチップと基板材料との熱膨張係数の差をな
くすことができ、絶縁膜としてポリイミド等の比較的軟
かいポリマーを用いることにより、チップと基板との接
続部における応力集中が防止される。さらに、チップの
動作中に発生する熱が基板に伝わり、チップを搭載した
基板の面がその裏面より熱膨張することにより反りが生
じるが、基板の表裏にほぼ同一の膜厚を有する絶縁膜を
設けることにより、この反りを解消できる。By using the same Si as the chip as the substrate material, the difference in the coefficient of thermal expansion between the IC chip and the substrate material can be eliminated, and by using a relatively soft polymer such as polyimide as the insulating film, the chip The stress concentration at the connection between the substrate and the substrate is prevented. Furthermore, the heat generated during the operation of the chip is transferred to the substrate, and the surface of the substrate on which the chip is mounted thermally expands from the back surface of the substrate to cause warpage, but an insulating film having almost the same thickness is formed on the front and back surfaces of the substrate. By providing it, this warp can be eliminated.
【０００７】なお、基板のポリマーは通常Ｓｉよりも熱
膨張係数が大きいが膜厚が薄いので、Ｓｉ板上に形成し
たポリマー膜の熱膨張の挙動はＳｉのそれにほぼ追従す
る。したがって、Ｓｉ基板上に形成したポリマー膜上の
配線にはんだボールを用いてＳｉチップを電気的に接続
したときには熱膨張を原因とする接続部の破断はほぼな
くなる。そのためチップの大面積化および接続ピンの高
密度多ピン化が容易となる。Since the polymer of the substrate usually has a larger coefficient of thermal expansion than Si but has a small film thickness, the thermal expansion behavior of the polymer film formed on the Si plate substantially follows that of Si. Therefore, when the Si chip is electrically connected to the wiring on the polymer film formed on the Si substrate by using the solder ball, the breakage of the connection portion due to the thermal expansion is almost eliminated. Therefore, it is easy to increase the chip area and increase the density and number of connection pins.
【０００８】以下図面を参照しなから、実施例を用いて
本発明を具体的に説明する。The present invention will be described in detail below with reference to the accompanying drawings with reference to the accompanying drawings.
【０００９】[0009]
【実施例】図１ａに示すように基板１として厚さ２ｍｍ
のシリコン板を用いた。これにレーザ又は電子ビームを
用いて直径１ｍｍのスルーホール１１をあけた。次に図
１ｂに示すように、上記基板１に酸化処理をほどこし
て、ＳｉＯ2の被膜２を基板表面およびスルーホール１
１内部に形成した。次いで、スルーホール内に導体ペー
スト３を充填し乾燥固化し、平坦化処理をほどこした。
つぎに図１ｃに示すように、ポリイミドイソンドロキナ
ゾリンジオン（ポリイミドの一種で、以下ＰＩＫと略称
する）をスピンコートにより被着させ、１０μｍのＰＩ
Ｋ膜４を形成した。ＰＩＫ膜の所定の箇所にスルーホー
ルをあけアルミニューム配線５を施こした。さらに図１
ｄに示すように、ＰＩＫ膜形成、スルーホール孔あけ、
アルミニウム配線工程を繰返して第二配線層５１を形成
した。第二配線層の上面にあるアルミ配線部の接続パッ
ドに必要な表面処理を行なった。接続パッドにシリコン
ＩＣチップ６をＣＣＢ接続する。EXAMPLE A substrate 1 having a thickness of 2 mm as shown in FIG. 1a
The silicon plate of was used. A through hole 11 having a diameter of 1 mm was formed in this using a laser or an electron beam. Next, as shown in FIG. 1b, the substrate 1 is subjected to an oxidation treatment to form a SiO 2 film 2 on the substrate surface and through holes 1.
1 formed inside. Next, the conductor paste 3 was filled in the through holes, dried and solidified, and subjected to a flattening treatment.
Next, as shown in FIG. 1c, a polyimide insondroquinazolinedione (a kind of polyimide, abbreviated as PIK hereinafter) is applied by spin coating, and a PI of 10 μm is deposited.
The K film 4 was formed. Through holes were opened at predetermined positions of the PIK film and aluminum wiring 5 was applied. Furthermore, FIG.
As shown in d, PIK film formation, through hole drilling,
The aluminum wiring process was repeated to form the second wiring layer 51. The surface treatment required for the connection pad of the aluminum wiring portion on the upper surface of the second wiring layer was performed. The silicon IC chip 6 is CCB-connected to the connection pad.
【００１０】[0010]
【発明の効果】以上説明したごとく本発明によればシリ
コンチップと配線基板との熱膨張の差を非常に小さくす
ることができる。そのため両者の接続部に働く応力を小
さくすることができ配線基板の信頼性を著しく高めるこ
とができる。また上記両者の中間に比較的軟かいポリマ
ー絶縁膜を配置するので配線の多層化が容易である。そ
のため多数のＩＣチップを一枚の配線基板に搭載するこ
とも容易となった。さらに、基板の反りを解消すること
ができた。As described above, according to the present invention, the difference in thermal expansion between the silicon chip and the wiring board can be made very small. Therefore, the stress acting on the connecting portion between the two can be reduced, and the reliability of the wiring board can be significantly improved. Further, since a relatively soft polymer insulating film is arranged between the two, it is easy to form a multilayer wiring. Therefore, it becomes easy to mount many IC chips on one wiring board. Furthermore, the warp of the substrate could be eliminated.
【図１】本発明の一実施例としての半導体実装基板の構
造とその製造工程の概略を示した説明図である。FIG. 1 is an explanatory view showing an outline of a structure of a semiconductor mounting substrate and a manufacturing process thereof as one embodiment of the present invention.
１…Ｓｉ基板、１１…スルーホール、２…酸化膜、３…
導体ペースト、４…高分子樹脂層、５および５１…Ａｌ
配線層、６…シリコンＩＣチップ。1 ... Si substrate, 11 ... Through hole, 2 ... Oxide film, 3 ...
Conductor paste, 4 ... Polymer resin layer, 5 and 51 ... Al
Wiring layer, 6 ... Silicon IC chip.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 9355−4Ｍ Ｈ０１Ｌ 23/14 Ｒ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 9355-4M H01L 23/14 R
Claims (6)
び裏面に形成された絶縁膜と、前記絶縁膜上に形成さ
れ、第１の開孔部を有する第１の軟質ポリマー層と、前
記第１の開孔部の底面、側面及び前記第１の軟質ポリマ
ー層上に延伸して形成され、かつ前記第１の開孔部の中
央部分には充填されていない第１の配線と、前記第１の
開孔部とは異なる箇所において前記第１の配線と半田で
電気的に接続されたＩＣチップとを有し、前記半導体基
板と前記ＩＣチップとは同じ材料からなることを特徴と
する半導体装置。1. A semiconductor substrate, an insulating film formed on a main surface and a back surface of the semiconductor substrate, a first soft polymer layer formed on the insulating film and having a first opening, and A first wiring that is formed by extending on the bottom surface and the side surface of the first opening and the first soft polymer layer and is not filled in the central portion of the first opening; An IC chip electrically connected to the first wiring with solder at a position different from the first opening, and the semiconductor substrate and the IC chip are made of the same material. Semiconductor device.
に、前記絶縁膜と前記第１の軟質ポリマー層との間に、
第２の開孔部を有する第２の軟質ポリマー層と前記第２
の開孔部の底面、側面及び前記第２の軟質ポリマー層上
に延伸して形成され、かつ前記第２の開孔部の中央部分
には充填されていない第２の配線とを有しており、前記
第２の配線は前記第１の配線と前記第１の開孔部を通じ
て接続されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, further comprising: between the insulating film and the first soft polymer layer,
A second soft polymer layer having a second aperture and the second
A bottom surface, a side surface of the opening and a second wiring which is formed by extending on the second soft polymer layer and which is not filled in the central portion of the second opening. The semiconductor device is characterized in that the second wiring is connected to the first wiring through the first opening.
に、前記半導体基板は、前記半導体基板の表裏を貫いて
形成されたスルーホールと、前記スルーホールの表面に
設けられた絶縁膜と、前記スルーホールに充填された導
体ペーストとを有し、前記スルーホール上に前記第２の
開孔部が形成されていることを特徴とする半導体装置。3. The semiconductor device according to claim 2, further comprising: a through hole formed in the semiconductor substrate through the front and back surfaces of the semiconductor substrate; an insulating film provided on the surface of the through hole; A conductive paste filled in a through hole, wherein the second opening portion is formed on the through hole.
おいて、前記軟質ポリマーは、ポリイミドであることを
特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the soft polymer is polyimide.
おいて、前記半導体基板は、シリコン基板であることを
特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein the semiconductor substrate is a silicon substrate.
成する工程と、前記絶縁膜上に開孔部を有する軟質ポリ
マー層を形成する工程と、前記開孔部の底面、側面及び
前記軟質ポリマー層上に延伸し、かつ前記開孔部の中央
部分には充填されていない配線を形成する工程と、前記
開孔部とは異なる箇所において前記配線と、前記半導体
基板と同じ材料からなるＩＣチップとを半田で電気的に
接続する工程を有することを特徴とする半導体装置の製
造方法。6. A step of forming an insulating film on a main surface and a back surface of a semiconductor substrate, a step of forming a soft polymer layer having an opening portion on the insulating film, a bottom surface, a side surface of the opening portion, and A step of forming a wiring that is not filled in the central portion of the opening portion and extending on the soft polymer layer, and the wiring in a portion different from the opening portion, and made of the same material as the semiconductor substrate A method of manufacturing a semiconductor device, comprising a step of electrically connecting to an IC chip with solder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5213738A JPH0810738B2 (en) | 1993-08-30 | 1993-08-30 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5213738A JPH0810738B2 (en) | 1993-08-30 | 1993-08-30 | Semiconductor device and manufacturing method thereof |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP758882A Division JPS58125859A (en) | 1982-01-22 | 1982-01-22 | Substrate for mounting of semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06169031A true JPH06169031A (en) | 1994-06-14 |
| JPH0810738B2 JPH0810738B2 (en) | 1996-01-31 |
Family
ID=16644197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5213738A Expired - Lifetime JPH0810738B2 (en) | 1993-08-30 | 1993-08-30 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0810738B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282072A (en) * | 2003-03-14 | 2004-10-07 | General Electric Co <Ge> | Interposer, interposer package, and device assembly employing the same |
| JP2009004507A (en) * | 2007-06-20 | 2009-01-08 | Shinko Electric Ind Co Ltd | Package for electronic component, manufacturing method thereof, and electronic component device |
| US7528476B2 (en) | 2004-12-21 | 2009-05-05 | Seiko Epson Corporation | Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument |
| JP2011082531A (en) * | 2008-12-26 | 2011-04-21 | Dainippon Printing Co Ltd | Through-hole electrode substrate, and method of manufacturing the same |
| US8198726B2 (en) | 2008-12-26 | 2012-06-12 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5473564A (en) * | 1977-11-24 | 1979-06-12 | Hitachi Ltd | Circuit device |
-
1993
- 1993-08-30 JP JP5213738A patent/JPH0810738B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5473564A (en) * | 1977-11-24 | 1979-06-12 | Hitachi Ltd | Circuit device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004282072A (en) * | 2003-03-14 | 2004-10-07 | General Electric Co <Ge> | Interposer, interposer package, and device assembly employing the same |
| US7528476B2 (en) | 2004-12-21 | 2009-05-05 | Seiko Epson Corporation | Semiconductor device, method for manufacturing semiconductor device, circuit board, and electronic instrument |
| JP2009004507A (en) * | 2007-06-20 | 2009-01-08 | Shinko Electric Ind Co Ltd | Package for electronic component, manufacturing method thereof, and electronic component device |
| US8129830B2 (en) | 2007-06-20 | 2012-03-06 | Shinko Electric Industries Co., Ltd. | Electronic component package and method of manufacturing the same, and electronic component device |
| EP2586742A1 (en) | 2007-06-20 | 2013-05-01 | Shinko Electric Industries Co., Ltd. | Electronic component package and method of manufacturing the same |
| EP2666745A1 (en) | 2007-06-20 | 2013-11-27 | Shinko Electric Industries Co., Ltd. | Electronic component package and method of manufacturing the same, and electronic component device |
| JP2011082531A (en) * | 2008-12-26 | 2011-04-21 | Dainippon Printing Co Ltd | Through-hole electrode substrate, and method of manufacturing the same |
| US8198726B2 (en) | 2008-12-26 | 2012-06-12 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
| US8623751B2 (en) | 2008-12-26 | 2014-01-07 | Dai Nippon Printing Co., Ltd. | Through-hole electrode substrate and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0810738B2 (en) | 1996-01-31 |
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