JPH06163634A - Method of installation of flip chip semiconductor device - Google Patents

Method of installation of flip chip semiconductor device

Info

Publication number
JPH06163634A
JPH06163634A JP22369392A JP22369392A JPH06163634A JP H06163634 A JPH06163634 A JP H06163634A JP 22369392 A JP22369392 A JP 22369392A JP 22369392 A JP22369392 A JP 22369392A JP H06163634 A JPH06163634 A JP H06163634A
Authority
JP
Japan
Prior art keywords
solder
block
circuit board
semiconductor device
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22369392A
Other languages
Japanese (ja)
Other versions
JPH0779152B2 (en
Inventor
Teruo Kusaka
輝雄 日下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22369392A priority Critical patent/JPH0779152B2/en
Publication of JPH06163634A publication Critical patent/JPH06163634A/en
Publication of JPH0779152B2 publication Critical patent/JPH0779152B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7565—Means for transporting the components to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Abstract

PURPOSE:To prevent noxious impurities from contacting with the surface of a chip by temporarily fixing the rear side of a semiconductor chip and the flat face of a block with each other, and making the block and the substrate abut on each other not through solder flux, and fusing the solder of a solder bump electrode by heating thereby fusing them together. CONSTITUTION:The rear sides 14 of a plurality of semiconductor chips 4, where solder bump electrodes 15 are formed on the surface sides, are temporarily fixed in the specified positions of the flat face of a block 21 by adhesives 2. Next, the flat face of a block 1 is opposed to the surface 22 of a circuit board 7 where a pad 8 is made, and the block 1 an the circuit board 2 are positioned, and both are brought close to each other. Next, the solder bump electrode 15 and the pad 8 are abutted not through solder flux, and a solder bump electrode 15 is fused together to the pad 8 by reflowing the solder of the solder bump electrode 15, thus a plurality of semiconductor chips are connected en block to the circuit board. Hereby, the reliability and the yield rate can be improved by eliminating noxious matter contained in the solder flux.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明はフリップチップ型半導体
装置の実装方法に係わり、特に半導体チップの電極を半
田付けにより回路基板に接続する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a flip chip type semiconductor device, and more particularly to a method for connecting electrodes of a semiconductor chip to a circuit board by soldering.

【０００２】[0002]

【従来の技術】半導体チップの表面に形成された複数の
半田バンプ電極を回路基板の配線パターンに直接接続す
るフリップチップ型半導体装置は、高密度実装が可能で
ありかつ高い信頼性が得られることからＬＳＩの分野で
広く普及されており、例えば、日本金属学会会報第２３
巻第１２号（１９８４）の１００４頁乃至１０１３頁に
「ＩＣ・ＬＳＩの微細はんだ接続技術」と題して佐藤等
によってこの技術が説明されている。2. Description of the Related Art A flip-chip type semiconductor device in which a plurality of solder bump electrodes formed on the surface of a semiconductor chip is directly connected to a wiring pattern of a circuit board is capable of high-density mounting and high reliability. Widely used in the field of LSI from, for example, the Japan Institute of Metals, No. 23
Volume 12 (1984), pages 1004 to 1013, describes this technology by Sato et al., Entitled "IC / LSI Fine Solder Connection Technology".

【０００３】従来技術においては、配線パターンが形成
された回路基板上に半田フラックスを塗布し、半導体チ
ップの半田バンプ電極を配線パターンのパッドに位置合
せし半田フラックスで接着した後、加熱して半田を溶融
（以下リフローと称す）することにより半田付け接続が
行われる。ここで、半田フラックスはリフローを円滑に
行う作用の他に、その接着力を利用して位置合せした半
導体チップを仮止め接着するという大切な作用を有して
いる。In the prior art, solder flux is applied on a circuit board on which a wiring pattern is formed, the solder bump electrodes of a semiconductor chip are aligned with the pads of the wiring pattern and bonded with solder flux, and then heated and soldered. Are melted (hereinafter referred to as reflow) to perform soldering connection. Here, the solder flux has an important function of temporarily re-bonding the semiconductor chips aligned by utilizing the adhesive force, in addition to the function of smoothly performing the reflow.

【０００４】一方、ＬＳＩの高度化にともないフリップ
チップ型半導体装置の半導体チップからの放熱が重要な
課題となり、このために半導体チップの裏面に放熱手段
を設けることが必要となる。この放熱方法の一つとして
Ｒａｏ Ｒ．Ｔｕｍｍａｌａは、ＩＭＣ １９８８ Ｐ
ｒｏｃｅｅｄｉｎｇｓ，Ｔｏｋｙｏ，Ｍａｙ２５−２
７，１９８８の予稿集の１２頁乃至１７頁に「ＡＤＶＡ
ＮＣＥ ＰＡＣＫＡＧＩＮＧ ＴＥＣＨＮＯＬＯＧＩＥ
Ｓ ＩＮ Ｕ．Ｓ．−ＡＮ ＯＶＥＲＶＩＥＷ」と題す
る論文を発表しそこで、冷却ピストンを一個の半導体チ
ップの裏面にバネで機械的に押しつける構造を提示して
いる。また、Ｒ．Ｄａｒｖｅａｕｘ等は、放熱器を一定
の厚さのインジウムを介して複数の半導体チップの裏面
に共通に取り付ける方法を、Ｐｒｏｃ．ｏｆ ｔｈｅ
３９ ｔｈ ＥｌｅｃｔｒｏｎｉｃＣｏｍｐｏｎｅｎｔ
ｓ Ｃｏｎｆｅｒｅｎｃｅ，１９８９，Ｍａｙの予稿集
の６６８頁乃至６７１頁の「ＴＨＥＲＭＡＬ／ＳＴＲＥ
ＳＳ ＡＮＡＬＹＳＩＳ ＯＦ Ａ ＭＵＬＴＩＣＨＩ
Ｐ ＰＡＣＫＡＧＥ ＤＥＳＩＧＮ」と題する論文で提
示している。On the other hand, heat dissipation from the semiconductor chip of the flip-chip type semiconductor device becomes an important subject as the sophistication of LSI increases. Therefore, it is necessary to provide a heat dissipation means on the back surface of the semiconductor chip. As one of the heat dissipation methods, Rao R. Tummala is IMC 1988 P
rosecedings, Tokyo, May25-2
7-1988 Proceedings, pages 12-17, "ADVA
NCE PACKAGING TECHNOLOGIE
S IN U. S. -AN OVERVIEW "has been published, which presents a structure in which a cooling piston is mechanically pressed against the backside of a semiconductor chip by a spring. In addition, R. Darveaux et al. Describe a method of commonly mounting a radiator on the back surfaces of a plurality of semiconductor chips via indium having a constant thickness, Proc. of the
39th Electronic Component
s Conference, 1989, May, Proceedings, pp. 668-671, "THERMAL / STRE".
SS ANALYSIS OF A MULTICHI
P PACKAGE DESIGN ”.

【０００５】まず図９を参照して従来技術の実装方法を
説明する。配線パターンが形成された回路基板７上にロ
ジン系の液状半田フラックス１１を塗布し、表面１５側
にトランジスタ等の素子や配線層が形成された半導体チ
ップ４をフェースダウンして矢印の方向に押し、その表
面１５上の半田バンプ電極５を配線パターンのパッド８
に位置合せし半田フラックス１１により仮止めした（図
９（Ａ））後、半田のリフローにより半田ボール１０を
形成して電極とパッドとの接続を行う（図９（Ｂ）。First, a conventional mounting method will be described with reference to FIG. A rosin-based liquid solder flux 11 is applied onto the circuit board 7 on which a wiring pattern is formed, and the semiconductor chip 4 on which elements such as transistors and a wiring layer are formed on the surface 15 side is pressed down in the direction of the arrow. , The solder bump electrode 5 on the surface 15 of the wiring pattern pad 8
After that, the solder flux 11 is temporarily fixed (FIG. 9 (A)), and then the solder balls 10 are formed by reflowing the solder to connect the electrodes to the pads (FIG. 9 (B)).

【０００６】表１に半導体チップにとって有害な不純物
であるＣｌ- およびＮａ+ の含有量の分析結果を示す。Table 1 shows the results of analysis of the contents of Cl − and Na + , which are harmful impurities for semiconductor chips.

【０００７】[0007]

【表１】 [Table 1]

【０００８】同表から明らかのように、半田フラックス
には、半導体チップを構成するポリイミドやパッケージ
ング材のモールド樹脂と比較してはるかに多くの有害不
純物が含有されているから、素子が形成されている表面
１５側が半田フラックス１１に対面する上記方法では、
信頼性や歩留りが低下してしまう。As is clear from the table, the solder flux contains much more harmful impurities than the polyimide constituting the semiconductor chip and the molding resin of the packaging material, so that the element is formed. In the above method in which the surface 15 side facing the solder flux 11 faces,
Reliability and yield will be reduced.

【０００９】また、上記方法では各半導体チップ４の裏
面１４の高さの偏差（ΔＨ）が大きくなる。例えば、縦
列３個横列３個の計９個の半導体チップ４を同一の回路
基板７に搭載し半田接続した場合、半導体チップ間で裏
面１４の最大高さと最小高さの差ΔＨは１００〜１５０
μｍと大きな値となる。したがって、複数の半導体チッ
プの裏面に共通に放熱器を熱抵抗を小にして取り付ける
ことは困難となる。In the above method, the height deviation (ΔH) of the back surface 14 of each semiconductor chip 4 becomes large. For example, when a total of nine semiconductor chips 4 of three columns and three rows are mounted on the same circuit board 7 and connected by soldering, the difference ΔH between the maximum height and the minimum height of the back surface 14 between the semiconductor chips is 100 to 150.
It becomes a large value of μm. Therefore, it is difficult to attach a radiator to the back surface of a plurality of semiconductor chips in common with a small thermal resistance.

【００１０】[0010]

【発明が解決しようとする課題】以上説明したように、
半田フラックスで半導体チップを仮止めする従来技術の
方法は、半田フラックスに含まれる多くの有害な不純物
が半導体チップの表面に接触するために、信頼性上また
歩留り上の問題を発生する。特に半導体チップの高集積
化、微細化が進めば進むほど各材料への有害な不純物低
減が厳しくなることからも、半田フラックスを製造プロ
セスから除去する必要がある。As described above,
The prior art method of temporarily fixing the semiconductor chip with the solder flux causes reliability and yield problems because many harmful impurities contained in the solder flux come into contact with the surface of the semiconductor chip. In particular, it is necessary to remove the solder flux from the manufacturing process because the harmful impurities in each material are more severely reduced as the semiconductor chips are highly integrated and miniaturized.

【００１１】さらに、上記従来技術の方法ではリフロー
後の各半導体チップの裏面が同一平面上に位置せず、複
数の半導体チップの裏面間での高さの偏差が大きくな
る。このために、上記したように放熱経路が長く複雑の
構造の冷却ピストンの冷却手段を半導体チップの一個ご
とに配置せざるをえない。一方、上記した半田材として
のインジウムを厚く（例えば、膜厚５００−８００μ
ｍ）に形成して複数の半導体チップの裏面間の高低差を
相殺して放熱器を共通に取り付ける方法は、放熱器まで
の熱抵抗が大きくなって好ましくない。Further, in the above-mentioned conventional method, the back surfaces of the respective semiconductor chips after the reflow are not located on the same plane, and the height deviation between the back surfaces of the plurality of semiconductor chips becomes large. For this reason, the cooling means of the cooling piston having a long heat dissipation path and a complicated structure as described above must be arranged for each semiconductor chip. On the other hand, the above-mentioned indium as the solder material is thick (for example, the film thickness is 500 to 800 μm).
The method of forming the m) and canceling the height difference between the back surfaces of the plurality of semiconductor chips and mounting the radiator in common is not preferable because the thermal resistance up to the radiator becomes large.

【００１２】[0012]

【課題を解決するための手段】本発明の特徴は、表面側
に半田バンプ電極を形成した複数個の半導体チップの裏
面側をブロックの平坦面の所定位置にそれぞれ、例えば
膜厚５−１０μｍのワックスを接着剤として仮止めする
工程と、複数のパッドを有する配線パターンを表面に形
成した回路基板を用意する工程と、前記ブロックの平坦
面を前記回路基板の表面に対向させて前記ブロックと前
記回路基板とを位置決めし、両者を近付けることにより
前記半田バンプ電極と前記パッドとを半田フラックスを
介することなく当接させ、前記半田バンプ電極の半田を
リフローさせて前記半田バンプ電極を前記パッドに溶着
させこれにより前記複数個の半導体チップを一括して前
記回路基板に接続するフリップチップ型半導装置の実装
方法にある。ここで前記リフローはハロゲンガス雰囲気
で行うことが好ましい。A feature of the present invention is that the back surface side of a plurality of semiconductor chips having solder bump electrodes formed on the front surface side is placed at predetermined positions on the flat surface of the block, for example, with a film thickness of 5-10 μm. A step of temporarily fixing wax as an adhesive; a step of preparing a circuit board having a wiring pattern having a plurality of pads formed on the surface; a step of making the flat surface of the block face the surface of the circuit board; By positioning the circuit board and bringing them close to each other, the solder bump electrode and the pad are brought into contact with each other without passing through solder flux, and the solder of the solder bump electrode is reflowed to weld the solder bump electrode to the pad. Thus, there is provided a method of mounting a flip-chip type semiconductor device in which the plurality of semiconductor chips are collectively connected to the circuit board. Here, the reflow is preferably performed in a halogen gas atmosphere.

【００１３】また、前記半田バンプ電極は高融点半田と
その上の低融点半田とを有し、前記加熱工程は第１の温
度による第１の熱処理工程とこの第１の温度より高い第
２の温度による第２の熱処理工程とを有し、前記第１の
熱処理工程によって前記低融点半田のみを溶融させて局
部的な接着を行ない、かつ前記ブロックを前記半導体チ
ップの裏面より除去し、しかる後に、前記半導体チップ
の裏面を治具の平坦面に載置した状態で前記第２の熱処
理工程を行って前記高融点半田および前記低融点半田を
溶融させて最終的な接着を行なうようにすることができ
る。この場合、前記第１の熱処理工程と前記第２の熱処
理工程との間に、前記半導体チップが局部的に接着され
ている前記回路基板の電気的試験を行なうことが好まし
い。Further, the solder bump electrode has a high melting point solder and a low melting point solder thereon, and the heating step includes a first heat treatment step at a first temperature and a second heat treatment step at a temperature higher than the first temperature. A second heat treatment step according to temperature, wherein only the low melting point solder is melted by the first heat treatment step to perform local adhesion, and the block is removed from the back surface of the semiconductor chip, and thereafter, And performing the second heat treatment step with the back surface of the semiconductor chip placed on the flat surface of the jig to melt the high melting point solder and the low melting point solder for final adhesion. You can In this case, it is preferable to perform an electrical test on the circuit board to which the semiconductor chip is locally bonded between the first heat treatment step and the second heat treatment step.

【００１４】また、ブロックと回路基板との前記位置決
めは、ブロックに位置決め用の貫通孔を形成し回路基板
に位置決め用のパターンを形成して、貫通孔を通してパ
ターンを視ることにより行うことができる。ここで、ブ
ロックを（１００）面のシリコンウェハーで構成し、位
置決め用の貫通孔はこのシリコンウェハーを選択的に異
方性エッチングして形成してもよい。The positioning of the block and the circuit board can be performed by forming a positioning through hole in the block, forming a positioning pattern on the circuit board, and viewing the pattern through the through hole. . Here, the block may be composed of a (100) plane silicon wafer, and the through holes for positioning may be formed by selectively anisotropically etching this silicon wafer.

【００１５】[0015]

【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.

【００１６】図１および図２を参照して本発明の第１の
実施例の実装方法を説明する。A mounting method according to the first embodiment of the present invention will be described with reference to FIGS.

【００１７】まず、図１（Ａ）に示すように、一辺が４
０〜１００ｍｍの四角平面形状で厚さ３〜５ｍｍのステ
ンレスのブロック１の平滑に仕上げた表面２１上にアル
コール系等の溶剤により溶解するワックス２を膜厚５〜
１０μｍに塗布する。またこのブロック１の周辺部の４
箇所のそれぞれに後で回路基板との位置決めのために使
用する貫通孔３が形成されている。First, as shown in FIG. 1A, one side is 4
A wax 2 dissolved in a solvent such as an alcohol is formed on a smooth surface 21 of a stainless block 1 having a square plane shape of 0 to 100 mm and a thickness of 3 to 5 mm.
Apply to 10 μm. In addition, 4 of the peripheral part of this block 1
A through hole 3 is formed at each of the locations, which will be used later for positioning with the circuit board.

【００１８】次に、図１（Ｂ）に示すように、半導体素
子、配線等が設けられている表面１５側に半田バンプ電
極５を形成した複数個の半導体チップ４の裏面１４側を
下にし矢印の方向に移動させて、それぞれブロック１の
平滑表面２１の所定位置においてワックス２により半導
体チップ４をその裏面１４側で接着固定する。この実施
例の半田バンプ電極５は、鉛−錫を半田メッキにより平
面形状が一辺１００〜２００μｍの正四角形で高さが５
０〜１５０μｍに形成したものである。Next, as shown in FIG. 1B, the back surface 14 side of the plurality of semiconductor chips 4 having the solder bump electrodes 5 formed on the front surface 15 side on which semiconductor elements, wirings, etc. are provided is faced down. The semiconductor chip 4 is moved in the direction of the arrow and bonded and fixed on the back surface 14 side of the semiconductor chip 4 with the wax 2 at a predetermined position on the smooth surface 21 of the block 1. The solder bump electrode 5 of this embodiment is a regular square having a side of 100 to 200 μm and a height of 5 by lead-tin solder plating.
It is formed to a thickness of 0 to 150 μm.

【００１９】次に、図１（Ｃ）に示すように、ボンダー
のステージ６上に回路基板７を載置する。回路基板７
は、一辺が３０〜１００ｍｍの四角平面形状で厚さが
０．５〜２．０ｍｍのシリコンから構成され、その表面
２２上にはポリイミド膜と銅、金、アルミニウム等の金
属膜からなる多層配線パターンが形成されそこにボンデ
ィングパッド８が接続形成されている。ボンディングパ
ッド８の平面積は半田バンプ電極５の平面積にマージン
を加えた大きさであり、銅メッキにより、５〜６μｍの
膜厚に表面２２上の位置合せマーク９と同時に形成す
る。そして、ブロック１の平滑表面２１と回路基板７の
表面２２を対向配置させ、顕微鏡により貫通孔３を通し
て位置合せマーク９を視てブロック１と回路基板７との
位置定めを行う。Next, as shown in FIG. 1C, the circuit board 7 is placed on the stage 6 of the bonder. Circuit board 7
Is made of silicon having a square planar shape with one side of 30 to 100 mm and a thickness of 0.5 to 2.0 mm, and on the surface 22 thereof, a multi-layer wiring formed of a polyimide film and a metal film of copper, gold, aluminum or the like. A pattern is formed and the bonding pad 8 is connected and formed there. The plane area of the bonding pad 8 is the plane area of the solder bump electrode 5 with a margin added, and is formed simultaneously with the alignment mark 9 on the surface 22 by copper plating to a thickness of 5 to 6 μm. Then, the smooth surface 21 of the block 1 and the surface 22 of the circuit board 7 are opposed to each other, and the block 1 and the circuit board 7 are positioned by observing the alignment mark 9 through the through hole 3 with a microscope.

【００２０】その後、ブロック１を垂直に下降させて複
数のバンプ電極５と複数のパッド８とをそれぞれ当接す
る。本発明では半田フラックスが存在しないのでリフロ
ーを円滑に行うために２００〜３００℃の温度でハロゲ
ンを含んだ不活性ガス雰囲気の熱処理炉で半田リフロー
を行う。半田バンプ５は溶融した際に表面張力により半
田ボール１０となってバンプ電極がパッドに溶着され
る。冷却後、接着剤２をアルコール系の溶剤で洗浄除去
してブロック１を複数の半導体チップ４の裏面１４から
取りはずす（図２（Ａ））。Thereafter, the block 1 is vertically lowered to bring the plurality of bump electrodes 5 and the plurality of pads 8 into contact with each other. In the present invention, since solder flux does not exist, the solder reflow is performed in a heat treatment furnace in an inert gas atmosphere containing halogen at a temperature of 200 to 300 ° C. in order to smoothly perform the reflow. When the solder bumps 5 are melted, they become solder balls 10 due to the surface tension, and the bump electrodes are welded to the pads. After cooling, the adhesive 2 is washed and removed with an alcoholic solvent to remove the block 1 from the back surface 14 of the plurality of semiconductor chips 4 (FIG. 2A).

【００２１】尚、ハロゲンガス雰囲気による半田リフロ
ー自体に関しては、Ｐ．Ａ．Ｍｏｓｋｏｗｉｔｚ等が
Ｊ．Ｖａｃ．Ｓｃｌ．Ｔｅｃｈｎｏｌ．Ａ４（３），Ｍ
ａｙ／Ｊｕｎｅ １９８６，ｐｐ．８３８−８４０に
「Ｔｈｅｒｍａｌ ｄｒｙ ｐｒｏｃｅｓｓ ｓｏｌｄ
ｅｒｉｎｇ」と題する論文で発表している。Regarding solder reflow itself in a halogen gas atmosphere, see P. A. Moskowitz et al. Vac. Scl. Technol. A4 (3), M
ay / June 1986, pp. 838-840, "Thermal dry process sold
ering ”.

【００２２】次に、図２（Ｂ）に示すように、露出した
半導体チップの裏面１４にサーマルグリース１８、例え
ば高熱伝導性シリコーン（エラストマータイプ）を介し
て放熱器１９を取付ける。本実施例ではブロック１の平
坦面２１により、各半導体チップ４の裏面１４の高さの
偏差（ΔＨ）は小さい値となる。例えば、縦列３個横列
３個の計９個の半導体チップ４を同一の回路基板７に搭
載し半田接続した場合、半導体チップ間で裏面の最大高
さと最小高さの差ΔＨは５〜１０μｍにおさめることが
できる。したがってサーマルグリース１８は膜厚が１０
〜７０μｍと薄い膜となり、半導体チップの裏面と放熱
器との間が低熱抵抗となるから、半導体チップの高速＆
高出力の性能を十分に発揮させることができる。このサ
ーマルグリース１８は熱伝導材としての作用と接着材と
しての作用を行うが、放熱器の接着強度を大きくするた
めに図示していない箇所において、ネジ、ピン等の機械
的な固定手段を併設することが好ましい。Next, as shown in FIG. 2B, a radiator 19 is attached to the exposed back surface 14 of the semiconductor chip through a thermal grease 18, for example, high thermal conductive silicone (elastomer type). In this embodiment, due to the flat surface 21 of the block 1, the height deviation (ΔH) of the back surface 14 of each semiconductor chip 4 has a small value. For example, when a total of nine semiconductor chips 4 of three rows and three columns are mounted on the same circuit board 7 and connected by soldering, the difference ΔH between the maximum height and the minimum height of the back surface between the semiconductor chips is 5 to 10 μm. Can be saved. Therefore, the thermal grease 18 has a film thickness of 10
Since it is a thin film of ~ 70 μm and the low thermal resistance is between the back surface of the semiconductor chip and the heat sink, high-speed &
The high output performance can be fully exerted. The thermal grease 18 functions as a heat conductive material and an adhesive material, but in order to increase the adhesive strength of the radiator, a mechanical fixing means such as a screw or a pin is provided at a place not shown. Preferably.

【００２３】また、回路基板と半導体チップとをパッケ
ージに封止する際は、複数の半導体チップの裏面が平坦
な状態であるので、サーマルグリースを介して高熱伝導
材料のパッケージキャップに熱的に接続し、キャップに
放熱フィンを取り付けることで、低熱抵抗の放熱系を形
成することができる。Further, when the circuit board and the semiconductor chip are sealed in the package, the back surfaces of the plurality of semiconductor chips are in a flat state, so that they are thermally connected to the package cap made of the high thermal conductive material via the thermal grease. Then, by attaching the radiation fins to the cap, a radiation system with low thermal resistance can be formed.

【００２４】図３（Ａ）および図３（Ｂ）は、図１のブ
ロック１をシリコンウェハーにより構成した場合を示す
平面図および断面図である。口径が４インチ、厚さ４０
０μｍの（１００）結晶面のシリコンウェハー１６の裏
面２４にフォトリソグラフィ技術により二酸化シリコン
膜（図示省略）をマスク材として形成し、異方性エッチ
ングで４個の貫通孔３を形成する。図３（Ｂ）に示すよ
うに、貫通孔３は異方性エッチング特有の（１１１）面
でストップされた斜面を有する構造となり、裏面２４側
で大きく表面２５側に行くに従って小さくなり、表面２
５では例えば一辺が３μｍの正方形状となる。そして接
着剤２を表面２５上に塗布しパターン形成する。3 (A) and 3 (B) are a plan view and a sectional view showing a case where the block 1 of FIG. 1 is composed of a silicon wafer. Caliber 4 inches, thickness 40
A silicon dioxide film (not shown) is formed as a mask material by photolithography on the back surface 24 of the silicon wafer 16 having a (100) crystal plane of 0 μm, and four through holes 3 are formed by anisotropic etching. As shown in FIG. 3B, the through hole 3 has a structure having an inclined surface stopped by the (111) plane peculiar to anisotropic etching, becomes larger on the back surface 24 side and becomes smaller toward the front surface 25 side, and the surface 2
5 has a square shape with one side of 3 μm, for example. Then, the adhesive 2 is applied on the surface 25 to form a pattern.

【００２５】この方法によれば、半導体ウェハー製造に
おけるフォトリソグラフィ技術およびエッチング技術を
そのまま用いることができるので、回路基板７との位置
合せのための貫通孔を精度良く形成することができる。According to this method, since the photolithography technique and the etching technique in the manufacture of semiconductor wafers can be used as they are, it is possible to accurately form the through holes for alignment with the circuit board 7.

【００２６】図４は図１のステンレスによるブロック１
を示す平面図であり、二点鎖線で示された箇所に半導体
チップが搭載接着される。それぞれの箇所に一対の＋字
型の位置合せマーク３５が表面２１より切り込みを入れ
て形成されている。一方、半導体チップにはその表面側
に配線パターンを形成する際に位置合せマークを形成す
る。この半導体チップの表面の位置合せマークは裏面側
から検知する必要があるので半導体チップとブロックと
の位置合せは赤外線を使用する。FIG. 4 is a block 1 made of stainless steel shown in FIG.
FIG. 3 is a plan view showing the semiconductor chip, and the semiconductor chip is mounted and adhered to the place indicated by the chain double-dashed line. A pair of + -shaped alignment marks 35 are formed at each position by cutting in from the surface 21. On the other hand, alignment marks are formed on the surface of the semiconductor chip when the wiring pattern is formed. Since the alignment mark on the front surface of the semiconductor chip needs to be detected from the back surface side, infrared rays are used for alignment between the semiconductor chip and the block.

【００２７】図５はブロック１に半導体チップ４を搭載
する状態を示す斜視図である。基台３１上の所定位置に
ガイドピン３３によりブロック１が載置され、真空孔３
２からの真空引きにより固定され、ブロック１上に半導
体チップ４が逐次搭載され接着される。FIG. 5 is a perspective view showing a state in which the semiconductor chip 4 is mounted on the block 1. The block 1 is placed at a predetermined position on the base 31 by the guide pin 33, and the vacuum hole 3
It is fixed by vacuuming from 2, and the semiconductor chips 4 are sequentially mounted and adhered on the block 1.

【００２８】次に図６を参照して、ブロックに半導体チ
ップを位置合せする方法を説明する。Next, with reference to FIG. 6, a method of aligning a semiconductor chip with a block will be described.

【００２９】図６（Ａ）に示すように、基台３１に真空
吸着されたブロック１と、Ｘ方向、Ｙ方向およびθ方向
に移動可能なコレット４３に表面１５側が真空吸着され
た半導体チップ４との間に、ハーフミラー４１が載置さ
れている。赤外線４６を用いてハーフミラー４１を通し
てＣＣＤカメラ４２により、半導体チップ４上の位置合
せマーク４５とブロック１上の位置せマーク３５とを重
ねて視てコレット４３をＸ方向、Ｙ方向およびθ方向に
移動調整することにより両マーク４５，３５を正確に重
畳させ、しかる後にハーフミラーを横方向に引き出し
て、コレットを垂直に下降させて半導体ペレットをブロ
ックに接着させて（図６（Ｂ））、コレットと半導体ペ
レットとの真空吸着を解除する。次に別の半導体ペレッ
トをコレットに真空吸着させて同様の操作を繰り返す。As shown in FIG. 6A, the block 1 vacuum-sucked on the base 31 and the semiconductor chip 4 vacuum-sucked on the surface 15 side by the collet 43 movable in the X, Y and θ directions. The half mirror 41 is mounted between the two. Using the infrared ray 46, the alignment mark 45 on the semiconductor chip 4 and the positioning mark 35 on the block 1 are superposed on each other by the CCD camera 42 through the half mirror 41 and the collet 43 is viewed in the X, Y and θ directions. The marks 45 and 35 are accurately overlapped by the movement adjustment, and then the half mirror is pulled out in the lateral direction and the collet is vertically lowered to adhere the semiconductor pellet to the block (FIG. 6 (B)). The vacuum suction between the collet and the semiconductor pellet is released. Next, another semiconductor pellet is vacuum-adsorbed to the collet and the same operation is repeated.

【００３０】次に図７，図８を参照して本発明の第２の
実施例の実装方法を説明する。尚、図７，図８において
図１，図２と同一もしくは類似の箇所は同一の符号で示
してあるのでその箇所に関する説明は省略する。Next, a mounting method according to the second embodiment of the present invention will be described with reference to FIGS. In FIGS. 7 and 8, the same or similar parts as those in FIGS. 1 and 2 are designated by the same reference numerals, and the description thereof will be omitted.

【００３１】まず、図７（Ａ）に示すように、ブロック
１の平滑表面２１上に融点が１００℃のワックス５２を
膜厚５〜１０μｍに塗布する。First, as shown in FIG. 7A, a wax 52 having a melting point of 100 ° C. is applied on the smooth surface 21 of the block 1 to a film thickness of 5 to 10 μm.

【００３２】次に、図７（Ｂ）に示すように、半導体チ
ップ４の裏面１４側をブロック１の平滑表面２１所定位
置にワックス５２により接着する。この実施例の半導体
チップ４の表面１５上の半田バンプ電極５５は半田メッ
キにより形成した高融点半田５６の上に半田メッキによ
り形成した低融点半田５７を重ねた構造になっている。Next, as shown in FIG. 7B, the back surface 14 side of the semiconductor chip 4 is adhered to a predetermined position of the smooth surface 21 of the block 1 with a wax 52. The solder bump electrode 55 on the surface 15 of the semiconductor chip 4 of this embodiment has a structure in which a low melting point solder 57 formed by solder plating is stacked on a high melting point solder 56 formed by solder plating.

【００３３】次に、図７（Ｃ）に示すように、ボンダー
のステージ６上に回路基板７を載置し、ブロック１の平
滑表面２１と回路基板７の表面２２を対向配置させ、貫
通孔３と位置合せマーク９によりブロック１と回路基板
７との位置定めを行なう。Next, as shown in FIG. 7 (C), the circuit board 7 is placed on the stage 6 of the bonder, the smooth surface 21 of the block 1 and the surface 22 of the circuit board 7 are arranged to face each other, and the through hole is formed. The block 1 and the circuit board 7 are positioned by the 3 and the alignment mark 9.

【００３４】次に、図８（Ａ）に示すように、ブロック
１を垂直に下降させて複数のバンプ電極５５と複数のパ
ッド８とをそれぞれ当接する。本発明では半田フラック
スは存在しない。そして１１０〜１３０℃の温度で３０
秒〜３分間、ハロゲンを含んだ不活性ガス雰囲気の熱処
理炉で半田の予備リフローを行ない、半田バンプ５５の
低融点半田５７のみを溶融して局部的な接着を行なう。
この際、ワックス５２は発泡し接着力が喪失してブロッ
ク１が半導体チップ４の裏面１４から除去される。Next, as shown in FIG. 8A, the block 1 is vertically lowered to bring the plurality of bump electrodes 55 and the plurality of pads 8 into contact with each other. There is no solder flux in the present invention. And 30 at a temperature of 110 to 130 ° C
Preliminary reflow of the solder is performed in a heat treatment furnace in an inert gas atmosphere containing halogen for 2 seconds to 3 minutes, and only the low melting point solder 57 of the solder bump 55 is melted to perform local adhesion.
At this time, the wax 52 foams and loses its adhesive force, and the block 1 is removed from the back surface 14 of the semiconductor chip 4.

【００３５】次に、図８（Ｂ）に示すように、半導体チ
ップの半田バンプ電極と接続するパッド８を有する配線
パターン５８の先端に位置し、回路基板７の周辺部に形
成されてある外部端子接続用のパッド６４に検査プロー
ブ５９を当接させて、半導体チップを局部的に接続した
回路基板の電気的検査を行う。この電気的試験で合格し
たものは次工程に送られ、不合格のもので修理、修正の
可能のものはそれを行なった後、再度の電気的試験を行
い合格したものは次工程に送られる。Next, as shown in FIG. 8 (B), an external portion formed on the peripheral portion of the circuit board 7 is located at the tip of the wiring pattern 58 having the pad 8 connected to the solder bump electrode of the semiconductor chip. The inspection probe 59 is brought into contact with the pad 64 for terminal connection to electrically inspect the circuit board to which the semiconductor chip is locally connected. Those that have passed this electrical test are sent to the next process, and those that have failed and that can be repaired or repaired are then subjected to another electrical test, and those that have passed are sent to the next process. .

【００３６】次工程では図８（Ｃ）に示すように、カー
ボン製の治具６１の平坦な底面６２上に半導体チップの
裏面１４を当接載置し、回路基板７の裏面２３にカーボ
ン製の蓋６３を被せて、２００〜３５０℃の温度で３０
秒〜５分間、ハロゲンを含んだ不活性ガス雰囲気の熱処
理炉で半田の本リフローを行ない、半田バンプ５の高融
点半田５６を溶融しかつ予備リフローで溶融し冷却凝固
した低融点半田５７を再度溶融して、表面張力により半
田ボール１０を形成して半導体チップと回路基板との接
続を行なう。In the next step, as shown in FIG. 8C, the back surface 14 of the semiconductor chip is placed in contact with the flat bottom surface 62 of the jig 61 made of carbon, and the back surface 23 of the circuit board 7 is made of carbon. Cover with a lid 63 of 30 at a temperature of 200 to 350 ° C.
The main reflow of the solder is performed in a heat treatment furnace in an inert gas atmosphere containing halogen for 2 seconds to 5 minutes to melt the high melting point solder 56 of the solder bump 5 and the low melting point solder 57 that is melted and cooled and solidified by the preliminary reflow. After melting, the solder balls 10 are formed by the surface tension to connect the semiconductor chip and the circuit board.

【００３７】その後、必要に応じて第１の実施例と同様
に、半導体チップの裏面に放熱器手段を設けることがで
きる。After that, if necessary, a radiator means can be provided on the back surface of the semiconductor chip as in the first embodiment.

【００３８】この第２の実施例では、半導体チップの裏
面は予備リフロー時にはブロック１の平坦面２１上に載
置され、本リフロー時には治具６１の平坦底面６２上に
載置されているから、複数の半導体チップの裏面間の高
さの偏差（ΔＨ）は第１の実施例と同様に小さい値とな
る。In the second embodiment, the back surface of the semiconductor chip is placed on the flat surface 21 of the block 1 during the preliminary reflow, and is placed on the flat bottom surface 62 of the jig 61 during the main reflow. The height deviation (ΔH) between the back surfaces of the plurality of semiconductor chips has a small value as in the first embodiment.

【００３９】[0039]

【発明の効果】このように本発明では、半導体チップの
仮止めを半導体チップの裏面側で行ない、半導体チップ
の表面側に半田フラックスが存在しないから、半田フラ
ックスに含まれる多くの有害な不純物による信頼性上ま
た歩留り上の問題の発生は皆無となる。As described above, according to the present invention, since the semiconductor chip is temporarily fixed on the back surface side of the semiconductor chip and the solder flux does not exist on the front surface side of the semiconductor chip, many harmful impurities contained in the solder flux are generated. There will be no reliability or yield problems.

【００４０】さらに本発明では、ブロックの平坦面もし
くはブロックの平坦面と治具の平坦面に複数の半導体チ
ップの裏面側を接着してリフローを行うから、リフロー
後の複数の半導体チップ間の裏面の高低差はほとんど無
視することができ、全ての裏面が実質的に同一平面に位
置される。したがって、薄い膜厚の、例えばサーマルグ
リースを接着剤として放熱器を熱抵抗を小にして複数の
半導体チップの裏面に共通接続することができる。Further, in the present invention, since the back side of a plurality of semiconductor chips is adhered to the flat surface of the block or the flat surface of the block and the flat surface of the jig for reflow, the back surface between the plurality of semiconductor chips after the reflow is performed. The difference in height of can be almost ignored, and all the back surfaces are located substantially in the same plane. Therefore, it is possible to commonly connect the radiator to the back surface of the plurality of semiconductor chips with a small film thickness, for example, using thermal grease as an adhesive to reduce the thermal resistance.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１の実施例の実装方法の前半を工程
順に示した断面図である。FIG. 1 is a sectional view showing a first half of a mounting method according to a first exemplary embodiment of the present invention in process order.

【図２】本発明の第１の実施例の実装方法の後半を工程
順に示した断面図である。FIG. 2 is a cross-sectional view showing the latter half of the mounting method of the first exemplary embodiment of the present invention in the order of steps.

【図３】図１のブロック１をシリコンウェハーで構成し
た場合を示す図であり、（Ａ）は平面図、（Ｂ）は
（Ａ）を切断線Ａ−Ａ′で切断し矢印の方向を視た断面
図である。3A and 3B are diagrams showing a case where the block 1 of FIG. 1 is composed of a silicon wafer, in which FIG. 3A is a plan view and FIG. 3B is a sectional view taken along the line AA ′ of FIG. FIG.

【図４】ブロックの一例を示す平面図である。FIG. 4 is a plan view showing an example of a block.

【図５】ブロックに半導体チップを搭載する状態を示す
斜視図である。FIG. 5 is a perspective view showing a state in which a semiconductor chip is mounted on a block.

【図６】ブロックに半導体チップを位置合わせする方法
を示す概略図である。FIG. 6 is a schematic view showing a method of aligning a semiconductor chip with a block.

【図７】本発明の第２の実施例の実施方法の前半を工程
順に示した断面図である。FIG. 7 is a cross-sectional view showing the first half of a method of implementing a second embodiment of the present invention in process order.

【図８】本発明の第２の実施方法の後半を工程順に示し
た図であり、（Ａ），（Ｃ）は断面図、（Ｂ）は平面図
である。FIG. 8 is a diagram showing the latter half of the second implementation method of the present invention in the order of steps, (A) and (C) being cross-sectional views and (B) being a plan view.

【図９】従来技術の実装方法を工程順に示した断面図で
ある。FIG. 9 is a cross-sectional view showing a mounting method of a conventional technique in the order of steps.

【符号の説明】[Explanation of symbols]

１ ブロック ２，５２ 仮接着剤としてのワックス ３ 貫通孔 ４ 半導体チップ ５，５５ 半田バンプ電極 ６ ステージ ７ 回路基板 ８ 配線パターンのパッド ９ 回路基板上の位置合せマーク １０ 半田ボール １１ 半田フラックス １４ 半導体チップの裏面 １５ 半導体チップの表面 １６ ブロックを構成するシリコンウェハー １８ サーマルグリース １９ 放熱器 ２１ ブロックの平滑表面 ２２ 回路基板の表面 ２３ 回路基板の裏面 ２４ シリコンウェハーの裏面 ２５ シリコンウェハーの表面 ３１ 基台 ３２ 真空孔 ３３ ガイドピン ３５ ブロック上の位置合せマーク ４１ ハーフミラー ４２ ＣＣＤカメラ ４３ コレット ４５ 半導体ペレット表面上の位置合せマーク ４６ 赤外線 ５６ 高融点半田 ５７ 低融点半田 ５８ 配線パターン ５９ 検査プローブ ６１ 治具 ６２ 治具の平坦な底面 ６３ 治具の蓋 ６４ 配線パターンの外部端子接続用のパッド 1 block 2,52 wax as temporary adhesive 3 through hole 4 semiconductor chip 5,55 solder bump electrode 6 stage 7 circuit board 8 wiring pattern pad 9 alignment mark on circuit board 10 solder ball 11 solder flux 14 semiconductor chip Back surface 15 of semiconductor chip 16 silicon wafer 18 constituting block 18 thermal grease 19 radiator 21 smooth surface of block 22 surface of circuit board 23 back surface of circuit board 24 back surface of silicon wafer 25 surface of silicon wafer 31 base 32 vacuum Hole 33 Guide pin 35 Alignment mark on block 41 Half mirror 42 CCD camera 43 Collet 45 Alignment mark on semiconductor pellet surface 46 Infrared 56 High melting point solder 57 Low melting point solder 58 Wiring pattern 59 Inspection professional -61 jig 62 flat bottom of jig 63 lid of jig 64 pad for external terminal connection of wiring pattern

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 表面側に半田バンプ電極を形成した複数
個の半導体チップの裏面側をブロックの平坦面の所定位
置にそれぞれ接着剤により仮止めする工程と、複数のパ
ッドを有する配線パターンを表面に形成した回路基板を
用意する工程と、前記ブロックの平坦面を前記回路基板
の表面に対向させて前記ブロックと前記回路基板とを位
置決めし、両者を近付けることにより前記半田バンプ電
極と前記パッドとを半田フラックスを介することなく当
接させ、加熱により前記半田バンプ電極の半田を溶融さ
せて前記半田バンプ電極を前記パッドに溶着させこれに
より前記複数個の半導体チップを一括して前記回路基板
に接続することを特徴とするフリップチップ型半導装置
の実装方法。1. A step of temporarily fixing the back side of a plurality of semiconductor chips having solder bump electrodes formed on the front side to predetermined positions on a flat surface of a block with an adhesive, and a wiring pattern having a plurality of pads on the surface. A step of preparing a circuit board formed in, and positioning the block and the circuit board with the flat surface of the block facing the surface of the circuit board, and by bringing them close to each other, the solder bump electrode and the pad Are abutted without passing through solder flux, and the solder of the solder bump electrodes is melted by heating to weld the solder bump electrodes to the pads, thereby collectively connecting the plurality of semiconductor chips to the circuit board. A method of mounting a flip-chip type semiconductor device, comprising: 【請求項２】 前記加熱により半田を溶融させる工程は
ハロゲンガス雰囲気で行うことを特徴とする請求項１に
記載の半導体装置の実装方法。2. The method of mounting a semiconductor device according to claim 1, wherein the step of melting the solder by heating is performed in a halogen gas atmosphere. 【請求項３】 前記ブロックに位置決め用の貫通孔が形
成されており、前記回路基板に位置決め用のパターンが
形成されており、前記貫通孔を通して前記パターンを視
ることにより前記ブロックと前記回路基板との前記位置
決めを行なうことを特徴とする請求項１に記載の半導体
装置の実装方法。3. A positioning through hole is formed in the block, a positioning pattern is formed in the circuit board, and the block and the circuit board are viewed by viewing the pattern through the through hole. 2. The method for mounting a semiconductor device according to claim 1, wherein the positioning is performed with. 【請求項４】 前記ブロックは（１００）面のシリコン
ウェハーであり、前記位置決め用の貫通孔はこのシリコ
ンウェハーを選択的に異方性エッチングして形成したこ
とを特徴とする請求項３に記載の半導体装置の実装方
法。4. The block is a (100) plane silicon wafer, and the through hole for positioning is formed by selectively anisotropically etching the silicon wafer. Semiconductor device mounting method. 【請求項５】 前記半田バンプ電極は高融点半田とその
上の低融点半田とを有し、前記加熱工程は第１の温度に
よる第１の熱処理工程とこの第１の温度より高い第２の
温度による第２の熱処理工程とを有し、前記第１の熱処
理工程によって前記低融点半田のみを溶融させて局部的
な溶着を行ない、かつ前記ブロックを前記半導体チップ
の裏面より除去し、しかる後に、前記半導体チップの裏
面を治具の平坦面に載置した状態で前記第２の熱処理工
程を行って前記高融点半田および前記低融点半田を溶融
させて最終的な溶着を行なうことを特徴とする請求項１
に記載の半導体装置の実装方法。5. The solder bump electrode has a high melting point solder and a low melting point solder thereon, and the heating step includes a first heat treatment step at a first temperature and a second heat treatment step at a temperature higher than the first temperature. A second heat treatment step depending on the temperature, wherein only the low melting point solder is melted by the first heat treatment step to perform local welding, and the block is removed from the back surface of the semiconductor chip, and thereafter, The second heat treatment step is performed while the back surface of the semiconductor chip is placed on the flat surface of the jig to melt the high melting point solder and the low melting point solder to perform final welding. Claim 1
A method for mounting a semiconductor device according to item 1. 【請求項６】 前記第１の熱処理工程と前記第２の熱処
理工程との間に、前記半導体チップが局部的に溶着され
ている前記回路基板の電気的試験を行うことを特徴とす
る請求項５に記載の半導体装置の実装方法。6. The electrical test of the circuit board on which the semiconductor chip is locally welded is performed between the first heat treatment step and the second heat treatment step. 5. The method for mounting a semiconductor device according to item 5. 【請求項７】 前記接着剤は前記ブロックの平坦面上に
塗布された膜厚５−１０μｍのワックスであることを特
徴とする請求項１に記載の半導体装置の実装方法。7. The method of mounting a semiconductor device according to claim 1, wherein the adhesive is a wax having a film thickness of 5 to 10 μm applied on the flat surface of the block. 【請求項８】 一括して前記回路基板に接続された前記
複数個の半導体チップの裏面側に放熱器を共通接続する
ことを特徴とする請求項１に記載のフリップチップ型半
導装置の実装方法。8. The mounting of the flip-chip type semiconductor device according to claim 1, wherein a radiator is commonly connected to the back surface side of the plurality of semiconductor chips connected to the circuit board at a time. Method. 【請求項９】 前記放熱器は前記半導体チップの裏面に
膜厚１０〜７０μｍのサーマルグリースで接着されてい
ることを特徴とする請求項８に記載の半導体装置の実装
方法。9. The method of mounting a semiconductor device according to claim 8, wherein the radiator is bonded to the back surface of the semiconductor chip with a thermal grease having a film thickness of 10 to 70 μm.
JP22369392A 1991-09-24 1992-08-24 Flip-chip type semiconductor device mounting method Expired - Fee Related JPH0779152B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22369392A JPH0779152B2 (en) 1991-09-24 1992-08-24 Flip-chip type semiconductor device mounting method

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP3-242249 1991-09-24
JP24224991 1991-09-24
JP22369392A JPH0779152B2 (en) 1991-09-24 1992-08-24 Flip-chip type semiconductor device mounting method

Publications (2)

Publication Number Publication Date
JPH06163634A true JPH06163634A (en) 1994-06-10
JPH0779152B2 JPH0779152B2 (en) 1995-08-23

Family

ID=26525631

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22369392A Expired - Fee Related JPH0779152B2 (en) 1991-09-24 1992-08-24 Flip-chip type semiconductor device mounting method

Country Status (1)

Country Link
JP (1) JPH0779152B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006077739A1 (en) * 2004-12-28 2006-07-27 Mitsumasa Koyanagi Method and apparatus for manufacturing integrated circuit device using self organizing function
WO2007077688A1 (en) * 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method and semiconductor module manufacturing method
JP2007250868A (en) * 2006-03-16 2007-09-27 Fujitsu Ltd Semiconductor device and method for manufacturing the same
JP2007281264A (en) * 2006-04-10 2007-10-25 Elpida Memory Inc Method of manufacturing semiconductor device
KR100889283B1 (en) * 2001-09-12 2009-03-17 니기소 가부시키가이샤 Circuit device mounting method and press
WO2010110070A1 (en) * 2009-03-23 2010-09-30 東京エレクトロン株式会社 Method and apparatus for producing three-dimensional integrated circuit
CN102378498A (en) * 2010-08-12 2012-03-14 富葵精密组件(深圳)有限公司 Production method of circuit board module
JP2012134233A (en) * 2010-12-20 2012-07-12 Disco Abrasive Syst Ltd Jig plate and method for stacking semiconductor device chip using the jig plate
JP2014045013A (en) * 2012-08-24 2014-03-13 Bondtech Inc Method and device for positioning object onto substrate
KR20230057265A (en) 2021-10-21 2023-04-28 가부시기가이샤 디스코 Processing method

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100889283B1 (en) * 2001-09-12 2009-03-17 니기소 가부시키가이샤 Circuit device mounting method and press
TWI395253B (en) * 2004-12-28 2013-05-01 Mitsumasa Koyanagi Method of fabricating integrated circuit device using self-organization function and apparatus for fabricating same
US8283208B2 (en) * 2004-12-28 2012-10-09 Mitsumasa Koyanagi Method and apparatus for fabricating integrated circuit device using self-organizing function
US8722460B2 (en) 2004-12-28 2014-05-13 Mitsumasa Koyanagi Method and apparatus for fabricating integrated circuit device using self-organizing function
WO2006077739A1 (en) * 2004-12-28 2006-07-27 Mitsumasa Koyanagi Method and apparatus for manufacturing integrated circuit device using self organizing function
JP5007127B2 (en) * 2004-12-28 2012-08-22 光正 小柳 Integrated circuit device manufacturing method and manufacturing apparatus using self-organizing function
WO2007077688A1 (en) * 2005-12-28 2007-07-12 Kabushiki Kaisha Toyota Jidoshokki Soldering method and semiconductor module manufacturing method
JP2007250868A (en) * 2006-03-16 2007-09-27 Fujitsu Ltd Semiconductor device and method for manufacturing the same
JP2007281264A (en) * 2006-04-10 2007-10-25 Elpida Memory Inc Method of manufacturing semiconductor device
WO2010110070A1 (en) * 2009-03-23 2010-09-30 東京エレクトロン株式会社 Method and apparatus for producing three-dimensional integrated circuit
US8349652B2 (en) 2009-03-23 2013-01-08 Tokyo Electron Limited Method and apparatus for manufacturing three-dimensional integrated circuit
JP2010225803A (en) * 2009-03-23 2010-10-07 Tokyo Electron Ltd Method and apparatus for manufacturing of three-dimensional integrated circuit
CN102378498A (en) * 2010-08-12 2012-03-14 富葵精密组件(深圳)有限公司 Production method of circuit board module
JP2012134233A (en) * 2010-12-20 2012-07-12 Disco Abrasive Syst Ltd Jig plate and method for stacking semiconductor device chip using the jig plate
JP2014045013A (en) * 2012-08-24 2014-03-13 Bondtech Inc Method and device for positioning object onto substrate
KR20230057265A (en) 2021-10-21 2023-04-28 가부시기가이샤 디스코 Processing method

Also Published As

Publication number Publication date
JPH0779152B2 (en) 1995-08-23

Similar Documents

Publication Publication Date Title
US5297333A (en) Packaging method for flip-chip type semiconductor device
US5427301A (en) Ultrasonic flip chip process and apparatus
TWI514487B (en) Thermal compression bonding of semiconductor chips
US11587860B2 (en) Method of forming thin die stack assemblies
KR100555395B1 (en) Flip chip interconnection using no-clean flux
JP2555811B2 (en) Flip chip bonding method for semiconductor chips
EP1386356B1 (en) Fluxless flip chip interconnection
JP2007516602A (en) Manufacturing structure and method of a capped tip containing a flowable conductive medium
US7833897B2 (en) Process for making interconnect solder Pb-free bumps free from organo-tin/tin deposits on the wafer surface
JP2000156457A (en) Manufacture of semiconductor device
JP3007497B2 (en) Semiconductor integrated circuit device, its manufacturing method, and its mounting method
JPH06163634A (en) Method of installation of flip chip semiconductor device
JP2001024085A (en) Semiconductor device
JP2010177604A (en) Semiconductor manufacturing method and manufacturing device
JP2715793B2 (en) Semiconductor device and manufacturing method thereof
TW200536646A (en) Vertical removal of excess solder from a circuit substrate
JPH0626227B2 (en) How to attach a semiconductor chip
US7666780B2 (en) Alignment verification for C4NP solder transfer
JPH07106334A (en) Method for bonding optical semiconductor device to optical substrate
JPH10308415A (en) Method for mounting electrode, electronic component, electronic device, and electronic component
JP4083533B2 (en) Manufacturing method of semiconductor device
JPH05218136A (en) Bonding method for flip chip
TWI807348B (en) Flip chip process and bonding equipment
JPH09186162A (en) Formation of metal bump
JP4952527B2 (en) Semiconductor device manufacturing method and semiconductor device

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19960206

LAPS Cancellation because of no payment of annual fees