JPH06151739A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06151739A JPH06151739A JP4294691A JP29469192A JPH06151739A JP H06151739 A JPH06151739 A JP H06151739A JP 4294691 A JP4294691 A JP 4294691A JP 29469192 A JP29469192 A JP 29469192A JP H06151739 A JPH06151739 A JP H06151739A
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- signal transmission
- transmission means
- field effect
- effect transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置の改良に関
する。詳しくは、基板の導電形を自動的に判別し、半導
体素子の特性をその基板導電形に適合するように自動的
に補正することができる半導体装置を提供することを目
的とする改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in semiconductor devices. More specifically, the present invention relates to an improvement intended to provide a semiconductor device capable of automatically determining the conductivity type of a substrate and automatically correcting the characteristics of a semiconductor element so as to match the conductivity type of the substrate.
【０００２】[0002]
【従来の技術】従来技術において、電界効果トランジス
タ等の半導体素子を基板に形成する場合、その半導体素
子の導電形と基板導電形とが同一のときは基板に形成さ
れた反対導電型のWell内に半導体素子を形成し、半導体
素子の導電形と基板導電形とが反対導電型のときは基板
に直接、半導体素子を形成している。そして、基板の導
電形によって、その基板に形成される半導体素子を使用
した半導体回路を設計変更することはなく、基板の導電
形が相違しても同一の半導体回路が採用されている。そ
の理由は、基板の導電形別にそれぞれ半導体回路を設計
することは半導体回路設計に膨大な時間を要し生産性を
低下させることが著しいからである。2. Description of the Related Art In the prior art, when a semiconductor element such as a field effect transistor is formed on a substrate, if the conductivity type of the semiconductor element and the substrate conductivity type are the same, a well of opposite conductivity type formed on the substrate The semiconductor element is formed on the substrate, and when the conductivity type of the semiconductor element and the conductivity type of the substrate are opposite conductivity types, the semiconductor element is formed directly on the substrate. The design of a semiconductor circuit using a semiconductor element formed on the substrate is not changed depending on the conductivity type of the substrate, and the same semiconductor circuit is used even if the conductivity type of the substrate is different. The reason is that designing a semiconductor circuit for each conductivity type of a substrate requires a huge amount of time for designing the semiconductor circuit, which significantly reduces productivity.
【０００３】[0003]
【発明が解決しようとする課題】ところが、基板のWell
内に半導体素子を形成する場合と、基板に直接、半導体
素子を形成する場合とでは、その半導体素子の特性（例
えばコンダクタンス）が僅かに相違し、したがって、従
来技術においては、上記二つの場合で、同一半導体回路
でも特性が僅かに相違することが起こると言う欠点があ
る。[Problems to be Solved by the Invention]
The characteristics (for example, conductance) of the semiconductor element are slightly different between the case where the semiconductor element is formed inside and the case where the semiconductor element is formed directly on the substrate. Therefore, in the conventional technique, there is a difference between the above two cases. However, there is a drawback that the characteristics may be slightly different even in the same semiconductor circuit.
【０００４】近年半導体集積回路には、特性の高精度化
が要求されており、上記のような基板導電形の相違に起
因する半導体素子の特性の相違によって半導体回路の特
性が設計値から僅かにずれることを看過しえない状況に
ある。In recent years, semiconductor integrated circuits are required to have higher accuracy, and the characteristics of the semiconductor circuit are slightly different from the designed values due to the difference in characteristics of the semiconductor element caused by the difference in the conductivity type of the substrate as described above. The situation is such that it cannot be overlooked.
【０００５】本発明の目的は、上記の欠点を解消するこ
とにあり、基板の導電形を自動的に判別し、半導体素子
の特性をその基板導電形に適合する様に自動的に補正す
ることができる半導体装置を提供することにある。An object of the present invention is to eliminate the above-mentioned drawbacks, and to automatically determine the conductivity type of a substrate and automatically correct the characteristics of a semiconductor element so as to match the conductivity type of the substrate. It is to provide a semiconductor device capable of
【０００６】[0006]
【課題を解決するための手段】上記の目的は、下記のい
ずれの手段をもっても達成される。The above object can be achieved by any of the following means.
【０００７】第１の手段は、制御信号を受けて負荷また
は論理回路（５）に対して電位を供給する第１の制御信
号伝達手段（４）と、前記の第１の制御信号伝達手段
（４）と並列に接続され、制御信号を受けて、負荷また
は論理回路（５）に対して電位を供給する第２の制御信
号伝達手段（３）と、基板内に形成された拡散領域の電
位に応答してオン又はオフし、前記の第２の制御信号伝
達手段（３）への電位の供給を制御する補正回路選択手
段（２）とを有する半導体装置である。The first means includes a first control signal transmitting means (4) for receiving a control signal and supplying a potential to the load or the logic circuit (5) and the first control signal transmitting means ( 4) second control signal transmitting means (3) connected in parallel with the control signal for supplying a potential to the load or the logic circuit (5), and the potential of the diffusion region formed in the substrate And a correction circuit selection means (2) for controlling the supply of the potential to the second control signal transmission means (3) in response to the above.
【０００８】上記の第１の手段には例えば下記の実施態
様がある。 イ．制御信号を受けて負荷または論理回路に対して電位
を供給するＰチャネル電界効果トランジスタよりなる第
１の制御信号伝達手段（４）と同一基板に形成されるＮ
拡散領域を有する導電形判別領域（１）と、この導電形
判別領域（１）のＮ拡散領域にゲートが接続され、ソー
スは高電位電源に接続されるＰチャネル電界効果トラン
ジスタよりなる補正回路選択手段（２）と、この補正回
路選択手段（２）を構成するＰチャネル電界効果トラン
ジスタのドレインにソースが接続され、前記の第１の制
御信号伝達手段（４）を構成するトランジスタのゲート
にゲートが接続され、前記の第１の制御信号伝達手段
（４）の出力端子にドレインが接続されている第２の制
御信号伝達手段（３）とよりなる半導体装置。The above-mentioned first means has the following embodiments, for example. I. N formed on the same substrate as the first control signal transmission means (4) composed of a P-channel field effect transistor which receives a control signal and supplies a potential to a load or a logic circuit.
A correction circuit selection including a conductivity type discriminating region (1) having a diffusion region, a gate connected to the N diffusion region of the conductivity type discriminating region (1), and a source connected to a high potential power source for a P-channel field effect transistor. The source is connected to the drain of the means (2) and the P-channel field effect transistor forming the correction circuit selecting means (2), and the gate is connected to the gate of the transistor forming the first control signal transmitting means (4). And a second control signal transmission means (3) having a drain connected to the output terminal of the first control signal transmission means (4).
【０００９】ロ．制御信号を受けて負荷または論理回路
に対して電位を供給するＰチャネル電界効果トランジス
タよりなる第１の制御信号伝達手段（４）と同一基板に
形成されるＰ拡散領域を有する導電形判別領域（６）
と、この導電形判別領域（６）のＰ拡散領域に否定論理
回路（７）を介してゲートが接続されソースは高電位電
源に接続されるＰチャネル電界効果トランジスタよりな
る補正回路選択手段（２）と、この補正回路選択手段
（２）を構成するＰチャネル電界効果トランジスタのド
レインにソースが接続され、前記の第１の制御信号伝達
手段（４）を構成するトランジスタのゲートにゲートが
接続され、前記の第１の制御信号伝達手段（４）の出力
端子にドレインが接続されている第２の制御信号伝達手
段（３）とよりなる半導体装置。B. A conductivity type discriminating region (P type diffusion region formed on the same substrate as the first control signal transmitting unit (4) including a P channel field effect transistor for receiving a control signal and supplying a potential to a load or a logic circuit ( 6)
And a correction circuit selecting means (2) comprising a P-channel field effect transistor whose gate is connected to the P diffusion region of the conductivity type discriminating region (6) through a negative logic circuit (7) and whose source is connected to a high potential power source. ), And the source is connected to the drain of the P-channel field effect transistor forming the correction circuit selecting means (2), and the gate is connected to the gate of the transistor forming the first control signal transmitting means (4). , A semiconductor device comprising a second control signal transmission means (3) having a drain connected to the output terminal of the first control signal transmission means (4).
【００１０】ハ．制御信号を受けて負荷または論理回路
に対して電位を供給するＮチャネル電界効果トランジス
タよりなる第１の制御信号伝達手段（４）と同一基板に
形成されるＰ拡散領域を有する導電形判別領域（６）
と、この導電形判別領域（６）のＰ拡散領域に否定論理
回路（７）を介してゲートが接続され、ソースは低電位
電源に接続されるＮチャネル電界効果トランジスタより
なる補正回路選択手段（２）と、この補正回路選択手段
（２）を構成するＮチャネル電界効果トランジスタのド
レインにソースが接続され、前記の第１の制御信号伝達
手段（４）を構成するトランジスタのゲートにゲートが
接続され、前記の第１の制御信号伝達手段（４）の出力
端子にドレインが接続されている第２の制御信号伝達手
段（３）とよりなる半導体装置。C. A conductivity type discrimination region (P type diffusion region formed on the same substrate as the first control signal transmission means (4) composed of an N channel field effect transistor for receiving a control signal and supplying a potential to a load or a logic circuit ( 6)
And a correction circuit selecting means (N-channel field effect transistor) whose gate is connected to the P diffusion region of the conductivity type discriminating region (6) through a negative logic circuit (7) and whose source is connected to a low potential power source ( 2) and the source of the N-channel field effect transistor constituting the correction circuit selecting means (2) are connected to the source thereof, and the gate thereof is connected to the gate of the transistor constituting the first control signal transmitting means (4). And a second control signal transmission means (3) having a drain connected to the output terminal of the first control signal transmission means (4).
【００１１】第２の手段は、Ｐチャネル電界効果トラン
ジスタとＮチャネル電界効果トランジスタとの直列回路
よりなり、制御信号を受けて負荷に電位を供給する第３
の制御信号伝達手段（２０）と、この第３の制御信号伝
達手段（２０）のＰチャネル電界効果トランジスタと同
一基板に形成されたＮ拡散領域を有する導電形判別領域
（１）と、この導電形判別領域（１）にソースが接続さ
れ、前記のＰチャネルトランジスタのドレインにドレイ
ンが接続され、前記の制御信号をゲートに入力されるＰ
チャネル電界効果トランジスタよりなる第４の制御信号
伝達手段（８）と、前記の第３の制御信号伝達手段（２
０）のＮチャネル電界効果トランジスタと同一基板に形
成されたＰ拡散領域を有する導電形判別領域（６）と、
この導電形判別領域（６）にソースが接続され、前記の
Ｎチャネルトランジスタのドレインにドレインが接続さ
れ、前記の制御信号をゲートに入力されるＮチャネル電
界効果トランジスタよりなる第５の制御信号伝達手段
（９）とを有する半導体装置である。The second means comprises a series circuit of a P-channel field effect transistor and an N-channel field effect transistor, and receives a control signal and supplies a potential to the load.
Control signal transmitting means (20), a conductivity type discriminating region (1) having an N diffusion region formed on the same substrate as the P channel field effect transistor of the third control signal transmitting means (20), and the conductivity type discriminating region (1). The source is connected to the shape determining region (1), the drain is connected to the drain of the P-channel transistor, and the control signal is input to the gate of P.
A fourth control signal transmission means (8) comprising a channel field effect transistor and the third control signal transmission means (2).
0) a conductivity type discriminating region (6) having a P diffusion region formed on the same substrate as the N-channel field effect transistor,
A source is connected to the conductivity type discriminating region (6), a drain is connected to the drain of the N-channel transistor, and a fifth control signal transmission is formed of an N-channel field effect transistor whose gate receives the control signal. A semiconductor device having means (9).
【００１２】[0012]
【作用】本発明に係る素子特性自己補正回路において
は、導電形判別領域が基板の導電形に対応して自動的に
高電位または低電位を持つので、この導電形判別領域に
ゲートが直接または否定論理回路を介して接続される電
界効果トランジスタよりなる補正回路選択手段が基板の
導電形に対応してオンまたはオフする。この補正回路選
択手段と第２の制御信号伝達手段との直列回路が第１の
制御信号伝達手段に並列に接続されているので、上記の
補正回路選択手段のオン・オフによって、第２の制御信
号伝達手段が基板導電形に対応して、第１の制御信号伝
達手段に自動的に付加されたり付加されなかったりす
る。したがって、基板の導電形が相違していても素子特
性が自動的に補正されるので、同一の半導体回路の特性
を同一にすることができる。In the device characteristic self-correction circuit according to the present invention, the conductivity type discriminating region automatically has a high potential or a low potential corresponding to the conductivity type of the substrate. The correction circuit selecting means, which is composed of a field effect transistor and is connected through a negative logic circuit, is turned on or off according to the conductivity type of the substrate. Since the series circuit of the correction circuit selecting means and the second control signal transmitting means is connected in parallel to the first control signal transmitting means, the second control is performed by turning on / off the correction circuit selecting means. The signal transmission means may or may not be automatically added to the first control signal transmission means, depending on the substrate conductivity type. Therefore, even if the conductivity types of the substrates are different, the element characteristics are automatically corrected, so that the characteristics of the same semiconductor circuit can be made the same.
【００１３】[0013]
【実施例】以下、図面を参照して、本発明の５実施例に
係る半導体装置について説明する。EXAMPLE A semiconductor device according to Example 5 of the present invention will be described below with reference to the drawings.
【００１４】図１は本発明の第１実施例（請求項２に対
応）に係る半導体装置の回路構成説明図であり、図２は
図１の回路がＮ基板に形成される場合の基板断面図（部
分）であり、図３は図１の回路がＰ基板に形成される場
合の基板断面図（部分）である。FIG. 1 is an explanatory view of a circuit configuration of a semiconductor device according to a first embodiment (corresponding to claim 2) of the present invention. FIG. 2 is a substrate cross section in the case where the circuit of FIG. 1 is formed on an N substrate. 3 is a diagram (portion), and FIG. 3 is a substrate cross-sectional view (portion) when the circuit of FIG. 1 is formed on a P substrate.
【００１５】図１・図２・図３参照 図において、１は、制御信号を受けて負荷または論理回
路５に対して電位を供給するＰチャネル電界効果トラン
ジスタよりなる第１の制御信号伝達手段４が形成されて
いるＮ形基板またはＰ形基板に形成されるＮ拡散領域を
有する導電形判別領域である。２は、この導電形判別領
域１にゲートが接続され、ソースは高電位電源ＶＤＤに
接続されるＰチャネル電界効果トランジスタよりなる補
正回路選択手段である。３は、この補正回路選択手段２
を構成するＰチャネル電界効果トランジスタのドレイン
にソースが接続され、上記の第１の制御信号伝達手段４
を構成する電界効果トランジスタのゲートにゲートが接
続され、上記の第１の制御信号伝達手段４の出力端子に
ドレインが接続されている第２の制御信号伝達手段であ
る。ＶＤＤは高電位電源であり、ＶＳＳは低電位電源で
ある。Referring to FIGS. 1, 2 and 3, reference numeral 1 denotes a first control signal transmitting means 4 which is a P-channel field effect transistor for receiving a control signal and supplying a potential to the load or the logic circuit 5. Is a conductivity type discriminating region having an N diffusion region formed on the N-type substrate or the P-type substrate in which is formed. Reference numeral 2 is a correction circuit selecting means having a gate connected to the conductivity type discriminating region 1 and a source connected to the high potential power supply VDD and comprising a P-channel field effect transistor. 3 is this correction circuit selection means 2
The source is connected to the drain of the P-channel field effect transistor that constitutes the
Is a second control signal transmission means having a gate connected to the gate of the field effect transistor constituting the above, and a drain connected to the output terminal of the first control signal transmission means 4 described above. VDD is a high potential power source and VSS is a low potential power source.
【００１６】つぎに、本実施例の動作について説明す
る。第１の制御信号伝達手段４が形成されている基板が
Ｎ形基板の場合（図２）においては、導電形判別領域１
の電位は基板電位と同一の高電位となるので、補正回路
選択手段２を構成する電界効果トランジスタはオフし、
第２の制御信号伝達手段３は第１の制御信号伝達手段４
に並列接続されない。また、第１の制御信号伝達手段４
が形成されている基板がＰ形基板の場合（図３）におい
ては、導電形判別領域１と基板とでダイオードを形成す
るが、導電形判別領域１と基板との間に流れるリーク電
流によって導電形判別領域１はＰ形基板と同じ低電位と
なり補正回路選択手段２を構成するトランジスタはオン
し、第２の制御信号伝達手段３は第１の制御信号伝達手
段４に並列に接続されることになる。したがって、基板
の導電形に対応して第２の制御信号伝達手段３が自動的
に、接続・非接続されるので、基板導電形が異なって
も、素子特性が自動的に補正されるから半導体回路の特
性を同一にすることができる。Next, the operation of this embodiment will be described. In the case where the substrate on which the first control signal transmitting means 4 is formed is the N-type substrate (FIG. 2), the conductivity type discrimination area 1
Since the potential of is the same high potential as the substrate potential, the field effect transistor constituting the correction circuit selecting means 2 is turned off,
The second control signal transmitting means 3 is the first control signal transmitting means 4
Is not connected in parallel. Also, the first control signal transmission means 4
In the case where the substrate on which is formed is a P-type substrate (FIG. 3), a diode is formed between the conductivity type determination region 1 and the substrate, but the conductivity is determined by the leakage current flowing between the conductivity type determination region 1 and the substrate. The shape determination area 1 has the same low potential as the P-type substrate, the transistor forming the correction circuit selecting means 2 is turned on, and the second control signal transmitting means 3 is connected in parallel to the first control signal transmitting means 4. become. Therefore, since the second control signal transmitting means 3 is automatically connected / disconnected according to the conductivity type of the substrate, the element characteristic is automatically corrected even if the conductivity type of the substrate is different. The characteristics of the circuits can be the same.
【００１７】ここでは、補正回路選択手段２の電界効果
トランジスタがオフのとき、基板と導電形判別領域は共
にＮ形であるから、この基板と導電形判別領域との関係
時に、必要なコンダクタンスを、第１の制御信号伝達手
段４を構成する電界効果トランジスタに設定しておく。
また、補正回路選択手段２の電界効果トランジスタがオ
ンのとき、基板と導電形判別領域は導電形が共に異なっ
ているから、この場合は、第１の制御信号伝達手段４を
構成する電界効果トランジスタのコンダクタンスと補正
回路選択手段２を構成する電界効果トランジスタと第２
の制御信号伝達手段３を構成する電界効果トランジスタ
との合成したコンダクタンスとの合成されたコンダクタ
ンスを、この基板と導電形判別領域との関係時に必要な
コンダクタンスとして設定しておく。Here, when the field effect transistor of the correction circuit selecting means 2 is off, both the substrate and the conductivity type discriminating region are N type, so that the necessary conductance is obtained when the substrate and the conductivity type discriminating region are related. , The first control signal transmitting means 4 is set in the field effect transistor.
Further, when the field effect transistor of the correction circuit selection means 2 is on, the conductivity type of the substrate is different from that of the conductivity type discrimination area. In this case, therefore, the field effect transistor constituting the first control signal transmission means 4 is formed. And a field-effect transistor which constitutes the correction circuit selecting means 2
The combined conductance with the combined conductance of the field effect transistor constituting the control signal transmission means 3 is set as a conductance necessary for the relationship between the substrate and the conductivity type discrimination region.
【００１８】図４は、本発明の第２実施例（請求項３に
対応）に係る半導体装置の回路構成説明図である。FIG. 4 is an explanatory diagram of a circuit configuration of a semiconductor device according to a second embodiment (corresponding to claim 3) of the present invention.
【００１９】図４参照 本実施例が第１実施例と相違する点は、第１実施例にお
けるＮ拡散領域が本実施例においては、Ｐ拡散領域であ
り、このＰ拡散領域が否定論理回路を介して補正回路選
択手段のゲートに接続されている点のみである。FIG. 4 is different from the first embodiment in that the N diffusion region in the first embodiment is a P diffusion region in this embodiment, and this P diffusion region is a negative logic circuit. It is only connected to the gate of the correction circuit selecting means via the.
【００２０】図において、６は第１の制御信号伝達手段
４と同一に基板に形成されたＰ拡散領域を有する導電形
判別領域であり、７は入力端子がこの導電形判別領域６
に接続され、出力端子が補正回路選択手段２のゲートに
接続される否定論理回路である。他の符号の説明は第１
実施例の場合と同一なので省略する。In the figure, 6 is a conductivity type discriminating region having a P diffusion region formed on the same substrate as the first control signal transmitting means 4, and 7 is an input terminal of this conductivity type discriminating region 6.
Is a negative logic circuit whose output terminal is connected to the gate of the correction circuit selecting means 2. Description of other symbols is first
Since it is the same as the case of the embodiment, it is omitted.
【００２１】つぎに、本実施例の動作について説明す
る。第１の制御信号伝達手段４が形成されている基板が
Ｎ形基板の場合は、導電形判別領域６とＮ形基板とでダ
イオードを形成するが導電形判別領域６と基板との間に
流れるリーク電流によって、導電形判別領域６はＮ形基
板と同一の高電位となる。したがって、否定論理回路７
を介して上記の導電形判別領域６に接続されている補正
回路選択手段２のゲートは低電位となり、補正回路選択
手段２はオンし、第２の制御信号伝達手段３は第１の制
御信号伝達手段４に並列に接続されることになる。ま
た、第１の制御信号伝達手段４が形成されている基板が
Ｐ形基板の場合は、導電形判別領域６は基板と同一電位
の低電位となるので、補正回路選択手段２のゲートは高
電位となり、補正回路選択手段２はオフする。したがっ
て、第２の制御信号伝達手段３は第１の制御信号伝達手
段４に並列に接続されない。よって、基板の導電形に対
応して第２の制御信号伝達手段３が自動的に接続・非接
続されるので、基板導電形が異なっても半導体回路の特
性を同一にすることができる。Next, the operation of this embodiment will be described. When the substrate on which the first control signal transmitting means 4 is formed is an N type substrate, a diode is formed between the conductivity type discriminating region 6 and the N type substrate, but the diode flows between the conductivity type discriminating region 6 and the substrate. Due to the leak current, the conductivity type discrimination region 6 has the same high potential as that of the N-type substrate. Therefore, the negative logic circuit 7
The gate of the correction circuit selecting means 2 connected to the conductivity type discriminating region 6 via the above becomes low potential, the correction circuit selecting means 2 is turned on, and the second control signal transmitting means 3 is set to the first control signal. It will be connected in parallel to the transmission means 4. If the substrate on which the first control signal transmission means 4 is formed is a P-type substrate, the conductivity type discrimination region 6 has the same low potential as the substrate, so the gate of the correction circuit selection means 2 is high. The potential becomes the potential, and the correction circuit selection means 2 is turned off. Therefore, the second control signal transmission means 3 is not connected in parallel to the first control signal transmission means 4. Therefore, since the second control signal transmitting means 3 is automatically connected / disconnected according to the conductivity type of the substrate, the characteristics of the semiconductor circuit can be the same even if the conductivity type of the substrate is different.
【００２２】図５は、本発明の第３実施例（請求項４に
対応）に係る半導体装置の回路構成説明図である。FIG. 5 is an explanatory diagram of a circuit configuration of a semiconductor device according to a third embodiment (corresponding to claim 4) of the present invention.
【００２３】図５参照 図において、６は制御信号を受けて負荷または論理回路
５に信号を伝達するＮチャネル電界効果トランジスタよ
りなる第１の制御信号伝達手段４が形成されているＰ形
基板またはＮ形基板に形成されるＰ拡散領域を有する導
電形判別領域である。７は入力端子がこの導電形判別領
域６に接続される否定論理回路である。２は、この否定
論理回路７の出力端子にゲートが接続され、ソースは低
電位電源に接続されるＮチャネル電界効果トランジスタ
よりなる補正回路選択手段である。３は、この補正回路
選択手段２を構成する電界効果トランジスタのドレイン
にソースが接続され、上記の第１の制御信号伝達手段４
を構成するトランジスタのゲートにゲートが接続され、
上記の第１の制御信号伝達手段４の出力端子にドレイン
が接続されている第２の制御信号伝達手段である。Referring to FIG. 5, reference numeral 6 denotes a P-type substrate in which a first control signal transmission means 4 composed of an N-channel field effect transistor for receiving a control signal and transmitting the signal to the load or the logic circuit 5 is formed. This is a conductivity type discrimination region having a P diffusion region formed on an N-type substrate. Reference numeral 7 is a negative logic circuit whose input terminal is connected to the conductivity type discrimination area 6. Reference numeral 2 is a correction circuit selecting means having an N-channel field effect transistor whose gate is connected to the output terminal of the NOT logic circuit 7 and whose source is connected to the low potential power source. The source of the field effect transistor 3 is connected to the field effect transistor constituting the correction circuit selecting means 2, and the first control signal transmitting means 4 is provided.
The gate is connected to the gate of the transistor
This is a second control signal transmission means in which the drain is connected to the output terminal of the first control signal transmission means 4.
【００２４】つぎに、本実施例の動作について説明す
る。第１の制御信号伝達手段４が形成されている基板が
Ｎ形基板の場合は、導電形判別領域６と基板とでダイオ
ードを形成するが導電形判別領域６と基板との間に流れ
るリーク電流によって、導電形判別領域６はＮ形基板と
同一の高電位となり、この導電形判別領域６に否定論理
回路７を介して接続される補正回路選択手段２のゲート
は低電位となるので、補正回路選択手段２はオフし、第
２の制御信号伝達手段３は第１の制御信号伝達手段４と
並列接続されない。また、第１の制御信号伝達手段４が
形成されている基板がＰ形基板の場合は、導電形判別領
域６は基板と同一の低電位となり、この導電形判別領域
６に否定論理回路７を介して接続される補正回路選択手
段２のゲートは高電位となるので、補正回路選択手段２
はオンし、第２の制御信号伝達手段３は第１の制御信号
伝達手段４と並列に接続されることになる。したがっ
て、基板の導電形に対応して第２の制御信号伝達手段３
が自動的に接続・非接続されるので、基板導電形が異な
っても半導体回路の特性を同一にすることができる。Next, the operation of this embodiment will be described. When the substrate on which the first control signal transmission means 4 is formed is an N-type substrate, a diode is formed between the conductivity type identification region 6 and the substrate, but a leak current flowing between the conductivity type identification region 6 and the substrate. As a result, the conductivity type discriminating region 6 has the same high potential as that of the N-type substrate, and the gate of the correction circuit selecting means 2 connected to the conductivity type discriminating region 6 via the negative logic circuit 7 has a low potential. The circuit selecting means 2 is turned off, and the second control signal transmitting means 3 is not connected in parallel with the first control signal transmitting means 4. When the substrate on which the first control signal transmitting means 4 is formed is a P-type substrate, the conductivity type discriminating region 6 has the same low potential as the substrate, and the negative logic circuit 7 is placed in the conductivity type discriminating region 6. Since the gate of the correction circuit selection means 2 connected via the high potential, the correction circuit selection means 2
Is turned on, and the second control signal transmitting means 3 is connected in parallel with the first control signal transmitting means 4. Therefore, the second control signal transmitting means 3 corresponding to the conductivity type of the substrate.
Are automatically connected / disconnected, the semiconductor circuit characteristics can be made the same even if the substrate conductivity types are different.
【００２５】図６は、本発明の第４実施例に係る半導体
装置の回路構成説明図である。FIG. 6 is an explanatory diagram of a circuit configuration of a semiconductor device according to the fourth embodiment of the present invention.
【００２６】図６参照 本実施例が第３実施例と相違する点は、第３実施例にお
けるＰ拡散領域を有する導電形判別領域が否定論理回路
を介して補正回路選択手段のトランジスタのゲートに接
続されるのに対し、本実施例においては、Ｎ拡散領域を
有する導電形判別領域が補正回路選択手段のトランジス
タのゲートに直接、接続される点のみである。Referring to FIG. 6, this embodiment is different from the third embodiment in that the conductivity type discrimination region having the P diffusion region in the third embodiment is connected to the gate of the transistor of the correction circuit selecting means through the negative logic circuit. In contrast to the connection, in the present embodiment, the conductivity type discrimination region having the N diffusion region is directly connected to the gate of the transistor of the correction circuit selecting means.
【００２７】図において、１は第１の制御信号伝達手段
４が形成されている基板に形成されるＮ拡散領域を有す
る導電形判別領域である。他の符号の説明は第３実施例
の場合と同一なので省略する。In the figure, reference numeral 1 is a conductivity type discriminating region having an N diffusion region formed on the substrate on which the first control signal transmitting means 4 is formed. The description of the other reference numerals is the same as that of the third embodiment and will not be repeated.
【００２８】つぎに、本実施例の動作について説明す
る。第１の制御信号伝達手段４がＮ形基板の場合におい
ては、導電形判別領域１の電位は基板電位と同一の高電
位となるので、補正回路選択手段２を構成する電界効果
トランジスタはオンし、第２の制御信号伝達手段３は第
１の制御信号伝達手段４と並列接続される。また、第１
の制御信号伝達手段４が形成されている基板がＰ形基板
の場合においては、導電形判別領域１と基板とでダイオ
ードを形成するが、導電形判別領域１と基板との間に流
れるリーク電流によって導電形判別領域１はＰ形基板と
同じ低電位となり補正回路選択手段２を構成するトラン
ジスタはオフし、第２の制御信号伝達手段３は第１の制
御信号伝達手段４と並列接続されない。したがって、基
板の導電形に対応して第２の制御信号伝達手段３が自動
的に接続・非接続されるので、基板導電形が異なっても
半導体回路の特性を同一にすることができる。Next, the operation of this embodiment will be described. When the first control signal transmission means 4 is an N-type substrate, the potential of the conductivity type discrimination region 1 becomes the same high potential as the substrate potential, so that the field effect transistor forming the correction circuit selection means 2 is turned on. , The second control signal transmitting means 3 is connected in parallel with the first control signal transmitting means 4. Also, the first
When the substrate on which the control signal transmitting means 4 is formed is a P-type substrate, a diode is formed between the conductivity type discrimination region 1 and the substrate, but a leak current flowing between the conductivity type discrimination region 1 and the substrate. As a result, the conductivity type discriminating region 1 has the same low potential as that of the P-type substrate, the transistor constituting the correction circuit selecting means 2 is turned off, and the second control signal transmitting means 3 is not connected in parallel with the first control signal transmitting means 4. Therefore, since the second control signal transmitting means 3 is automatically connected / disconnected according to the conductivity type of the substrate, the characteristics of the semiconductor circuit can be made the same even if the conductivity type of the substrate is different.
【００２９】なお、上記の導電形判別領域と補正回路選
択手段と否定論理回路の組み合わせは第１〜第４実施例
の場合も含めて表１に示すとおりである。第１〜第４実
施例以外のものについての説明は冗長を避けるために省
略する。The combinations of the conductivity type discriminating region, the correction circuit selecting means and the negative logic circuit are shown in Table 1 including the cases of the first to fourth embodiments. Descriptions other than those of the first to fourth embodiments are omitted to avoid redundancy.
【００３０】[0030]
【表１】 [Table 1]
【００３１】図７は本発明の第５実施例（請求項５に対
応）に係る半導体装置の回路構成説明図である。 図７参照 本実施例は、Ｐチャネル電界効果トランジスタとＮチャ
ネル電界効果トランジスタとが直列接続されてなる第３
の制御信号伝達手段２０において、このＰチャネル電界
効果トランジスタに対しては、このトランジスタと同一
基板に形成されたＮ拡散領域を有する導電形判別領域１
を、Ｐチャネル電界効果トランジスタよりなる第４の制
御信号伝達手段８のソースに接続し、また、上記の第３
の制御信号伝達手段２０を構成するＮチャネル電界効果
トランジスタに対しては、このトランジスタと同一基板
に形成されたＰ拡散領域を有する導電形判別領域６を、
Ｎチャネル電界効果トランジスタよりなる第５の制御信
号伝達手段９のソースに接続するものであって、上記の
第１〜第４実施例における補正回路選択手段２を省略し
たものである。FIG. 7 is an explanatory diagram of a circuit configuration of a semiconductor device according to a fifth embodiment (corresponding to claim 5) of the present invention. Refer to FIG. 7. In this embodiment, a P-channel field effect transistor and an N-channel field effect transistor are connected in series.
In the control signal transmitting means 20 of 1., for the P-channel field effect transistor, the conductivity type discriminating region 1 having an N diffusion region formed on the same substrate as the transistor is provided.
Is connected to the source of the fourth control signal transmission means 8 composed of a P-channel field effect transistor, and the third control signal transmission means 8 is connected to the source of the fourth control signal transmission means 8.
For the N-channel field effect transistor which constitutes the control signal transmitting means 20 of 1., the conductivity type discriminating region 6 having the P diffusion region formed on the same substrate as this transistor,
It is connected to the source of the fifth control signal transmission means 9 composed of an N-channel field effect transistor, and the correction circuit selection means 2 in the first to fourth embodiments is omitted.
【００３２】つぎに本実施例の動作について説明する。
第３の制御信号伝達手段２０を構成するＰチャネル電界
効果トランジスタ及びＮチャネル電界効果トランジスタ
が形成されている基板がＮ形基板の場合は、上記のＮ拡
散領域は、他の実施例で説明したように、Ｎ形基板と同
一の高電位となる。Ｐ拡散領域には電流の供給源が無く
なるので、回路動作に寄与しない。この場合、第４の制
御信号伝達手段８は第３の制御信号伝達手段２０のＰチ
ャネルトランジスタと並列接続され、補正動作に寄与す
るが、第５の制御信号伝達手段９を構成するトランジス
タは電流が流れないので、補正動作に寄与しなくなる。
また、基板がＰ形基板の場合は、上記のＰ拡散領域はＰ
形基板と同一の低電位となりＮ拡散領域には電流供給源
が無くなるので、第４の制御信号伝達手段８を構成する
トランジスタには電流が流れず、第４の制御信号伝達手
段８は補正動作に寄与しないが、第５の制御信号伝達手
段９は第３の制御信号伝達手段２０のＮチャネルトラン
ジスタと並列接続され補正動作に寄与する。すなわち、
基板がＮ形基板のときは第３の制御信号伝達手段２０の
Ｐチャネルトランジスタが補正され、基板がＰ形基板の
ときは第３の制御信号伝達手段２０のＮチャネルトラン
ジスタが補正されることになる。したがって、基板の導
電形が異なっても、それぞれの基板導電形に対応して素
子特性の補正が自動的に行われ、半導体回路の特性を基
板導電形に関わりなく同一にすることができる。Next, the operation of this embodiment will be described.
When the substrate on which the P-channel field effect transistor and the N-channel field effect transistor forming the third control signal transmitting means 20 are formed is an N-type substrate, the above N diffusion region has been described in the other embodiments. Thus, it has the same high potential as the N-type substrate. Since there is no current supply source in the P diffusion region, it does not contribute to the circuit operation. In this case, the fourth control signal transmitting means 8 is connected in parallel with the P-channel transistor of the third control signal transmitting means 20 and contributes to the correction operation, but the transistor constituting the fifth control signal transmitting means 9 is a current source. Does not flow, it does not contribute to the correction operation.
When the substrate is a P-type substrate, the P diffusion region is P
Since the potential is the same as that of the shaped substrate and there is no current supply source in the N diffusion region, no current flows through the transistor that constitutes the fourth control signal transmission means 8, and the fourth control signal transmission means 8 performs the correction operation. However, the fifth control signal transmission means 9 is connected in parallel with the N-channel transistor of the third control signal transmission means 20 and contributes to the correction operation. That is,
When the substrate is an N-type substrate, the P-channel transistor of the third control signal transmission means 20 is corrected, and when the substrate is a P-type substrate, the N-channel transistor of the third control signal transmission means 20 is corrected. Become. Therefore, even if the conductivity types of the substrates are different, the element characteristics are automatically corrected corresponding to each substrate conductivity type, and the characteristics of the semiconductor circuit can be made the same regardless of the substrate conductivity types.
【００３３】つぎに、本実施例のレイアウトについて説
明する。図８は図７の回路のレイアウトであり、制御信
号伝達手段８・９の一端は拡散層によって第３の制御信
号伝達手段２０のＰチャネルトランジスタ・Ｎチャネル
トランジスタの出力部に接続されており、制御信号伝達
手段８・９の他端は配線パターンを介して導電形判別領
域１・６に接続されている。第３の制御信号伝達手段２
０のＰチャネルトランジスタ・Ｎチャネルトランジスタ
は配線パターンを介して電源ＶＤＤ・ＶＳＳに接続され
る。Next, the layout of this embodiment will be described. FIG. 8 is a layout of the circuit of FIG. 7. One end of the control signal transmission means 8 and 9 is connected to the output portions of the P-channel transistor and the N-channel transistor of the third control signal transmission means 20 by a diffusion layer. The other ends of the control signal transmitting means 8 and 9 are connected to the conductivity type discriminating regions 1 and 6 via a wiring pattern. Third control signal transmission means 2
The 0 P-channel transistor / N-channel transistor is connected to the power supply VDD / VSS through the wiring pattern.
【００３４】図９は本実施例の応用例のレイアウトであ
り、第３の制御信号伝達手段と第４及び第５の制御信号
伝達手段との組の複数に対して導電形判別領域の組（Ｎ
拡散領域とＰ拡散領域との組）１個を使用する場合のレ
イアウトである。FIG. 9 is a layout of an application example of the present embodiment, in which a set of conductivity type discriminating regions (for a plurality of sets of the third control signal transmitting means and the fourth and fifth control signal transmitting means). N
This is a layout in the case where only one diffusion region and one P diffusion region are used.
【００３５】[0035]
【発明の効果】以上説明したように、本発明に係る半導
体装置においては、第１の制御信号伝達手段と同一基板
上に導電形判別領域が形成されていて基板導電形に対応
して自動的に高電位または低電位を持つことにより、こ
の導電形判別領域にゲートが直接または否定論理回路を
介して接続されているトランジスタよりなる補正回路選
択手段が基板の導電形に対応して自動的にオン・オフさ
せることができるので、この補正回路選択手段と直列接
続された第２の制御信号伝達手段を基板導電形に対応し
て上記の第１の制御信号伝達手段に並列接続するので、
半導体回路の特性を基板の導電形に関係なく同一となす
ことができる。As described above, in the semiconductor device according to the present invention, the conductivity type discriminating area is formed on the same substrate as the first control signal transmitting means, so that the conductivity type is automatically determined according to the substrate conductivity type. By having a high potential or a low potential, the correction circuit selection means consisting of a transistor whose gate is connected to this conductivity type discrimination area directly or through a negative logic circuit automatically corresponds to the conductivity type of the substrate. Since it can be turned on / off, the second control signal transmitting means connected in series with the correction circuit selecting means is connected in parallel to the first control signal transmitting means corresponding to the substrate conductivity type.
The characteristics of the semiconductor circuit can be the same regardless of the conductivity type of the substrate.
【００３６】また、本発明に係る他の半導体装置におい
ては、Ｐチャネル電界効果トランジスタとＮチャネル電
界効果トランジスタとの直列回路よりなる第３の制御信
号伝達手段と同一基板にＮ拡散領域とＰ拡散領域とが形
成され、このＮ拡散領域にソースが接続された第４の制
御信号伝達手段とＰ拡散領域にソースが接続された第５
の制御信号伝達手段とが基板導電形に対応して自動的に
上記の第３の制御信号伝達手段と並列に負荷に電位を供
給することで、半導体回路の特性を基板の導電形に関係
なく同一となすことができる。Further, in another semiconductor device according to the present invention, the N diffusion region and the P diffusion region are formed on the same substrate as the third control signal transmitting means including a series circuit of the P channel field effect transistor and the N channel field effect transistor. A fourth control signal transmitting means having a region formed therein, the source being connected to the N diffusion region, and a fifth source having a source connected to the P diffusion region.
Control signal transmitting means automatically supplies a potential to the load in parallel with the third control signal transmitting means in correspondence with the substrate conductivity type so that the characteristics of the semiconductor circuit are independent of the substrate conductivity type. Can be the same.
【００３７】したがって、本発明は、基板の導電形を自
動的に判別し、半導体素子の特性を基板導電形に適合す
るように自動的に補正することができる半導体装置を提
供することができる。Therefore, the present invention can provide a semiconductor device capable of automatically determining the conductivity type of a substrate and automatically correcting the characteristics of a semiconductor element so as to match the conductivity type of the substrate.
【図１】本発明の第１実施例に係る半導体装置の回路構
成説明図である。FIG. 1 is a circuit configuration explanatory diagram of a semiconductor device according to a first exemplary embodiment of the present invention.
【図２】図１の回路が形成されたＮ形基板断面図（部
分）である。FIG. 2 is a sectional view (portion) of an N-type substrate on which the circuit of FIG. 1 is formed.
【図３】図１の回路が形成されたＰ形基板断面図（部
分）である。3 is a sectional view (portion) of a P-type substrate on which the circuit of FIG. 1 is formed.
【図４】本発明の第２実施例に係る半導体装置の回路構
成説明図である。FIG. 4 is an explanatory diagram of a circuit configuration of a semiconductor device according to a second exemplary embodiment of the present invention.
【図５】本発明の第３実施例に係る半導体装置の回路構
成説明図である。FIG. 5 is an explanatory diagram of a circuit configuration of a semiconductor device according to a third exemplary embodiment of the present invention.
【図６】本発明の第４実施例に係る半導体装置の回路構
成説明図である。FIG. 6 is an explanatory diagram of a circuit configuration of a semiconductor device according to a fourth exemplary embodiment of the present invention.
【図７】本発明の第５実施例に係る半導体装置の回路構
成説明図である。FIG. 7 is an explanatory diagram of a circuit configuration of a semiconductor device according to a fifth exemplary embodiment of the present invention.
【図８】本発明の第５実施例のレイアウト図である。FIG. 8 is a layout diagram of a fifth embodiment of the present invention.
【図９】本発明の第５実施例の応用例のレイアウト図で
ある。FIG. 9 is a layout diagram of an application example of the fifth embodiment of the present invention.
１ 導電形判別領域（Ｎ拡散領域） ２ 補正回路選択手段 ３ 第２の制御信号伝達手段 ４ 第１の制御信号伝達手段 ５ 負荷または論理回路（Ｎチャネルトランジスタ） ６ 導電形判別領域（Ｐ拡散領域） ７ 否定論理回路 ８ 第４の制御信号伝達手段 ９ 第５の制御信号伝達手段 ２０ 第３の制御信号伝達手段（Ｐチャネルトランジ
スタとＮチャネルトランジスタの直列回路）1 Conduction Type Discrimination Region (N Diffusion Region) 2 Correction Circuit Selection Means 3 Second Control Signal Transmission Means 4 First Control Signal Transmission Means 5 Load or Logic Circuit (N Channel Transistor) 6 Conduction Types Discrimination Region (P Diffusion Region) ) 7 Negative logic circuit 8 Fourth control signal transmission means 9 Fifth control signal transmission means 20 Third control signal transmission means (serial circuit of P-channel transistor and N-channel transistor)
Claims (5)
（５）に対して電位を供給する第１の制御信号伝達手段
（４）と、 前記第１の制御信号伝達手段（４）と並列に接続され、
制御信号を受けて、負荷または論理回路（５）に対して
電位を供給する第２の制御信号伝達手段（３）と、 基板内に形成された拡散領域の電位に応答してオン又は
オフし、前記第２の制御信号伝達手段（３）への電位の
供給を制御する補正回路選択手段（２）とを有すること
を特徴とする半導体装置。1. A first control signal transmission means (4) for receiving a control signal and supplying an electric potential to a load or a logic circuit (5), and in parallel with the first control signal transmission means (4). Connected,
Second control signal transmitting means (3) for receiving a control signal and supplying a potential to the load or the logic circuit (5), and turning on or off in response to the potential of the diffusion region formed in the substrate. And a correction circuit selecting means (2) for controlling the supply of the potential to the second control signal transmitting means (3).
対して電位を供給するＰチャネル電界効果トランジスタ
よりなる第１の制御信号伝達手段（４）と同一基板に形
成されるＮ拡散領域を有する導電形判別領域（１）と、 該導電形判別領域（１）のＮ拡散領域にゲートが接続さ
れ、ソースは高電位電源に接続されるＰチャネル電界効
果トランジスタよりなる補正回路選択手段（２）と、 該補正回路選択手段（２）を構成するＰチャネル電界効
果トランジスタのドレインにソースが接続され、前記第
１の制御信号伝達手段（４）を構成するトランジスタの
ゲートにゲートが接続され、前記第１の制御信号伝達手
段（４）の出力端子にドレインが接続されてなる第２の
制御信号伝達手段（３）とよりなることを特徴とする請
求項１記載の半導体装置。2. An N diffusion region formed on the same substrate as a first control signal transmission means (4) composed of a P-channel field effect transistor for receiving a control signal and supplying a potential to a load or a logic circuit. Correction circuit selecting means (2) comprising a conductivity type discrimination region (1) and a P-channel field effect transistor having a gate connected to the N diffusion region of the conductivity type determination region (1) and a source connected to a high potential power source. A source of the P-channel field effect transistor constituting the correction circuit selecting means (2) is connected to a source thereof, and a gate thereof is connected to a gate of a transistor constituting the first control signal transmitting means (4), 2. The semiconductor according to claim 1, further comprising a second control signal transmission means (3) having a drain connected to an output terminal of the first control signal transmission means (4). Location.
対して電位を供給するＰチャネル電界効果トランジスタ
よりなる第１の制御信号伝達手段（４）と同一基板に形
成されるＰ拡散領域を有する導電形判別領域（６）と、 該導電形判別領域（６）のＰ拡散領域に否定論理回路
（７）を介してゲートが接続されソースは高電位電源に
接続されるＰチャネル電界効果トランジスタよりなる補
正回路選択手段（２）と、 該補正回路選択手段（２）を構成するＰチャネル電界効
果トランジスタのドレインにソースが接続され、前記第
１の制御信号伝達手段（４）を構成するトランジスタの
ゲートにゲートが接続され、前記第１の制御信号伝達手
段（４）の出力端子にドレインが接続されてなる第２の
制御信号伝達手段（３）とよりなることを特徴とする請
求項１記載の半導体装置。3. A P diffusion region formed on the same substrate as a first control signal transmission means (4) comprising a P channel field effect transistor for receiving a control signal and supplying a potential to a load or a logic circuit. A conductivity type discriminating region (6) and a P channel field effect transistor whose gate is connected to the P diffusion region of the conductivity type discriminating region (6) through a negative logic circuit (7) and whose source is connected to a high potential power source. And a source of the P-channel field effect transistor forming the correction circuit selecting means (2), the source of which is connected to the first control signal transmitting means (4). A second control signal transmission means (3) having a gate connected to the gate and a drain connected to the output terminal of the first control signal transmission means (4). The semiconductor device of claim 1, wherein that.
対して電位を供給するＮチャネル電界効果トランジスタ
よりなる第１の制御信号伝達手段（４）と同一基板に形
成されるＰ拡散領域を有する導電形判別領域（６）と、 該導電形判別領域（６）のＰ拡散領域に否定論理回路
（７）を介してゲートが接続され、ソースは低電位電源
に接続されるＮチャネル電界効果トランジスタよりなる
補正回路選択手段（２）と、 該補正回路選択手段（２）を構成するＮチャネル電界効
果トランジスタのドレインにソースが接続され、前記第
１の制御信号伝達手段（４）を構成するトランジスタの
ゲートにゲートが接続され、前記第１の制御信号伝達手
段（４）の出力端子にドレインが接続されてなる第２の
制御信号伝達手段（３）とよりなることを特徴とする請
求項１記載の半導体装置。4. A P diffusion region formed on the same substrate as a first control signal transmission means (4) comprising an N channel field effect transistor which receives a control signal and supplies a potential to a load or a logic circuit. An N-channel field effect transistor in which a gate is connected to a conductivity type discriminating region (6) and a P diffusion region of the conductivity type discriminating region (6) through a negative logic circuit (7), and a source is connected to a low potential power source. A correction circuit selecting means (2), and a transistor forming the first control signal transmitting means (4), the source of which is connected to the drain of the N-channel field effect transistor forming the correction circuit selecting means (2). A second control signal transmission means (3) having a gate connected to the gate of the first control signal transmission means and a drain connected to the output terminal of the first control signal transmission means (4). The semiconductor device according to claim 1.
ャネル電界効果トランジスタとの直列回路よりなり、制
御信号を受けて負荷に電位を供給する第３の制御信号伝
達手段（２０）と、 該第３の制御信号伝達手段（２０）のＰチャネル電界効
果トランジスタと同一基板に形成されたＮ拡散領域を有
する導電形判別領域（１）と、 該導電形判別領域（１）にソースが接続され、前記Ｐチ
ャネルトランジスタのドレインにドレインが接続され、
前記制御信号をゲートに入力されるＰチャネル電界効果
トランジスタよりなる第４の制御信号伝達手段（８）
と、 前記第３の制御信号伝達手段（２０）のＮチャネル電界
効果トランジスタと同一基板に形成されたＰ拡散領域を
有する導電形判別領域（６）と、 該導電形判別領域（６）にソースが接続され、前記Ｎチ
ャネルトランジスタのドレインにドレインが接続され、
前記制御信号をゲートに入力されるＮチャネル電界効果
トランジスタよりなる第５の制御信号伝達手段（９）と
を有することを特徴とする半導体装置。5. A third control signal transmission means (20) comprising a series circuit of a P-channel field effect transistor and an N-channel field effect transistor and receiving a control signal to supply a potential to a load, and the third control signal transmission means (20). A conductivity type discrimination region (1) having an N diffusion region formed on the same substrate as the P channel field effect transistor of the control signal transmission means (20), and a source connected to the conduction type discrimination region (1), The drain is connected to the drain of the channel transistor,
Fourth control signal transmission means (8) comprising a P-channel field effect transistor for inputting the control signal to its gate
A conductive type discriminating region (6) having a P diffusion region formed on the same substrate as the N-channel field effect transistor of the third control signal transmitting means (20), and a source in the conductive type discriminating region (6). Is connected to the drain of the N-channel transistor,
A semiconductor device comprising: a fifth control signal transmission means (9) comprising an N-channel field effect transistor having the control signal input to its gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4294691A JPH06151739A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4294691A JPH06151739A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06151739A true JPH06151739A (en) | 1994-05-31 |
Family
ID=17811062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4294691A Withdrawn JPH06151739A (en) | 1992-11-04 | 1992-11-04 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06151739A (en) |
-
1992
- 1992-11-04 JP JP4294691A patent/JPH06151739A/en not_active Withdrawn
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20000104 |