JPH0613590A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0613590A JPH0613590A JP19337092A JP19337092A JPH0613590A JP H0613590 A JPH0613590 A JP H0613590A JP 19337092 A JP19337092 A JP 19337092A JP 19337092 A JP19337092 A JP 19337092A JP H0613590 A JPH0613590 A JP H0613590A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- layer
- distance
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に基本回路のセルが複数個搭載されたマスタス
ライス方式の半導体集積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a master slice type semiconductor integrated circuit device having a plurality of basic circuit cells mounted thereon.
【０００２】[0002]
【従来の技術】マスタスライス方式の半導体集積回路装
置では、基本回路を構成するセルが複数個配置され、セ
ル間が複数層の配線によって接続されている。これらの
配線層については各配線層毎にそれぞれ配線ピッチ、配
線幅および配線膜厚の基準が定められている。一般に配
線基準は下層では細かく上層にいく程広くなっている。
それは、上層にいく程下層の配線層の影響を受けて平坦
化されなくなるため、微細加工が困難になるからであ
る。2. Description of the Related Art In a master slice type semiconductor integrated circuit device, a plurality of cells forming a basic circuit are arranged, and the cells are connected by wirings of a plurality of layers. With respect to these wiring layers, the wiring pitch, wiring width, and wiring film thickness standards are set for each wiring layer. In general, the wiring standard is finer in the lower layer and wider in the upper layer.
The reason for this is that as it goes up, it is not flattened by the influence of the lower wiring layer, which makes fine processing difficult.
【０００３】従来の半導体集積回路装置においては、セ
ル間の配線は、配線が最短距離になるように配線層を選
び、上記配線基準に従って敷設されていた。In a conventional semiconductor integrated circuit device, wiring between cells is laid according to the above wiring standard by selecting a wiring layer so that the wiring has the shortest distance.
【０００４】[0004]
【発明が解決しようとする課題】近年の半導体集積回路
装置では、回路の大規模化のため、チップ面積が増大し
て最大配線長が長くなる傾向にある。一方で、高集積化
の要請に応えるため、配線は一層微細化されつつあり、
そのため単位長当たりの配線抵抗は増加傾向にある。In recent semiconductor integrated circuit devices, there is a tendency for the chip area to increase and the maximum wiring length to increase due to the large scale of the circuit. On the other hand, in order to meet the demand for high integration, wiring is becoming finer,
Therefore, the wiring resistance per unit length tends to increase.
【０００５】これらの理由により近年、配線遅延が顕著
になってきているが、このような状況下にあって、従来
は配線経路を最短距離にとることのみで、有効な配線遅
延対策は立てられていなかったため、配線長が長い場合
には、極端な配線遅延を伴う個所が生じ、最悪の場合に
は回路が駆動しきれなくなるという問題が起る。而し
て、半導体集積回路を高速動作させるためには、最大配
線遅延を短縮し、部分的に極端な遅延の生じるのを回避
することが有効である。For these reasons, wiring delays have become remarkable in recent years. Under such circumstances, however, conventionally, an effective wiring delay countermeasure can be established only by taking the shortest wiring route. Therefore, when the wiring length is long, there is a portion with an extreme wiring delay, and in the worst case, the circuit cannot be driven completely. Therefore, in order to operate the semiconductor integrated circuit at a high speed, it is effective to shorten the maximum wiring delay and avoid the occurrence of a partial delay.
【０００６】よって、本発明の目的とするところは、配
線長の長い部分での配線遅延を短縮して集積回路内全体
の配線遅延を平準化することにより、半導体集積回路の
高速動作を可能ならしめることである。Therefore, an object of the present invention is to reduce the wiring delay in a portion having a long wiring length and level the wiring delay in the entire integrated circuit, so that high-speed operation of the semiconductor integrated circuit is possible. It is to tighten.
【０００７】[0007]
【課題を解決するための手段】本発明の半導体集積回路
は、各々異なる基準を有する複数配線層でセル間の配線
を行うものであって、その際規定値を超える長さの配線
には上層にある配線層を用い、規定値以下の長さの配線
には下層にある配線層を用いるものである。A semiconductor integrated circuit according to the present invention is for wiring between cells in a plurality of wiring layers each having a different reference, in which case a wiring having a length exceeding a specified value is provided with an upper layer. The wiring layer in FIG. 3 is used, and the wiring layer in the lower layer is used for wiring having a length equal to or shorter than the specified value.
【０００８】[0008]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。図１、図２は、本発明の実施例を説明する
ための断面図である。図１には配線方向が交互に変わる
例が、また、図２には配線方向が同一方向である例が示
されている。Embodiments of the present invention will now be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining an embodiment of the present invention. FIG. 1 shows an example in which the wiring directions alternate, and FIG. 2 shows an example in which the wiring directions are the same.
【０００９】図１、図２に示されるように、半導体基板
５上に、絶縁膜６、７を介して配線層１、２、３、４が
形成されている。各配線層１、２、３、４は、各々ピッ
チｐ1 、ｐ2 、ｐ3 、ｐ4 、配線幅ｗ1 、ｗ2 、ｗ3 、
ｗ4 、配線膜厚ｔ1 、ｔ2 、ｔ3 、ｔ4 の配線基準に従
って形成されている。ここに示されるように、配線基準
は下層で細かく、上層にいく程粗くなっている。As shown in FIGS. 1 and 2, wiring layers 1, 2, 3, 4 are formed on a semiconductor substrate 5 with insulating films 6, 7 interposed therebetween. The wiring layers 1 , 2 , 3 , 4 have pitches p 1 , p 2 , p 3 , p 4 , wiring widths w 1 , w 2 , w 3 , respectively.
It is formed in accordance with the wiring standard of w 4 , wiring film thickness t 1 , t 2 , t 3 , t 4 . As shown here, the wiring standard is finer in the lower layer and coarser in the upper layer.
【００１０】ここで、配線層１はセル内配線用に、また
配線層４は電源層として用意されている。従って、セル
間配線には、配線層２、３が、それぞれ下層配線層、上
層配線層として用いられている。表１は、図１、図２の
配線層２、３の配線基準、単位線長当たりの抵抗・容量
の見積り値を示した表である。Here, the wiring layer 1 is prepared for in-cell wiring, and the wiring layer 4 is prepared as a power source layer. Therefore, for the inter-cell wiring, the wiring layers 2 and 3 are used as the lower wiring layer and the upper wiring layer, respectively. Table 1 is a table showing wiring standards of the wiring layers 2 and 3 of FIGS. 1 and 2 and estimated values of resistance and capacitance per unit line length.
【００１１】[0011]
【表１】 [Table 1]
【００１２】図３は、基本回路をＥＣＬ回路で構成した
場合の配線距離と配線遅延の関係を示したグラフであ
る。ここで、曲線は、配線を下層配線層２のみ使用し
た場合で、配線距離１ｍｍのときの配線遅延時間を１と
している（以下、この遅延時間を基準遅延時間と呼
ぶ）。曲線は、上層配線層３のみを使用した場合の遅
延時間を示している。また、曲線は、曲線とを平
均したもので、下層の配線層２と上層配線層３を各々５
０％使用した場合に相当している。従来のように使用配
線層を特定しない場合、セル間配線の平均的配線遅延時
間は、曲線に近くなる。FIG. 3 is a graph showing the relationship between the wiring distance and the wiring delay when the basic circuit is composed of an ECL circuit. Here, the curve shows the case where the wiring is used only in the lower wiring layer 2 and the wiring delay time when the wiring distance is 1 mm is 1 (hereinafter, this delay time is referred to as a reference delay time). The curve shows the delay time when only the upper wiring layer 3 is used. The curve is an average of the curves, and the lower wiring layer 2 and the upper wiring layer 3 are each 5
This is equivalent to using 0%. If the used wiring layer is not specified as in the conventional case, the average wiring delay time of the inter-cell wiring becomes close to a curve.
【００１３】図４は、あるマスタスライス方式半導体集
積回路装置におけるセル間配線の配線距離分布を示した
図である。同図に示されるように、通常の半導体集積回
路装置では、０．５ｍｍ以下の配線距離の短いところに
分布のピークが存在する。そこで、本発明では、セル間
距離に例えば３ｍｍの規定値を設け、大多数の配線が含
まれるこれ以下の配線長の配線は、微細で多くの配線を
収容できる下層配線層２を使用し、少数の規定値以上の
距離の配線は、配線抵抗が低い上層配線層３を使用す
る。FIG. 4 is a diagram showing a wiring distance distribution of inter-cell wiring in a master slice type semiconductor integrated circuit device. As shown in the figure, in a normal semiconductor integrated circuit device, there is a distribution peak at a short wiring distance of 0.5 mm or less. Therefore, in the present invention, the inter-cell distance is set to a prescribed value of, for example, 3 mm, and the wiring having a wiring length of less than this including the majority of wirings uses the lower wiring layer 2 capable of accommodating many wirings. The upper wiring layer 3 having a low wiring resistance is used for a small number of wirings over a specified value.
【００１４】配線長が短い場合、単位長当たりの抵抗値
の高い下層配線を使用しても配線遅延はそれ程増加する
ことはない。例えば規定値を３ｍｍと設定した場合、最
大配線遅延は、図３に示されるように基準遅延時間の
１．１６倍程度にとどまる。一方、長距離の配線は、単
位長当たりの抵抗値が低い上層配線を使用しているため
距離が延びても遅延時間の増加は低く、例えば配線長が
１０ｍｍの場合でも基準遅延時間の１．０６倍程度にな
るにすぎない。このことは、従来法での遅延時間が基準
遅延時間の１．３７倍であったのに比較して１割強の改
善がなされたことになる。よって、本発明により、配線
遅延を所定の範囲内に抑えることができ、高速動作が可
能な半導体集積回路装置を提供することができる。When the wiring length is short, the wiring delay does not increase so much even if a lower layer wiring having a high resistance value per unit length is used. For example, when the specified value is set to 3 mm, the maximum wiring delay is about 1.16 times the reference delay time as shown in FIG. On the other hand, since the long-distance wiring uses the upper wiring having a low resistance value per unit length, the increase of the delay time is small even if the distance is extended. For example, even when the wiring length is 10 mm, the reference delay time of 1. It is only about 06 times. This means that the delay time in the conventional method was 1.37 times the reference delay time, which is an improvement of more than 10%. Therefore, according to the present invention, a wiring delay can be suppressed within a predetermined range, and a semiconductor integrated circuit device capable of high speed operation can be provided.
【００１５】以上、好ましい実施例について説明した
が、本発明はこの実施例に限定されるものではなく、各
種の変更が可能である。例えば、セル間を接続するため
の配線層を３以上とすることができる。配線層が３層の
場合、下層配線層を短距離用に、中間配線層を中間距
離用に、上層配線層を長距離配線用に用いる、短距離
配線には下層配線層と中間配線層を用い、長距離配線に
は上層配線層と中間配線層とを用いる、等の手段を採る
ことができる。また、４層を用いる場合、下層の２層を
短距離用に、上層の２層を長距離用配線に用い、下層の
２層および上層の２層のそれぞれにＸ方向配線とＹ方向
配線に専用化された配線層を設けるようにすることがで
きる。Although the preferred embodiment has been described above, the present invention is not limited to this embodiment, and various modifications can be made. For example, the number of wiring layers for connecting the cells can be three or more. When the wiring layers are three layers, the lower wiring layer is used for short distance, the intermediate wiring layer is used for intermediate distance, the upper wiring layer is used for long distance wiring, and the lower wiring layer and the intermediate wiring layer are used for short distance wiring. It is also possible to employ means such as using an upper wiring layer and an intermediate wiring layer for the long distance wiring. When four layers are used, the lower two layers are used for short-distance wiring and the upper two layers are used for long-distance wiring. It is possible to provide a dedicated wiring layer.
【００１６】[0016]
【発明の効果】以上説明したように、本発明は、接続す
るセル間の距離に規定値を設け、規定値以下の場合には
下層の、また規定値以上の場合には上層の配線層を用い
てセル間の配線を行うようにしたものであるので、本発
明によれば、数の多い短距離の配線は、微細で配線密度
の高い下層配線層を用いて面積当たりの配線効率向上を
図ることができ、また、少数の長距離の配線について
は、配線抵抗の低い上層配線層を用いることにより遅延
時間を効果的に短縮することができる。従って、本発明
によれば、大規模化された半導体集積回路装置の高集積
化・高性能化を実現することができる。As described above, according to the present invention, the distance between the cells to be connected is set to a specified value, and when the value is less than the specified value, the lower wiring layer is formed, and when it is more than the specified value, the upper wiring layer is formed. According to the present invention, since a plurality of short-distance wirings are used, the wiring efficiency per area is improved by using a lower wiring layer that is fine and has a high wiring density. Further, for a small number of long-distance wirings, the delay time can be effectively shortened by using the upper wiring layer having a low wiring resistance. Therefore, according to the present invention, high integration and high performance of a large scale semiconductor integrated circuit device can be realized.
【図１】 本発明の一実施例を説明するための断面図。FIG. 1 is a sectional view for explaining an embodiment of the present invention.
【図２】 本発明の一実施例を説明するための断面図。FIG. 2 is a sectional view for explaining one embodiment of the present invention.
【図３】 配線距離と配線遅延時間との関係を示すグラ
フ。FIG. 3 is a graph showing the relationship between wiring distance and wiring delay time.
【図４】 セル間配線の配線距離分布図。FIG. 4 is a wiring distance distribution diagram of inter-cell wiring.
１、４ 配線層 ２ 下層配線層 ３ 上層配線層 ５ 半導体基板 ６、７ 絶縁膜 1, 4 Wiring layer 2 Lower wiring layer 3 Upper wiring layer 5 Semiconductor substrate 6, 7 Insulating film
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 7514−4Ｍ Ｈ０１Ｌ 21/88 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location 7514-4M H01L 21/88 Z
Claims (1)
配線層でセル間を接続することにより所定の機能を実現
するマスタスライス方式の半導体集積回路装置におい
て、 接続を行うべきセル間の距離が予め設定した規定値以上
の場合には上層の配線層を用い、規定値以下の場合には
下層の配線層を用いてセル間を接続したことを特徴とす
る半導体集積回路装置。1. In a master slice semiconductor integrated circuit device in which a basic circuit is prepared for each cell and a predetermined function is realized by connecting the cells with a plurality of wiring layers, the distance between the cells to be connected The semiconductor integrated circuit device is characterized in that the cells are connected by using the upper wiring layer when the value is equal to or more than a preset specified value and using the lower wiring layer when the value is equal to or less than the specified value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19337092A JPH0613590A (en) | 1992-06-26 | 1992-06-26 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19337092A JPH0613590A (en) | 1992-06-26 | 1992-06-26 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0613590A true JPH0613590A (en) | 1994-01-21 |
Family
ID=16306788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19337092A Pending JPH0613590A (en) | 1992-06-26 | 1992-06-26 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0613590A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205570B1 (en) | 1997-06-06 | 2001-03-20 | Matsushita Electronics Corporation | Method for designing LSI circuit pattern |
| US6483176B2 (en) | 1999-12-22 | 2002-11-19 | Kabushiki Kaisha Toshiba | Semiconductor with multilayer wiring structure that offer high speed performance |
| JP2004207602A (en) * | 2002-12-26 | 2004-07-22 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US7132474B2 (en) | 2004-09-08 | 2006-11-07 | Lg Chem. Ltd. | Method for preparing styrenic resin having high impact strength and gloss |
| JP2007288215A (en) * | 1999-06-25 | 2007-11-01 | Toshiba Corp | Method for designing wiring structure of lsi |
| WO2009104391A1 (en) * | 2008-02-20 | 2009-08-27 | 日本電気株式会社 | Low-loss small inductor element |
| JP2010123847A (en) * | 2008-11-21 | 2010-06-03 | Oki Semiconductor Co Ltd | Semiconductor element |
| JP2010199386A (en) * | 2009-02-26 | 2010-09-09 | Oki Semiconductor Co Ltd | Semiconductor device |
| JP2010283373A (en) * | 2010-08-05 | 2010-12-16 | Renesas Electronics Corp | Semiconductor device |
| JP2011199225A (en) * | 2010-03-24 | 2011-10-06 | Renesas Electronics Corp | Semiconductor device and manufacturing method therefor |
| US8080831B2 (en) | 2002-09-27 | 2011-12-20 | Renesas Electronics Corporation | Semiconductor device and manufacturing the same |
-
1992
- 1992-06-26 JP JP19337092A patent/JPH0613590A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6205570B1 (en) | 1997-06-06 | 2001-03-20 | Matsushita Electronics Corporation | Method for designing LSI circuit pattern |
| JP2007288215A (en) * | 1999-06-25 | 2007-11-01 | Toshiba Corp | Method for designing wiring structure of lsi |
| US6483176B2 (en) | 1999-12-22 | 2002-11-19 | Kabushiki Kaisha Toshiba | Semiconductor with multilayer wiring structure that offer high speed performance |
| US6504237B2 (en) | 1999-12-22 | 2003-01-07 | Kabushiki Kaisha Toshiba | Semiconductor with multilayer metal structure using copper that offer high speed performance |
| US8080831B2 (en) | 2002-09-27 | 2011-12-20 | Renesas Electronics Corporation | Semiconductor device and manufacturing the same |
| JP2004207602A (en) * | 2002-12-26 | 2004-07-22 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
| US7132474B2 (en) | 2004-09-08 | 2006-11-07 | Lg Chem. Ltd. | Method for preparing styrenic resin having high impact strength and gloss |
| WO2009104391A1 (en) * | 2008-02-20 | 2009-08-27 | 日本電気株式会社 | Low-loss small inductor element |
| JP2010123847A (en) * | 2008-11-21 | 2010-06-03 | Oki Semiconductor Co Ltd | Semiconductor element |
| JP2010199386A (en) * | 2009-02-26 | 2010-09-09 | Oki Semiconductor Co Ltd | Semiconductor device |
| JP2011199225A (en) * | 2010-03-24 | 2011-10-06 | Renesas Electronics Corp | Semiconductor device and manufacturing method therefor |
| US9042117B2 (en) | 2010-03-24 | 2015-05-26 | Renesas Electronics Corporation | Semiconductor device |
| JP2010283373A (en) * | 2010-08-05 | 2010-12-16 | Renesas Electronics Corp | Semiconductor device |
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