JPH06101551B2 - CMOS integrated circuit device - Google Patents
CMOS integrated circuit deviceInfo
- Publication number
- JPH06101551B2 JPH06101551B2 JP60270505A JP27050585A JPH06101551B2 JP H06101551 B2 JPH06101551 B2 JP H06101551B2 JP 60270505 A JP60270505 A JP 60270505A JP 27050585 A JP27050585 A JP 27050585A JP H06101551 B2 JPH06101551 B2 JP H06101551B2
- Authority
- JP
- Japan
- Prior art keywords
- channel mos
- channel
- mos transistor
- transistor
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000009792 diffusion process Methods 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 19
- 238000010586 diagram Methods 0.000 description 13
- 230000010354 integration Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 238000002955 isolation Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高密度で高速なCMOS集積回路に関するものであ
る。The present invention relates to a high density and high speed CMOS integrated circuit.
集積回路(LSI)は論理LSIとメモリLSIに大分類され
る。ユーザ毎に機能・特性の異る論理LSIを短期間に、
効率よく実現するために、あらかじめトランジスタや抵
抗など回路素子を規則的に形成した半導体基板(マスタ
基板)を用い、回路素子間の結線を変えることで、ユー
ザの要求に対応した機能・特性を実現するいわゆるマス
タスライス方式がとられてきた。マスタスライスLSIに
おいては、あらかじめ形成しておく回路素子の配置や形
状が集積密度を大きく左右する。従来高集積度のマスタ
スライスLSIを実現する回路構成として、第6図の等価
回路と第7図の平面パタン図で示す、共通拡散層を持つ
2組のNチヤネルMOSトランジスタとPチヤネルMOSトラ
ンジスタをチップの所定領域全面に敷き詰めた、シーオ
ブゲート(Sea of Gates)と呼ばれる構成や、または
第8図の等価回路及び第9図の平面パタン図に示すよう
なP形及びN形のMOSトランジスタを、それぞれ分離領
域を設けずソース及びドレインを共通にして連続的に配
置し、素子間を分離する必要がある場合には、それぞれ
のMOSトランジスタのゲートに固定電圧を印加し(Nチ
ヤネルMOSトランジスタには基板電圧を、PチヤネルMOS
トランジスタには電源電圧を)、左右のMOSトランジス
タ間を電気的に遮断するゲート分離構成などがある。Integrated circuits (LSIs) are roughly classified into logic LSIs and memory LSIs. A logic LSI with different functions and characteristics for each user can be
In order to achieve this efficiently, a semiconductor substrate (master substrate) on which circuit elements such as transistors and resistors are regularly formed in advance is used, and the wiring between circuit elements is changed to realize the functions and characteristics that meet user requirements. The so-called master slice method has been adopted. In the master slice LSI, the layout and shape of the circuit elements formed in advance have a great influence on the integration density. As a circuit configuration for realizing a conventional highly integrated master slice LSI, two sets of an N-channel MOS transistor and a P-channel MOS transistor having a common diffusion layer shown in the equivalent circuit of FIG. 6 and the plane pattern diagram of FIG. 7 are used. A structure called Sea of Gates, which is spread over the entire predetermined area of the chip, or P-type and N-type MOS transistors as shown in the equivalent circuit of FIG. 8 and the plane pattern diagram of FIG. , In the case where it is necessary to separate the elements by arranging the source and drain in common with no isolation region and separating them continuously, a fixed voltage is applied to the gate of each MOS transistor (N-channel MOS transistor Is the substrate voltage, P channel MOS
The transistor has a power supply voltage), and there is a gate separation structure that electrically cuts off between the left and right MOS transistors.
第6図において、1,2及び3,4はそれぞれPチヤネルおよ
びNチヤネルMOSトランジスタのゲートを、6はPチヤ
ネルMOSトランジスタのソースを、5、7はPチヤネルM
OSトランジスタのドレインを、9はNチヤネルMOSトラ
ンジスタのソースを、8,10はNチヤネルMOSトランジス
タのドレインを示す。また、第7図において11はNウエ
ル領域を、12はNウエル領域の電位固定用のN+領域を、
13は基板電位固定用のP+領域を示す。また、第8図にお
いて、14〜25はMOSトランジスタのゲートを、26〜35は
ソースまたはドレインを示す。In FIG. 6, 1, 2 and 3, 4 are the gates of the P-channel and N-channel MOS transistors, 6 is the source of the P-channel MOS transistor, and 5 and 7 are the P-channel M.
The drain of the OS transistor, 9 indicates the source of the N channel MOS transistor, and 8 and 10 indicate the drain of the N channel MOS transistor. In FIG. 7, 11 is an N well region, 12 is an N + region for fixing the potential of the N well region,
Reference numeral 13 denotes a P + region for fixing the substrate potential. Further, in FIG. 8, 14 to 25 are gates of MOS transistors, and 26 to 35 are sources or drains.
これら従来の構成は、同一寸法のP形及びN形トランジ
スタを用いているため、メモリ回路やレジスタ回路等の
情報記憶回路を構成した場合、動作安定度が低いという
問題があつた。すなわち、従来CMOSマスタスライスで用
いられているメモリ回路は、第10図の回路図に示すよう
に、合計6トランジスタから成るものであり、36は電源
線(VDD)、37は接地線(VSS)、38はワード線、39,40
は1対のビツト線、41,42はメモリセル内のノード、43,
44はビツト線とメモリセル間のスイツチとなるトランス
フアゲート、45,46はメモリセルを構成するNチヤネル
トランジスタ、47,48はメモリセルを構成するPチヤネ
ルトランジスタである。Pチヤネルトランジスタ47と48
の大きさを一定とし、Nチヤネルトランジスタ45と46、
及びトランスフアゲート43と44をそれぞれ同一寸法と
し、Nチヤネルトランジスタ45とトランスフアゲート43
の比率Q2/Q1(同時にNチヤネルトランジスタ46とトラ
ンスフアゲート44の比率でもある。)を変えてメモリセ
ルの情報をビツト線39に読み出した時、第11図に示すよ
うに、Nチヤネルトランジスタ45とトランスフアゲート
43のトランジスタ寸法の比率Q2/Q1が2以下ではメモリ
セル内のノード41と42の電位差がほとんどなくなり、メ
モリセル内の情報が破壊されてしまう。このためメモリ
セルを安定に動作させるには、2倍以上寸法の異るトラ
ンジスタを用いて回路を構成する必要がある。また第12
図に示すような、高集積化に適したラツチ回路におい
て、データをラツチするため出力信号の反転信号を入力
側にフイードバツクする49のP形トランジスタは、通常
他のトランジスタの半分以下の寸法のものが用いられ
る。このP形トランジスタ49が大きい場合、50のトラン
スフアゲートがON状態となつて情報を“1"から“0"に書
き替える時、ノード51の電位変化が遅く、データ書き替
えに時間がかかる、またはノード51の電位がインバータ
58の論理閾値レベル以下に低下せず、データの書き替え
が不可能となる問題があり、第12図の回路では、49のP
形トランジスタを他のトランジスタの半分以下とする必
要があつた。また従来のマスタスライスでは、集積密度
を向上させるため、第7図や第9図に示す基本セルをチ
ツプの所定領域全面に敷き詰めた第13図や第14図の構成
が用いられているが、いずれの構成においても、基板電
位を固定するために必要な拡散層領域が第13図のNウエ
ル電位固定用N+領域12,基板電位固定用P+領域13や、第1
4図のNウエル電位固定用N+領域12,基板電位固定用P+領
域13で示すように、トランジスタ間の無効領域となり、
集積密度を上げる上で問題となつていた。Since these conventional configurations use P-type and N-type transistors of the same size, there is a problem that the operation stability is low when an information storage circuit such as a memory circuit or a register circuit is configured. That is, as shown in the circuit diagram of FIG. 10, the memory circuit conventionally used in the CMOS master slice is composed of a total of 6 transistors, 36 is a power supply line (V DD ), and 37 is a ground line (V DD ). SS ), 38 is word line, 39,40
Is a pair of bit lines, 41, 42 are nodes in the memory cell, 43,
44 is a transfer gate serving as a switch between the bit line and the memory cell, 45 and 46 are N-channel transistors forming the memory cell, and 47 and 48 are P-channel transistors forming the memory cell. P channel transistors 47 and 48
The size of N is constant, N-channel transistors 45 and 46,
And the transfer gates 43 and 44 have the same size, and the N-channel transistor 45 and the transfer gate 43
When the information of the memory cell is read out on the bit line 39 by changing the ratio Q 2 / Q 1 (which is also the ratio of the N channel transistor 46 and the transfer gate 44), as shown in FIG. 45 and transfer gate
When the transistor size ratio Q 2 / Q 1 of 43 is 2 or less, the potential difference between the nodes 41 and 42 in the memory cell is almost eliminated, and the information in the memory cell is destroyed. Therefore, in order to operate the memory cell stably, it is necessary to configure the circuit by using transistors whose size is twice or more different. Also the 12th
In a latch circuit suitable for high integration as shown in the figure, 49 P-type transistors that feed back the inverted signal of the output signal to the input side to latch the data are usually less than half the size of other transistors. Is used. When the P-type transistor 49 is large, when the transfer gate of 50 is turned on and information is rewritten from "1" to "0", the potential change of the node 51 is slow and it takes time to rewrite data, or The potential of node 51 is inverter
There is a problem that the data cannot be rewritten without lowering below the logical threshold level of 58, and in the circuit of FIG.
It was necessary to reduce the number of shaped transistors to less than half that of other transistors. Further, in the conventional master slice, in order to improve the integration density, the structure shown in FIGS. 13 and 14 in which the basic cells shown in FIGS. 7 and 9 are spread over the entire predetermined area of the chip is used. In any of the configurations, the diffusion layer regions necessary for fixing the substrate potential are the N well region fixing N + region 12, the substrate potential fixing P + region 13, and the first diffusion region shown in FIG.
As shown by the N well region fixing N + region 12 and the substrate potential fixing P + region 13 in FIG.
There was a problem in increasing the integration density.
第13図において、59は敷き詰める構成の単位となるセル
パタン単を示し、第13図および第14図における60は基本
セルが並ぶコア領域を、61は入出力回路が並ぶ周辺領域
を示す。第14図に示すゲート分離構成は、トランジスタ
のゲートに電圧を印加することで、任意の位置で素子間
を分離できる高密度な構成であるが、基板電位固定用の
拡散層をトランジスタ列間に設けなければならなく、約
17%の面積増加となり、高密度化上問題となつていた。In FIG. 13, reference numeral 59 denotes a cell pattern that is a unit of the structure to be spread, 60 in FIGS. 13 and 14 denotes a core area where basic cells are arranged, and 61 denotes a peripheral area where input / output circuits are arranged. The gate separation structure shown in FIG. 14 is a high-density structure in which elements can be separated at arbitrary positions by applying a voltage to the gates of transistors, but a diffusion layer for fixing the substrate potential is provided between transistor columns. Must be provided, about
The area increased by 17%, which was a problem for higher density.
またゲート分離構成では、トランジスタのゲート電極及
び基板電位固定用拡散層と電源線を接続するため、トラ
ンジスタの一方のゲート電極上に電源線を通すため、2
個の信号端子の内、外側の1端子は信号用としては使用
できず、信号線結線上の柔軟性がそこなわれるという問
題があつた。Further, in the gate separation structure, since the power supply line is connected to the gate electrode of the transistor and the diffusion layer for fixing the substrate potential, the power supply line is passed over one gate electrode of the transistor.
Of the individual signal terminals, the outer one terminal cannot be used for signals and there is a problem in that the flexibility of the signal line connection is impaired.
本発明は従来の問題点を解決するため、CMOSマスタスラ
イス方式LSIのトランジスタ配置としてPチヤネルMOSト
ランジスタとNチヤネルMOSトランジスタを、それぞれ
ゲート電極を対向させて横一列に並べ、隣接するPチヤ
ネルMOSトランジスタの拡散層および隣接するNチヤネ
ルMOSトランジスタの拡散層をそれぞれ共通とし、同一
種類のPチヤネルMOSトランジスタのすべて、および同
一種類のNチヤネルMOSトランジスタのすべてがそれぞ
れ電気回路的には直列に接続される構成のCMOS集積回路
装置において、前記隣接するPチヤネルMOSトランジス
タのソース拡散層とドレイン拡散層、および前記隣接す
るNチヤネルMOSトランジスタのソース拡散層とドレイ
ン拡散層をそれぞれ共通とし、前記横一列に並べたPチ
ヤネルMOSトランジスタの列内に前記PチヤネルMOSトラ
ンジスタより短いチヤネル幅のPチヤネルMOSトランジ
スタを配置し、前記横一列に並べたNチヤネルMOSトラ
ンジスタの列内に前記NチヤネルMOSトランジスタより
短いチヤネル幅のNチヤネルMOSトランジスタを配置
し、前記チヤネル幅の短いPチヤネルMOSトランジスタ
およびNチヤネルMOSトランジスタを配置したことによ
り生じる余裕領域に基板電位固定用の拡散層を設けたこ
とを特徴としている。In order to solve the conventional problems, the present invention has a P-channel MOS transistor and an N-channel MOS transistor as a transistor arrangement of a CMOS master slice type LSI, which are arranged in a horizontal row with their gate electrodes facing each other, and adjacent P-channel MOS transistors. Common diffusion layer and adjacent N-channel MOS transistor diffusion layers, and all P-channel MOS transistors of the same type and all N-channel MOS transistors of the same type are electrically connected in series. In the CMOS integrated circuit device having the structure, the source diffusion layer and the drain diffusion layer of the adjacent P-channel MOS transistors and the source diffusion layer and the drain diffusion layer of the adjacent N-channel MOS transistors are common to each other and arranged in the horizontal row. In the row of P channel MOS transistors, the P A P-channel MOS transistor having a channel width shorter than that of the channel MOS transistor is arranged, and an N-channel MOS transistor having a channel width shorter than that of the N-channel MOS transistor is arranged in the row of N-channel MOS transistors arranged side by side. It is characterized in that a diffusion layer for fixing the substrate potential is provided in a marginal area generated by arranging the P channel MOS transistor and the N channel MOS transistor having a short width.
すなわち、本発明は、要約すると、ゲート分離構成にお
いて、一定の割合で小寸法のMOSトランジスタをMOSトラ
ンジスタ列内に配置し、かつ小寸法MOSトランジスタの
配置により生じた余裕領域に、基板電位固定用の拡散層
を配置したことを特徴とし、その目的は高密度で安定な
回路動作を行うマスタスライス構成を提供することにあ
る。That is, the present invention is summarized as follows. In a gate isolation structure, small-sized MOS transistors are arranged at a constant rate in a MOS transistor array, and a substrate potential is fixed in a margin area generated by the arrangement of small-sized MOS transistors. Of the diffusion layer is arranged, and the purpose thereof is to provide a master slice configuration which performs stable circuit operation with high density.
本発明は、CMOSマスタスライスにおいて、メモリ回路や
データラツチ回路を、十分な回路動作余裕を持つて構成
するのに必要な幅の狭いMOSトランジスタを一定の割合
で配置されているため、この幅の狭いMOSトランジスタ
を回路に利用することにより、従来マスタスライスでは
実現できなかつた完全非同期形のメモリ回路を構成する
ことが可能である。According to the present invention, in the CMOS master slice, the MOS transistors having a narrow width necessary for configuring the memory circuit and the data latch circuit with a sufficient circuit operation allowance are arranged at a fixed ratio. By using MOS transistors in the circuit, it is possible to construct a completely asynchronous memory circuit that could not be realized by the conventional master slice.
また、一定の割合でチヤネル幅の狭いトランジスタを配
置したことにより生じた余裕領域に、基板電位(ウエル
電位を含む)固定用の拡散層を設けたことにより、従来
トランジスタ列間にあつて全体の約17%の面積を占めて
いた拡散層をなくし、マスタスライスの集積密度を増加
させることができる。以下図面にもとづき実施例につい
て説明する。In addition, by providing a diffusion layer for fixing the substrate potential (including well potential) in a marginal area generated by arranging transistors with a narrow channel width at a constant rate, it is possible to reduce the total area between conventional transistor rows. By eliminating the diffusion layer that occupies about 17% of the area, the integration density of the master slice can be increased. Embodiments will be described below with reference to the drawings.
第1図は本発明の実施例であつて、11はNウエル、12は
ウエル電位固定用のN+拡散層によるウエル電位固定用N+
領域、13は基板電位固定用P+拡散層による基板電位固定
用P+領域、62〜67はチヤネル幅の広いPチヤネルMOSト
ランジスタ、68〜70はチヤネル幅の狭いPチヤネルMOS
トランジスタ、71〜76はチヤル幅の広いNチヤネルMOS
トランジスタ、77〜79はチヤネル幅の狭いNチヤネルMO
Sトランジスタ、80はPチヤネルMOSトランジスタのソー
スまたはドレインとなるP形拡散層、81はNチヤネルMO
SトランジスタのソースまたはドレインとなるN形拡散
層である。このように一定の間隔でチヤネル幅の狭いMO
Sトランジスタを配置することにより、回路動作に対応
した異る寸法のトランジスタを利用することができ、安
定な回路動作を達成することができる。第1図のトラン
ジスタ配置の下で、配線によりメモリセルを構成する場
合のレイアウトパタン図を第2図に示す。第2図で右斜
線部は第1層目の金属配線層を、左斜線部は第2層目の
金属配線層を示す。また黒ぬり部は第1層目金属とトラ
ンジスタのゲート及びソース・ドレインとの接続点を示
し、点の領域は第1層金属と第2層金属の接続スルーホ
ールである。第2図は第10図の回路を現わしており、36
は電源線、37は接地線、38はワード線、39,40は左右の
ビツト線、41,42はメモリセル内のノード、43,44の幅の
狭いトランジスタを用いたトランスフアゲート、45,46
はメモリセル内のNチヤネルMOSトランジスタ、47,48は
PチヤネルMOSトランジスタである。47,48のPチヤネル
MOSトランジスタを他と分離してメモリ回路に用いるた
めに、63,64,65,66のチヤネル幅の広いPチヤネルMOSト
ランジスタのゲートに正電圧を印加し、各トランジスタ
を非導通状態として分離する。またトランスフアゲート
43,44も同様、隣りの72,75のチヤネル幅の広いNチヤネ
ルMOSトランジスタのゲートに接地電位を与え、非導通
状態として他と分離する。このようにメモリセル回路を
構成する場合、大きさの異るトランジスタを用いること
により、安定な回路動作を実現することができる。ま
た、1メモリセルは、NチヤネルMOSトランジスタのゲ
ート6個分(6ピツチと呼ぶ)で実現でき、シーオブゲ
ートの7ピツチと比べても高密度に実現できる。Figure 1 an alien in the embodiment of the present invention, 11 N-well, 12 for fixing the well potential N + well due to the diffusion layer potential fixing N +
Region 13, 13 is a P + region for fixing the substrate potential by the P + diffusion layer, 62-67 is a P channel MOS transistor with a wide channel width, 68-70 is a P channel MOS with a narrow channel width
Transistors, 71-76 are N-channel MOS with wide channel width
Transistors, 77 to 79 are N channels with narrow channel MO
S-transistor, 80 is a P-type diffusion layer serving as the source or drain of a P-channel MOS transistor, and 81 is an N-channel MO.
It is an N-type diffusion layer that serves as the source or drain of the S transistor. In this way, MO with a narrow channel width at regular intervals
By arranging the S transistor, it is possible to use transistors having different sizes corresponding to the circuit operation, and it is possible to achieve stable circuit operation. FIG. 2 shows a layout pattern diagram when a memory cell is constituted by wiring under the transistor arrangement of FIG. In FIG. 2, the shaded area to the right indicates the first metal wiring layer, and the shaded area to the left indicates the second metal wiring layer. Further, the solid black portion indicates a connection point between the first layer metal and the gate and the source / drain of the transistor, and the region of the point is a connection through hole of the first layer metal and the second layer metal. FIG. 2 shows the circuit of FIG.
Is a power supply line, 37 is a ground line, 38 is a word line, 39 and 40 are left and right bit lines, 41 and 42 are nodes in a memory cell, 43 and 44 are transfer gates using narrow transistors, and 45 and 46 are
Is an N channel MOS transistor in the memory cell, and 47 and 48 are P channel MOS transistors. 47,48 P channel
In order to separate the MOS transistors from others and use them in the memory circuit, a positive voltage is applied to the gates of the P-channel MOS transistors 63, 64, 65, 66 having a wide channel width to separate each transistor from the non-conducting state. Also transfer gate
Similarly, 43 and 44 also apply the ground potential to the gates of the adjacent N-channel MOS transistors having a wide channel width of 72 and 75, which are separated from each other by making them non-conductive. In the case of configuring the memory cell circuit in this way, stable circuit operation can be realized by using transistors having different sizes. Further, one memory cell can be realized with six gates of N-channel MOS transistors (referred to as 6 pitches), and can be realized with a high density as compared with 7 pitches of the sea of gates.
また第1図に示すように、従来、トランジスタ列間に置
かれていた12のNウエルコンタクト用拡散領域を形成す
るウエル電位固定用N+領域を、68や69のチヤネル幅の短
いPチヤネルMOSトランジスタの寸法を小さくしたこと
により生じた余裕領域に、また、13の基板コンタクト用
拡散層を形成する基板電位固定用P+領域を、77や78のチ
ヤネル幅の狭いNチヤネルMOSトランジスタの余裕領域
に置くことにより、PチヤネルおよびNチヤネルそれぞ
れのMOSトランジスタ列間の間隔をつめて配列すること
が出来、高密度化を達成することができる。Further, as shown in FIG. 1, the well potential fixing N + regions forming the diffusion regions for 12 N well contacts, which are conventionally placed between the transistor columns, are replaced by the P channel MOS of 68 or 69 having a short channel width. In the margin area created by reducing the size of the transistor, and the P + area for fixing the substrate potential that forms the diffusion layer for the substrate contact in 13 is the margin area of the N channel MOS transistor with a narrow channel width of 77 or 78. In this case, the MOS transistor rows of the P-channel and the N-channel can be arranged with a small space between them, and high density can be achieved.
MOSトランジスタ列間にウエルコンタクトや基板コンタ
クト用の拡散層を配置する従来構成と、本発明の構成を
比較して第3図A,Bに示す。第3図Aは従来構成、第3
図Bは本発明の構成を示している。本発明によりセル列
間の拡散層をMOSトランジスタ配列内に吸収でき、約13
%〜15%面積が縮小できる。FIGS. 3A and 3B show a comparison between the configuration of the present invention and the conventional configuration in which diffusion layers for well contacts and substrate contacts are arranged between MOS transistor columns. FIG. 3A shows a conventional configuration, third
FIG. B shows the configuration of the present invention. According to the present invention, the diffusion layer between cell columns can be absorbed in the MOS transistor array,
Area can be reduced by 15% to 15%.
第4図に本発明の他の実施例の平面パタン図を示す。第
1図と同じ符号は同じ部分を示す。幅の狭いMOSトラン
ジスタの上下に基板コンタクト用の拡散層を置くことに
より、MOSトランジスタ列が対象となり、電源線及び接
地線をMOSトランジスタ列の上下いずれにも置くことが
可能となる。第5図Aに第4図の実施例のパタンをチツ
プ一面に敷き詰めた図を示す。このような構造であるか
ら、第5図Aに示すように、PチヤネルMOSトランジス
タ列、NチヤネルMOSトランジスタ列を交互に配列した
敷き詰め形構成において、任意の位置でP−N,またはN
−Pの順序でゲート列を置くことができる。このため、
配線トラツクはMOSトランジスタ列1列分のトラツク数
の倍数で設定でき、効率的な配線ができるという利点が
ある。FIG. 4 shows a plane pattern diagram of another embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts. By placing a diffusion layer for substrate contact above and below a narrow MOS transistor, the MOS transistor array is targeted, and the power supply line and the ground line can be located above and below the MOS transistor array. FIG. 5A shows a diagram in which the pattern of the embodiment shown in FIG. 4 is spread all over the chip. Due to this structure, as shown in FIG. 5A, in a spread type configuration in which P-channel MOS transistor rows and N-channel MOS transistor rows are alternately arranged, P-N or N
Gate rows can be placed in the order -P. For this reason,
The wiring track can be set by a multiple of the number of tracks for one MOS transistor row, and there is an advantage that efficient wiring can be performed.
第5図Bに本発明の他の実施例の一部を示す。第1図と
同じ符号は同じ部分を示す。FIG. 5B shows a part of another embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same parts.
第5図Bにおいて、N形拡散層81がP形拡散層と完全に
分離されて一部存在し、そのN形拡散層が12のNウェル
電位固定用N+領域に囲まれたことが第1図と異なるほか
はすべて同じである。このようにしても12の電位固定の
役割は何ら変わることがなく、また、マスタスライスと
しての特徴もこれまで述べたことと変わりがないことは
言うまでもない。In FIG. 5B, the N-type diffusion layer 81 is completely separated from the P-type diffusion layer and partially present, and the N-type diffusion layer is surrounded by 12 N well potential fixing N + regions. It is the same except that it is different from Fig. 1. It goes without saying that the role of fixing the potential of 12 does not change even in this case, and the characteristics of the master slice are the same as those described above.
この考えは第4図のように、pウェル、nウェルのそれ
ぞれ上下の電位固定部分がある場合にも、適用可能であ
る。This idea can be applied to the case where there are potential fixing portions above and below the p well and the n well as shown in FIG.
以上説明したように、本発明によればPチヤネル及びN
チヤネルMOSトランジスタ1列に縦続接続された構成に
おいて、チヤネル幅の狭いMOSトランジスタを一定のく
り返し(たとえば2乃至3個のMOSトランジスタ毎に1
個)で配列したことにより、素子間分離用のゲートまた
は、メモリセルやフリツプフロツプ,ラツチ回路でチヤ
ネル幅の狭いトランスフアゲートとして利用でき、安定
な回路動作を実現できる利点がある。As described above, according to the present invention, the P channel and N
In a structure in which one row of channel MOS transistors are connected in series, a MOS transistor having a narrow channel width is repeatedly repeated (for example, every 2 to 3 MOS transistors are 1
This arrangement has the advantage that it can be used as a gate for element isolation or as a transfer gate with a narrow channel width in a memory cell, flip-flop, or latch circuit, and can realize stable circuit operation.
第1図は本発明の一実施例の平面パタン図、第2図は本
発明の基本セル構成のもとでメモリセルをレイアウトし
たパタン図、第3図A,Bは従来例と本発明の実施例との
比較を示す図、第4図は本発明の他の実施例の平面パタ
ン図、第5図A,Bは第4図のパタンをチツプ一面に敷き
詰めた図、第6図および第8図はそれぞれ従来のマスタ
スライスLSIの基本構成単位の等価回路図、第7図およ
び第9図はそれぞれ第6図および第8図の従来構成の平
面パタン図、第10図はスタテイツクメモリのメモリセル
回路、第11図はメモリセル回路の安定動作条件を示す
図、第12図は高集積化に適したラツチ回路図、第13図は
第7図の基本セルをチツプ全面に敷き詰めた構成図、第
14図は第9図の基本セルをチツプ全面に敷き詰めた構成
図である。 1〜4,14〜25……MOSトランジスタのゲート、5〜10,26
〜35……MOSトランジスタのソースまたはドレイン、11
……Nウエル、12……Nウエル電位固定用N+領域、13…
…基板電位固定用P+領域、36……電源線、37は接地線、
38……ワード線、39,40……ビツト線、41,42……メモリ
セル内ノード、43,44……ビツト線とメモリセル間のス
イツチとなるトランスフアゲート、45,46……Nチヤネ
ルMOSトランジスタ、47,48……PチヤネルMOSトランジ
スタ、49……ラツチのPチヤネルMOSトランジスタ、50
……トランスフアゲート、51〜55……ラツチ内のノー
ド、56……電源、57,58……インバータ、59……敷き詰
めの単位となるセルパタン、60……コア領域、61……周
辺領域、62〜67……長いチヤネル幅を持つPチヤネルMO
Sトランジスタ、68〜70……短いチヤネル幅を持つPチ
ヤネルMOSトランジスタ、71〜76……長いチヤネル幅を
持つNチヤネルMOSトランジスタ、77〜79……短いチヤ
ネル幅を持つNチヤネルMOSトランジスタ、80……P形
拡散層、81……N形拡散層FIG. 1 is a plane pattern diagram of an embodiment of the present invention, FIG. 2 is a pattern diagram in which memory cells are laid out under the basic cell configuration of the present invention, and FIGS. 3A and 3B are conventional examples and the present invention. FIG. 4 shows a comparison with an embodiment, FIG. 4 is a plane pattern view of another embodiment of the present invention, and FIGS. 5A and 5B are views in which the pattern of FIG. 4 is spread over a chip, FIG. 6 and FIG. FIG. 8 is an equivalent circuit diagram of the basic configuration unit of the conventional master slice LSI, FIGS. 7 and 9 are plane pattern diagrams of the conventional configuration of FIGS. 6 and 8, and FIG. 10 is a static memory. Memory cell circuit, Fig. 11 is a diagram showing stable operation conditions of the memory cell circuit, Fig. 12 is a latch circuit diagram suitable for high integration, and Fig. 13 is a configuration in which the basic cells of Fig. 7 are spread all over the chip. Figure, first
FIG. 14 is a configuration diagram in which the basic cells of FIG. 9 are spread over the entire surface of the chip. 1 to 4,14 to 25 …… MOS transistor gate, 5 to 10,26
~ 35 …… Source or drain of MOS transistor, 11
…… N well, 12 …… N well potential fixing N + region, 13 ・ ・ ・
... P + area for fixing the substrate potential, 36 ... power supply line, 37 is a ground line,
38 ... Word line, 39,40 ... bit line, 41,42 ... Node in memory cell, 43,44 ... Transfer gate as switch between bit line and memory cell, 45,46 ... N channel MOS Transistors, 47, 48 ... P-channel MOS transistors, 49 ... Latch P-channel MOS transistors, 50
...... Transfer gates, 51 to 55 ...... nodes in the latch, 56 ...... power supply, 57,58 ...... inverter, 59 …… cell pattern that is the unit of spreading, 60 …… core area, 61 …… peripheral area, 62 ~ 67 …… P channel MO with long channel width
S-transistor, 68-70 ... P-channel MOS transistor with short channel width, 71-76 ... N-channel MOS transistor with long channel width, 77-79 ... N-channel MOS transistor with short channel width, 80 ... … P type diffusion layer, 81 …… N type diffusion layer
Claims (1)
タ配置としてPチヤネルMOSトランジスタとNチヤネルM
OSトランジスタを、それぞれゲート電極を対向させて横
一列に並べ、隣接するPチヤネルMOSトランジスタの拡
散層および隣接するNチヤネルMOSトランジスタの拡散
層をそれぞれ共通とし、同一種類のPチヤネルMOSトラ
ンジスタのすべて、および同一種類のNチヤネルMOSト
ランジスタのすべてがそれぞれ電気回路的には直列に接
続される構成のCMOS集積回路装置において、 前記隣接するPチヤネルMOSトランジスタのソース拡散
層とドレイン拡散層、および前記隣接するNチヤネルMO
Sトランジスタのソース拡散層とドレイン拡散層をそれ
ぞれ共通とし、 前記横一列に並べたPチヤネルMOSトランジスタの列内
に前記PチヤネルMOSトランジスタより短いチヤネル幅
のPチヤネルMOSトランジスタを配置し、 前記横一列に並べたNチヤネルMOSトランジスタの列内
に前記NチヤネルMOSトランジスタより短いチヤネル幅
のNチヤネルMOSトランジスタを配置し、 前記チヤネル幅の短いPチヤネルMOSトランジスタおよ
びNチヤネルMOSトランジスタを配置したことにより生
じる余裕領域に基板電位固定用の拡散層を設けてなる ことを特徴とするCMOS集積回路装置。1. A P-channel MOS transistor and an N-channel M as a transistor arrangement of a CMOS master slice type LSI.
The OS transistors are arranged in a horizontal row with their gate electrodes facing each other, and the diffusion layers of the adjacent P-channel MOS transistors and the diffusion layers of the adjacent N-channel MOS transistors are respectively common, and all of the P-channel MOS transistors of the same type, And a CMOS integrated circuit device in which all N-channel MOS transistors of the same type are electrically connected in series in an electrical circuit, the source diffusion layer and the drain diffusion layer of the adjacent P-channel MOS transistors, and the adjacent N Channel MO
The source diffusion layer and the drain diffusion layer of the S transistor are common to each other, and a P channel MOS transistor having a channel width shorter than the P channel MOS transistor is arranged in the row of P channel MOS transistors arranged in the horizontal row. An N channel MOS transistor having a channel width shorter than that of the N channel MOS transistor is arranged in the column of N channel MOS transistors arranged in line, and a margin caused by arranging the P channel MOS transistor and the N channel MOS transistor having the short channel width is arranged. A CMOS integrated circuit device characterized in that a diffusion layer for fixing the substrate potential is provided in the region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60270505A JPH06101551B2 (en) | 1985-11-30 | 1985-11-30 | CMOS integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60270505A JPH06101551B2 (en) | 1985-11-30 | 1985-11-30 | CMOS integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62130538A JPS62130538A (en) | 1987-06-12 |
JPH06101551B2 true JPH06101551B2 (en) | 1994-12-12 |
Family
ID=17487187
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60270505A Expired - Fee Related JPH06101551B2 (en) | 1985-11-30 | 1985-11-30 | CMOS integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06101551B2 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04112138U (en) * | 1991-03-20 | 1992-09-29 | 株式会社東郷製作所 | End cap for molding |
JPH056965A (en) * | 1991-06-26 | 1993-01-14 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit and manufacture thereof |
EP0598895A4 (en) * | 1992-06-10 | 1994-11-09 | Aspec Tech Inc | Symmetrical multi-layer metal logic array with continuous substrate taps. |
DE69333881T2 (en) | 1992-07-31 | 2006-07-13 | Hughes Electronics Corp., El Segundo | Integrated circuit safety system and method with implanted connections |
EP0690509A1 (en) * | 1994-06-30 | 1996-01-03 | Texas Instruments Incorporated | Substrate contact for gate array base cell and method of forming same |
DE69525707T2 (en) * | 1994-09-30 | 2002-08-01 | Sharp K.K., Osaka | MOS inverter circuit |
JPH08213575A (en) * | 1995-11-27 | 1996-08-20 | Nippon Telegr & Teleph Corp <Ntt> | Cmos integrated circuit device |
-
1985
- 1985-11-30 JP JP60270505A patent/JPH06101551B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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JPS62130538A (en) | 1987-06-12 |
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