JPH0595230A - Frequency converter - Google Patents
Frequency converterInfo
- Publication number
- JPH0595230A JPH0595230A JP27862291A JP27862291A JPH0595230A JP H0595230 A JPH0595230 A JP H0595230A JP 27862291 A JP27862291 A JP 27862291A JP 27862291 A JP27862291 A JP 27862291A JP H0595230 A JPH0595230 A JP H0595230A
- Authority
- JP
- Japan
- Prior art keywords
- noise
- signal
- circuit
- mixing
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Noise Elimination (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はテレビジョンチュ−ナ等
の受信装置に用いて好適な周波数変換装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency converter suitable for use in a receiver such as a television tuner.
【０００２】[0002]
【従来の技術】先ず、従来におけるテレビジョンチュ−
ナの基本構成を図４に示す。同図において１はアンテナ
からの受信信号を取り入れる入力端子、２は受信信号の
中から希望の信号のみを通過させる同調回路又はバンド
パスフィルタ、３は増幅回路をそれぞれ示す。４及び５
はそれぞれ混合回路と局部発振回路を示し、これらは周
波数変換装置６を構成している。７は周波数変換された
信号の中から希望信号のみを通過してそれ以外を減衰さ
せる中間周波フィルタを示す。この中間周波フィルタも
同調回路で構成される。８は出力端子を示す。2. Description of the Related Art First, a conventional television tuner is used.
Fig. 4 shows the basic configuration of the antenna. In the figure, 1 is an input terminal for receiving a received signal from the antenna, 2 is a tuning circuit or bandpass filter for passing only a desired signal from the received signal, and 3 is an amplifier circuit. 4 and 5
Denote a mixing circuit and a local oscillation circuit, respectively, which constitute the frequency conversion device 6. Reference numeral 7 denotes an intermediate frequency filter that passes only the desired signal and attenuates the rest of the frequency-converted signals. This intermediate frequency filter is also composed of a tuning circuit. Reference numeral 8 indicates an output terminal.
【０００３】このような構成のチュ−ナで、基本性能で
ある全体の利得（ＧT ）や雑音指数（ＦT ）は次の数
１，数２を用いて設定するようにしている。[0003] Ju thus configured - with Na, overall gain is a basic performance (G T) and noise figure (F T) are to be set using the following Equation 1, Equation 2.
【０００４】[0004]
【数１】ＧT ＝Ｇ1 ×Ｇ2 [Equation 1] G T = G 1 × G 2
【０００５】[0005]
【数２】ＦT ＝Ｆ1 ＋（Ｆ2 −１）／Ｇ1 ## EQU2 ## F T = F 1 + (F 2 -1) / G 1
【０００６】ここにＧ1 ，Ｆ1 は増幅回路３の利得と雑
音指数，Ｇ2 ，Ｆ2 は混合回路４の変換利得と雑音指数
である。（また、上記の式では同調回路２及び７の挿入
損失はないものと仮定している。）上記性能のうち利得
はテレビ受像機全体との兼ね合いから所定の値に設定さ
れ、しかもＧ1 とＧ2 の積で決定できるもので比較的設
計上の自由度がある。一方、雑音指数はその値が小さい
ほど優れたチュ−ナが得られるのでできるだけ雑音指数
の小さい増幅回路や混合回路を得る努力が払われてい
る。そのうえでさらに雑音指数を小さくするには数２か
ら明らかなように増幅回路３の利得Ｇ1 を大きくするこ
とが考えられる。一般には、Ｆ1 ＜Ｆ2 であるので増幅
回路３の利得Ｇ1 を大きくすることは全体の雑音指数を
小さく抑えるのに効果がある。Here, G 1 and F 1 are the gain and noise figure of the amplifier circuit 3, and G 2 and F 2 are the conversion gain and noise figure of the mixing circuit 4. (Also, in the above equation, it is assumed that there is no insertion loss of the tuning circuits 2 and 7.) Among the above performances, the gain is set to a predetermined value in consideration of the whole television receiver, and G 1 and It can be determined by the product of G 2 and has a relative degree of freedom in design. On the other hand, as the noise figure becomes smaller, a better tuner can be obtained. Therefore, efforts are being made to obtain an amplifier circuit or a mixing circuit having a noise figure as small as possible. In order to further reduce the noise figure, it is conceivable to increase the gain G 1 of the amplifier circuit 3 as is clear from the equation (2). In general, since F 1 <F 2 , increasing the gain G 1 of the amplifier circuit 3 is effective in suppressing the noise figure as a whole.
【０００７】しかし、増幅回路３の利得Ｇ1 を大きくす
ると、必然的に混合回路４に入力される信号レベルが大
きくなり、この結果混合回路４では受信の妨害となる歪
成分が発生する。この理由は、混合回路に使用する能動
素子が非直線特性を持っているためである。そのため従
来においては雑音指数ＦTを小さく抑える手段として増
幅回路３の利得Ｇ1 をむやみと大きくすることはせず、
雑音指数又は歪成分の大きさがいずれも極端に大きくな
らないように利得Ｇ1 を決めていた。尚、周波数変換装
置の入出力端６ａ，６ｂにおける信号と雑音のレベル関
係は次の数３，数４の通りになっている。However, when the gain G 1 of the amplifier circuit 3 is increased, the signal level input to the mixing circuit 4 is inevitably increased, and as a result, a distortion component that interferes with reception occurs in the mixing circuit 4. The reason for this is that the active elements used in the mixing circuit have non-linear characteristics. Therefore, conventionally, as a means for suppressing the noise figure F T to be small, the gain G 1 of the amplifier circuit 3 is not unnecessarily increased.
The gain G 1 is determined so that the noise figure or the magnitude of the distortion component does not become extremely large. The relationship between the signal level and the noise level at the input / output terminals 6a and 6b of the frequency conversion device is as shown in the following equations 3 and 4.
【０００８】[0008]
【数３】Ｐo ＝Ｐi Ｇ2 (3) P o = P i G 2
【０００９】[0009]
【数４】Ｎo ＝Ｎi Ｇ2 Ｆ2 (4) N o = N i G 2 F 2
【００１０】ここにＰo ，Ｎo はそれぞれ出力端６ｂに
おける信号レベルと雑音レベル，Ｐi Ｎi は入力端６ａ
における信号レベルと雑音レベルである。Here, P o and N o are the signal level and noise level at the output end 6b, respectively, and P i N i is the input end 6a.
Signal level and noise level at.
【００１１】図５は図４における混合回路４を接合型Ｆ
ＥＴ（電界効果トランジスタ）１個で構成した例を示
し、図６は４個の接合型ＦＥＴによっていわゆるダブル
バランスミキサを構成した例を示している。図において
６ａは信号入力端，６ｂは出力端，５ａは局部発振信号
の入力端をそれぞれ示し、４ａ〜４ｄは接合型ＦＥＴを
示す。FIG. 5 shows the mixing circuit 4 of FIG.
FIG. 6 shows an example in which one ET (field effect transistor) is used, and FIG. 6 shows an example in which a so-called double balance mixer is configured by four junction FETs. In the figure, 6a is a signal input terminal, 6b is an output terminal, 5a is a local oscillation signal input terminal, and 4a to 4d are junction FETs.
【００１２】[0012]
【発明が解決しようとする課題】以上のように、チュ−
ナの全体の雑音指数ＦT を小さくするために、増幅回路
３の利得Ｇ1 を大きくすれば混合回路４で発生する歪成
分が大きくなり、逆に歪成分を抑えようと利得Ｇ1 を小
さくすれば混合回路４の雑音指数Ｆ2 が全体の雑音指数
ＦT に影響を及ぼすことになる。そのため雑音指数と歪
特性を同時に改善することは不可能であった。本発明は
以上の問題を解決するものであり、その目的は全体の雑
音指数を大きくすることなく歪成分を小さく抑え得る周
波数変換装置を提供することにある。SUMMARY OF THE INVENTION As described above, the tu
If the gain G 1 of the amplifier circuit 3 is increased in order to reduce the overall noise figure F T of the antenna, the distortion component generated in the mixing circuit 4 increases, and conversely the gain G 1 is decreased to suppress the distortion component. Then, the noise figure F 2 of the mixing circuit 4 affects the overall noise figure F T. Therefore, it is impossible to improve the noise figure and distortion characteristics at the same time. The present invention solves the above problems, and an object of the present invention is to provide a frequency converter capable of suppressing the distortion component to a small value without increasing the overall noise figure.
【００１３】[0013]
【課題を解決するための手段】以上の目的を達成するた
め本発明においては、受信信号と局部発振信号とをそれ
ぞれ分配手段にて分配してＮ個（Ｎは２以上）の混合回
路に入力し、前記Ｎ個の混合回路から出力される前記２
つの信号の周波数の和又は差の信号を加算手段にて加算
して中間周波信号として取り出すようにした。In order to achieve the above object, according to the present invention, a reception signal and a local oscillation signal are distributed by distribution means and input to N (N is 2 or more) mixing circuits. The two output from the N mixing circuits.
The signal of the sum or difference of the frequencies of the two signals is added by the adding means so as to be taken out as an intermediate frequency signal.
【００１４】[0014]
【作用】前記手段によれば、個々の混合回路には受信信
号レベルが従来よりも１／Ｎに減衰されて入力される。
その結果個々の混合回路から出力される中間周波信号の
レベルは１／Ｎに下がるが、そこで発生する歪成分は１
／Ｎよりも小さくなる。従って、個々の混合回路の出力
を加算した場合、中間周波信号レベルは従来と同レベル
になり、又雑音レベルも同レベルとなる。一方歪成分は
従来よりも小さくなる。According to the above means, the received signal level is attenuated to 1 / N and inputted to each mixing circuit.
As a result, the level of the intermediate frequency signal output from each mixing circuit drops to 1 / N, but the distortion component generated there is 1
It becomes smaller than / N. Therefore, when the outputs of the individual mixing circuits are added, the intermediate frequency signal level becomes the same level as the conventional one, and the noise level also becomes the same level. On the other hand, the distortion component becomes smaller than before.
【００１５】[0015]
【実施例】図１に本発明の第１実施例に係る周波数変換
装置１１を示す。ここで１１ａ，１１ｂは入出力端子，
１５は局部発振回路，１３，１４は同一構成の混合回
路，１２，１６はそれぞれ信号分配手段としての分配回
路，１７は信号加算手段としての混合回路をそれぞれ示
す。次にこの周波数変換装置１１の動作について説明す
る。入力端子１１ａにおける受信信号と雑音のレベルを
Ｐi ，Ｎi とすると、個々の混合回路１３，１４の入力
側では受信信号及び雑音レベルはそれぞれＰi ／２，Ｎ
i ／2 となる。混合回路１３，１４の利得，雑音指数は
Ｇ2 Ｆ2 であるから、それぞれの混合回路１３，１４の
出力はＰi Ｇ2 ／２，Ｎi Ｇ2 Ｆ2 ／２となる。従っ
て、２つの混合回路１３，１４の出力を加え合わせると
信号レベルはＰi Ｇ2 ，雑音レベルはＮi Ｇ2 Ｆ2 とな
り、これは従来の混合回路を１個用いた構成と同じであ
ることがわかる。これは全体の利得ＧT と雑音指数ＦT
が従来と同じであることを示している。1 shows a frequency converter 11 according to a first embodiment of the present invention. Here, 11a and 11b are input / output terminals,
Reference numeral 15 is a local oscillation circuit, 13 and 14 are mixing circuits having the same configuration, 12 and 16 are distribution circuits as signal distribution means, and 17 is a mixing circuit as signal addition means. Next, the operation of the frequency conversion device 11 will be described. Assuming that the received signal and noise levels at the input terminal 11a are P i and N i , the received signal and noise levels at the input side of the individual mixing circuits 13 and 14 are P i / 2 and N, respectively.
i / 2. Gain of the mixing circuits 13 and 14, since the noise figure is a G 2 F 2, the output of each of the mixing circuits 13 and 14 becomes P i G 2/2, N i G 2 F 2/2. Therefore, when the outputs of the two mixing circuits 13 and 14 are added together, the signal level becomes P i G 2 and the noise level becomes N i G 2 F 2 , which is the same as the configuration using one conventional mixing circuit. I understand. This is the overall gain G T and noise figure F T
Is the same as the conventional one.
【００１６】次に混合回路１３，１４内で発生する歪成
分について詳述する。一般にトランジスタ，ＦＥＴ等の
能動素子は入出力間に非直線特性を有していることは前
述した通りであるが、今その特性を数５のように表して
みる。Next, the distortion component generated in the mixing circuits 13 and 14 will be described in detail. As described above, active elements such as transistors and FETs generally have a non-linear characteristic between input and output, but the characteristic will now be expressed as in Equation 5.
【００１７】[0017]
【数５】 ｅo ＝Ｋ1 ｅi ＋Ｋ2 ｅi 2 ＋Ｋ3 ｅi 3 ＋・・・[Equation 5] e o = K 1 e i + K 2 e i 2 + K 3 e i 3 + ...
【００１８】ここでｅo は混合回路の出力電圧，ｅi は
入力電圧である。今、入力電圧として受信信号α＝Ａｃ
ｏｓａと局部発振信号β＝Ｂｃｏｓｂの和を数５に代入
して計算すると、Ｋ2 ｅi 2 の項からは周波数変換され
た中間周波信号成分（２つの信号の周波数の和又は差の
成分）Ｋ2 ｅi 2 ＝Ｋ2 ＡＢｃｏｓ（ａ±ｂ）が得られ
るが、Ｋ3 ｅi 3 以後の高次項からは妨害となる歪成分
が生成される。その１例を示すと数６のようになる。Where e o is the output voltage of the mixing circuit and e i is the input voltage. Now, the received signal α = Ac as the input voltage
When the sum of osa and the local oscillation signal β = Bcosb is substituted into Equation 5, the frequency-converted intermediate frequency signal component (the sum or difference component of the frequencies of the two signals) is calculated from the term of K 2 e i 2. Although K 2 e i 2 = K 2 AB cos (a ± b) is obtained, a disturbing distortion component is generated from higher-order terms after K 3 e i 3 . If one example is shown, it becomes as shown in Expression 6.
【００１９】[0019]
【数６】 Ｋ3 ｅi 3 ＝Ｋ3 ｛Ａ3 （３ｃｏｓａ＋ｃｏｓ３ａ）／４＋３Ａ2 Ｂｃｏｓｂ （１＋ｃｏｓ２ａ／２＋３ＡＢ2 ｃｏｓａ（１＋ｃｏｓ２ｂ）／ ２＋Ｂ3 （３ｃｏｓｂ＋ｃｏｓ３ｂ）／４｝K 3 e i 3 = K 3 {A 3 (3cosa + cos3a) / 4 + 3A 2 Bcosb (1 + cos2a / 2 + 3AB 2 cosa (1 + cos2b) / 2 + B 3 (3cosb + cos3b) / 4}
【００２０】この式から明らかなように高次項から生成
される歪成分のレベルは入力電圧の振幅Ａ又はＢの３乗
に比例することがわかる。このことは入力信号及び局部
発振信号レベルが小さければ出力レベルは３乗に反比例
して小さくなることを示し、例えば入力信号を２分配し
て従来の１／２にした実施例では歪成分は従来の１／８
に低減し、２つの混合回路１３，１４からの出力を加算
しても従来の１／４に抑えられることがわかる。また入
力信号レベルが小さい場合は周波数変換するのに必要と
する局部発振信号のレベルもそれに応じて小さくして済
むので、局部発振信号に起因する歪成分も同様に小さく
抑えられる。以上のことを積極的に利用すれば増幅回路
３の利得Ｇ1 を若干大きくして全体の雑音指数ＮT を小
さくしたうえさらに混合回路全体で発生する歪成分を小
さく抑えることが可能となる。As is clear from this equation, the level of the distortion component generated from the higher order terms is proportional to the cube of the amplitude A or B of the input voltage. This means that if the input signal and the local oscillation signal level are low, the output level decreases in inverse proportion to the cube of the power. For example, in the embodiment in which the input signal is divided into two to be 1/2 of the conventional one, the distortion component is conventionally 1/8 of
It can be seen that even if the outputs from the two mixing circuits 13 and 14 are added, it can be suppressed to 1/4 of the conventional value. When the input signal level is low, the level of the local oscillation signal required for frequency conversion can be reduced accordingly, so that the distortion component caused by the local oscillation signal can also be suppressed to a small level. By positively utilizing the above, it is possible to slightly increase the gain G 1 of the amplifier circuit 3 to reduce the overall noise figure N T and further suppress the distortion component generated in the entire mixing circuit.
【００２１】図２は本発明の第２実施例を示す。本実施
例では混合回路１３，１４として接合型ＦＥＴ（電界効
果トランジスタ）をそれぞれ用いている。また本実施例
では分配，混合手段としての分配回路，混合回路を使用
せず、接続部１８，１９にてそれぞれ分配手段，混合手
段を構成している。また、図３は本発明の第３実施例を
示す。本実施例では接合型ＦＥＴ４個によるいわゆるダ
ブルバランスミキサが２回路並列に接続されている。同
図で接合型トランジスタ１３ａ〜１３ｄで構成される一
方のダブルバランスミキサが図１，２の混合回路１３に
相当し、接合型トランジスタ１４ａ〜１４ｄで構成され
る他方のダブルバランスミキサが図１，２の混合回路１
４に相当している。端子１１ａ，１１ａは信号入力端，
端子１１ｂ，１１ｂは出力端，端子１５ａ，１５ａは局
部発振信号の入力端である。また、本実施例では、端子
１１ａ，１５ａのトランジスタ１３ａ〜１３ｄ，１４ａ
〜１４ｄとの間の接続部がそれぞれ分配手段を構成して
おり、これらトランジスタと端子１１ｂとの間の接続部
がそれぞれ加算手段を構成している。FIG. 2 shows a second embodiment of the present invention. In this embodiment, junction type FETs (field effect transistors) are used as the mixing circuits 13 and 14, respectively. Further, in the present embodiment, the distribution circuit and the mixing circuit are not used as the distribution and mixing means, but the distribution means and the mixing means are constituted by the connecting portions 18 and 19, respectively. 3 shows a third embodiment of the present invention. In this embodiment, a so-called double balance mixer including four junction FETs is connected in parallel in two circuits. In the figure, one double-balanced mixer composed of junction type transistors 13a to 13d corresponds to the mixing circuit 13 in FIGS. 1 and 2, and the other double-balanced mixer composed of junction type transistors 14a to 14d is shown in FIG. Mixing circuit 1 of 2
It corresponds to 4. The terminals 11a and 11a are signal input terminals,
The terminals 11b and 11b are output terminals, and the terminals 15a and 15a are input terminals for a local oscillation signal. Further, in this embodiment, the transistors 13a to 13d and 14a of the terminals 11a and 15a are provided.
14d to 14d respectively constitute distribution means, and the connection between these transistors and the terminal 11b respectively constitutes addition means.
【００２２】以上の実施例では受信信号と局部発振信号
を２分配し、混合回路を２個用いた場合を説明したが、
本発明はこれのみに限られることはなく、一般的にＮ分
配してＮ個の混合回路を用いてもよい。また、Ｎの数を
増やすほど混合回路で発生する歪成分は小さくなること
は先に説明したことから明かである。また混合回路の数
を増やすことはコストに対して不利になると考えられる
が、チュ−ナ回路の集積回路化が進んでいる現在ではほ
とんどコスト的に影響は及ぼすことはない。また本発明
はダブルコンバ−ジョンチュ−ナの如く、入力非同調型
で同時に多数の入力信号が到来する方式のチュ−ナにも
適用でき、むしろこのような場合の方が歪成分の低減効
果は大きくなる。In the above embodiment, the case where the reception signal and the local oscillation signal are divided into two and two mixing circuits are used has been described.
The present invention is not limited to this, and in general, N distribution circuits may be used and N mixing circuits may be used. Further, it is apparent from the above that the distortion component generated in the mixing circuit becomes smaller as the number of N is increased. Further, it is considered that increasing the number of mixed circuits is disadvantageous to the cost, but at the present time when the tuner circuit is integrated into a circuit, it hardly affects the cost. The present invention can also be applied to a tuner of an input non-tuning type in which a large number of input signals arrive at the same time, such as a double conversion tuner. growing.
【００２３】[0023]
【発明の効果】以上のように本発明によれば雑音指数を
悪化させることなく従来に比して混合回路で発生する歪
成分を大幅に低減することができる。換言すれば歪成分
を同等レベルに維持すれば雑音指数を低減させることが
できる。従ってチュ−ナの基本性能である雑音指数と歪
を同時に改善することが可能となる。As described above, according to the present invention, the distortion component generated in the mixing circuit can be significantly reduced as compared with the conventional case without deteriorating the noise figure. In other words, if the distortion component is maintained at the same level, the noise figure can be reduced. Therefore, it is possible to simultaneously improve the noise figure and the distortion, which are the basic performances of the tuner.
【図１】本発明の第１実施例を示す周波数変換装置のブ
ロック図である。FIG. 1 is a block diagram of a frequency conversion device showing a first embodiment of the present invention.
【図２】本発明の第２実施例を示す具体的回路図であ
る。FIG. 2 is a specific circuit diagram showing a second embodiment of the present invention.
【図３】本発明の第３実施例を示す具体的回路図であ
る。FIG. 3 is a specific circuit diagram showing a third embodiment of the present invention.
【図４】従来の周波数変換装置を用いたチュ−ナのブロ
ック図である。FIG. 4 is a block diagram of a tuner using a conventional frequency conversion device.
【図５】従来の周波数変換装置の具体的回路図である。FIG. 5 is a specific circuit diagram of a conventional frequency conversion device.
【図６】従来の周波数変換装置の別の具体的回路図であ
る。FIG. 6 is another specific circuit diagram of the conventional frequency conversion device.
１１ 周波数変換装置 １２，１６ 分配回路（分配手段） １３，１４ 混合回路 １５ 局部発振回路 １７ 混合回路（加算手段） １８ 接続部（分配手段） １９ 接続部（分配手段） 11 Frequency Converter 12, 16 Distribution Circuit (Distribution Means) 13, 14 Mixing Circuit 15 Local Oscillation Circuit 17 Mixing Circuit (Adding Means) 18 Connection Part (Distribution Means) 19 Connection Part (Distribution Means)
Claims (1)
信号と局部発振信号をそれぞれ分配して前記Ｎ個の混合
に与える分配手段と、前記Ｎ個の混合回路からそれぞれ
出力される前記２つの信号の周波数の和又は差の信号を
加算して中間周波数信号として出力する加算手段とから
なる周波数変換装置。1. N (N is 2 or more) mixing circuits, distribution means for distributing a reception signal and a local oscillation signal to each of the N mixing circuits, and outputs from each of the N mixing circuits. And a signal of the sum or difference of the frequencies of the two signals that are added and output as an intermediate frequency signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27862291A JPH0595230A (en) | 1991-09-30 | 1991-09-30 | Frequency converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27862291A JPH0595230A (en) | 1991-09-30 | 1991-09-30 | Frequency converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0595230A true JPH0595230A (en) | 1993-04-16 |
Family
ID=17599848
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27862291A Pending JPH0595230A (en) | 1991-09-30 | 1991-09-30 | Frequency converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0595230A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11082074B2 (en) | 2015-12-16 | 2021-08-03 | Kumu Networks, Inc. | Systems and methods for linearized-mixer out-of-band interference mitigation |
| US11211969B2 (en) | 2017-03-27 | 2021-12-28 | Kumu Networks, Inc. | Enhanced linearity mixer |
-
1991
- 1991-09-30 JP JP27862291A patent/JPH0595230A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11082074B2 (en) | 2015-12-16 | 2021-08-03 | Kumu Networks, Inc. | Systems and methods for linearized-mixer out-of-band interference mitigation |
| US11671129B2 (en) | 2015-12-16 | 2023-06-06 | Kumu Networks, Inc. | Systems and methods for linearized-mixer out-of-band interference mitigation |
| US11211969B2 (en) | 2017-03-27 | 2021-12-28 | Kumu Networks, Inc. | Enhanced linearity mixer |
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